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Diffstat (limited to 'Documentation/devicetree/bindings')
8 files changed, 133 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/arm/freescale.txt b/Documentation/devicetree/bindings/arm/freescale.txt new file mode 100644 index 00000000000..8c52102b225 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale.txt @@ -0,0 +1,7 @@ +mx51 "Babbage" evalutation board +Required root node properties: + - compatible = "fsl,mx51-babbage", "fsl,mx51"; + +mx53 "Loco" evaluation board +Required root node properties: + - compatible = "fsl,mx53-loco", "fsl,mx53"; diff --git a/Documentation/devicetree/bindings/arm/genesi.txt b/Documentation/devicetree/bindings/arm/genesi.txt new file mode 100644 index 00000000000..b353489acd4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/genesi.txt @@ -0,0 +1,8 @@ +Genesi EfikaMX based on Freescale mx51 +Required root node properties: + - compatible = "genesi,efikamx", "fsl,mx51"; + +Genesi EfikaMX Smartbook based on Freescale mx51 +Required root node properties: + - compatible = "genesi,efikasb", "fsl,mx51"; + diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt new file mode 100644 index 00000000000..7ca52161e7a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -0,0 +1,44 @@ +* ARM L2 Cache Controller + +ARM cores often have a separate level 2 cache controller. There are various +implementations of the L2 cache controller with compatible programming models. +The ARM L2 cache representation in the device tree should be done as follows: + +Required properties: + +- compatible : should be one of: + "arm,pl310-cache" + "arm,l220-cache" + "arm,l210-cache" +- cache-unified : Specifies the cache is a unified cache. +- cache-level : Should be set to 2 for a level 2 cache. +- reg : Physical base address and size of cache controller's memory mapped + registers. + +Optional properties: + +- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of + read, write and setup latencies. Minimum valid values are 1. Controllers + without setup latency control should use a value of 0. +- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of + read, write and setup latencies. Controllers without setup latency control + should use 0. Controllers without separate read and write Tag RAM latency + values should only use the first cell. +- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. +- arm,filter-ranges : <start length> Starting address and length of window to + filter. Addresses in the filter window are directed to the M1 port. Other + addresses will go to the M0 port. +- interrupts : 1 combined interrupt. + +Example: + +L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + arm,filter-latency = <0x80000000 0x8000000>; + cache-unified; + cache-level = <2>; + interrupts = <45>; +}; diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt index 1d5d7a870ec..951ca46789d 100644 --- a/Documentation/devicetree/bindings/arm/primecell.txt +++ b/Documentation/devicetree/bindings/arm/primecell.txt @@ -6,7 +6,9 @@ driver matching. Required properties: -- compatible : should be a specific value for peripheral and "arm,primecell" +- compatible : should be a specific name for the peripheral and + "arm,primecell". The specific name will match the ARM + engineering name for the logic block in the form: "arm,pl???" Optional properties: diff --git a/Documentation/devicetree/bindings/arm/samsung.txt b/Documentation/devicetree/bindings/arm/samsung.txt new file mode 100644 index 00000000000..594cb97e3d8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung.txt @@ -0,0 +1,9 @@ +Samsung Exynos4 S5PV310 SoC based SMDKV310 eval board + + SMDKV310 eval board is based on S5PV310 SoC which belongs to + Samsung's Exynos4 family of application processors. + +Required root node properties: + - compatible = "samsung,smdkv310","samsung,s5pv310" + (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. + (b) "samsung,s5pv310" - for boards based on S5PV310 SoC. diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt new file mode 100644 index 00000000000..a2c416bcbcc --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt @@ -0,0 +1,10 @@ +ARM PL061 GPIO controller + +Required properties: +- compatible : "arm,pl061", "arm,primecell" +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters: + - bit 0 specifies polarity (0 for normal, 1 for inverted) +- gpio-controller : Marks the device node as a GPIO controller. +- interrupts : Interrupt mapping for GPIO IRQ. + diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt new file mode 100644 index 00000000000..306ec3ff3c0 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt @@ -0,0 +1,12 @@ +ARM PL022 SPI controller + +Required properties: +- compatible : "arm,pl022", "arm,primecell" +- reg : Offset and length of the register set for the device +- interrupts : Should contain SPI controller interrupt + +Optional properties: +- cs-gpios : should specify GPIOs used for chipselects. + The gpios will be referred to as reg = <index> in the SPI child nodes. + If unspecified, a single SPI device without a chip select can be used. + diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt new file mode 100644 index 00000000000..e8552782b44 --- /dev/null +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -0,0 +1,40 @@ +Device tree binding vendor prefix registry. Keep list in alphabetical order. + +This isn't an exhaustive list, but you should add new prefixes to it before +using them to avoid name-space collisions. + +adi Analog Devices, Inc. +amcc Applied Micro Circuits Corporation (APM, formally AMCC) +apm Applied Micro Circuits Corporation (APM) +arm ARM Ltd. +atmel Atmel Corporation +chrp Common Hardware Reference Platform +dallas Maxim Integrated Products (formerly Dallas Semiconductor) +denx Denx Software Engineering +epson Seiko Epson Corp. +est ESTeem Wireless Modems +fsl Freescale Semiconductor +GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. +gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. +hp Hewlett Packard +ibm International Business Machines (IBM) +idt Integrated Device Technologies, Inc. +intercontrol Inter Control Group +linux Linux-specific binding +marvell Marvell Technology Group Ltd. +maxim Maxim Integrated Products +mosaixtech Mosaix Technologies, Inc. +national National Semiconductor +nintendo Nintendo +nvidia NVIDIA +nxp NXP Semiconductors +powervr Imagination Technologies +qcom Qualcomm, Inc. +ramtron Ramtron International +samsung Samsung Semiconductor +schindler Schindler +simtek +sirf SiRF Technology, Inc. +stericsson ST-Ericsson +ti Texas Instruments +xlnx Xilinx |