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config DBX500_PRCMU_QOS_POWER
	bool "DBX500 PRCMU power QoS support"
	depends on (MFD_DB5500_PRCMU || MFD_DB8500_PRCMU)
	default y
	help
	  Add support for PRCMU power Quality of Service

config UX500_CONTEXT
	bool "Context save/restore support for UX500"
	depends on (UX500_SOC_DB8500 || UX500_SOC_DB5500) && PM
	help
	  This is needed for ApSleep and deeper sleep states.

config UX500_PM_PERFORMANCE
	bool "Performance supervision"
	depends on DBX500_PRCMU_QOS_POWER
	default y
	help
	  Enable supervision of events which may require a boost
	  of platform performance.

config UX500_CONSOLE_UART_GPIO_PIN
	int "The pin number of the console UART GPIO pin"
	default 29
	depends on UX500_SUSPEND_DBG_WAKE_ON_UART || UX500_CPUIDLE_DEBUG
	help
	  GPIO pin number of the GPIO pin connected to the console UART RX line.

	  Board-specific code can change this.

config UX500_SUSPEND
	bool "Suspend to mem and standby support"
	depends on (UX500_SOC_DB8500 || UX500_SOC_DB5500) && PM && SUSPEND
	select UX500_CONTEXT
	help
	  Add support for suspend.

config UX500_SUSPEND_STANDBY
	bool "Suspend Standby goes to ApSleep"
	depends on UX500_SUSPEND
	help
	  If yes, echo standby > /sys/power/state puts the system into ApSleep.

config UX500_SUSPEND_MEM
	bool "Suspend Mem goes to ApDeepSleep"
	depends on UX500_SUSPEND
	help
	  If yes, echo mem > /sys/power/state puts the system into ApDeepSleep else
	  it will do the same as echo standby > /sys/power/state.

config UX500_SUSPEND_DBG
	bool "Suspend debug"
	depends on UX500_SUSPEND && DEBUG_FS
	help
	  Add debug support for suspend.

config UX500_SUSPEND_DBG_WAKE_ON_UART
	bool "Suspend wakes on console UART"
	depends on UX500_SUSPEND_DBG
	help
	  Wake up on uart interrupts. Makes it possible for the console to wake up system.

config UX500_USECASE_GOVERNOR
	bool "UX500 use-case governor"
	depends on (UX500_SOC_DB8500 || UX500_SOC_DB5500) && \
			(CPU_FREQ && CPU_IDLE && HOTPLUG_CPU && \
			EARLYSUSPEND && UX500_L2X0_PREFETCH_CTRL && PM)
	default y
	help
	  Adjusts CPU_IDLE, CPU_FREQ, HOTPLUG_CPU and L2 cache parameters