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|
/*
* ALSA SoC OMAP ABE driver
*
* Author: Laurent Le Faucheur <l-le-faucheur@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef _ABE_SM_ADDR_H_
#define _ABE_SM_ADDR_H_
#define init_SM_ADDR 0
#define init_SM_ADDR_END 309
#define init_SM_sizeof 310
#define S_Data0_ADDR 310
#define S_Data0_ADDR_END 310
#define S_Data0_sizeof 1
#define S_Temp_ADDR 311
#define S_Temp_ADDR_END 311
#define S_Temp_sizeof 1
#define S_PhoenixOffset_ADDR 312
#define S_PhoenixOffset_ADDR_END 312
#define S_PhoenixOffset_sizeof 1
#define S_GTarget1_ADDR 313
#define S_GTarget1_ADDR_END 319
#define S_GTarget1_sizeof 7
#define S_Gtarget_DL1_ADDR 320
#define S_Gtarget_DL1_ADDR_END 321
#define S_Gtarget_DL1_sizeof 2
#define S_Gtarget_DL2_ADDR 322
#define S_Gtarget_DL2_ADDR_END 323
#define S_Gtarget_DL2_sizeof 2
#define S_Gtarget_Echo_ADDR 324
#define S_Gtarget_Echo_ADDR_END 324
#define S_Gtarget_Echo_sizeof 1
#define S_Gtarget_SDT_ADDR 325
#define S_Gtarget_SDT_ADDR_END 325
#define S_Gtarget_SDT_sizeof 1
#define S_Gtarget_VxRec_ADDR 326
#define S_Gtarget_VxRec_ADDR_END 327
#define S_Gtarget_VxRec_sizeof 2
#define S_Gtarget_UL_ADDR 328
#define S_Gtarget_UL_ADDR_END 329
#define S_Gtarget_UL_sizeof 2
#define S_Gtarget_unused_ADDR 330
#define S_Gtarget_unused_ADDR_END 330
#define S_Gtarget_unused_sizeof 1
#define S_GCurrent_ADDR 331
#define S_GCurrent_ADDR_END 348
#define S_GCurrent_sizeof 18
#define S_GAIN_ONE_ADDR 349
#define S_GAIN_ONE_ADDR_END 349
#define S_GAIN_ONE_sizeof 1
#define S_Tones_ADDR 350
#define S_Tones_ADDR_END 361
#define S_Tones_sizeof 12
#define S_VX_DL_ADDR 362
#define S_VX_DL_ADDR_END 373
#define S_VX_DL_sizeof 12
#define S_MM_UL2_ADDR 374
#define S_MM_UL2_ADDR_END 385
#define S_MM_UL2_sizeof 12
#define S_MM_DL_ADDR 386
#define S_MM_DL_ADDR_END 397
#define S_MM_DL_sizeof 12
#define S_DL1_M_Out_ADDR 398
#define S_DL1_M_Out_ADDR_END 409
#define S_DL1_M_Out_sizeof 12
#define S_DL2_M_Out_ADDR 410
#define S_DL2_M_Out_ADDR_END 421
#define S_DL2_M_Out_sizeof 12
#define S_Echo_M_Out_ADDR 422
#define S_Echo_M_Out_ADDR_END 433
#define S_Echo_M_Out_sizeof 12
#define S_SDT_M_Out_ADDR 434
#define S_SDT_M_Out_ADDR_END 445
#define S_SDT_M_Out_sizeof 12
#define S_VX_UL_ADDR 446
#define S_VX_UL_ADDR_END 457
#define S_VX_UL_sizeof 12
#define S_VX_UL_M_ADDR 458
#define S_VX_UL_M_ADDR_END 469
#define S_VX_UL_M_sizeof 12
#define S_BT_DL_ADDR 470
#define S_BT_DL_ADDR_END 481
#define S_BT_DL_sizeof 12
#define S_BT_UL_ADDR 482
#define S_BT_UL_ADDR_END 493
#define S_BT_UL_sizeof 12
#define S_BT_DL_8k_ADDR 494
#define S_BT_DL_8k_ADDR_END 496
#define S_BT_DL_8k_sizeof 3
#define S_BT_DL_16k_ADDR 497
#define S_BT_DL_16k_ADDR_END 501
#define S_BT_DL_16k_sizeof 5
#define S_BT_UL_8k_ADDR 502
#define S_BT_UL_8k_ADDR_END 503
#define S_BT_UL_8k_sizeof 2
#define S_BT_UL_16k_ADDR 504
#define S_BT_UL_16k_ADDR_END 507
#define S_BT_UL_16k_sizeof 4
#define S_SDT_F_ADDR 508
#define S_SDT_F_ADDR_END 519
#define S_SDT_F_sizeof 12
#define S_SDT_F_data_ADDR 520
#define S_SDT_F_data_ADDR_END 528
#define S_SDT_F_data_sizeof 9
#define S_MM_DL_OSR_ADDR 529
#define S_MM_DL_OSR_ADDR_END 552
#define S_MM_DL_OSR_sizeof 24
#define S_24_zeros_ADDR 553
#define S_24_zeros_ADDR_END 576
#define S_24_zeros_sizeof 24
#define S_DMIC1_ADDR 577
#define S_DMIC1_ADDR_END 588
#define S_DMIC1_sizeof 12
#define S_DMIC2_ADDR 589
#define S_DMIC2_ADDR_END 600
#define S_DMIC2_sizeof 12
#define S_DMIC3_ADDR 601
#define S_DMIC3_ADDR_END 612
#define S_DMIC3_sizeof 12
#define S_AMIC_ADDR 613
#define S_AMIC_ADDR_END 624
#define S_AMIC_sizeof 12
#define S_DMIC1_L_ADDR 625
#define S_DMIC1_L_ADDR_END 636
#define S_DMIC1_L_sizeof 12
#define S_DMIC1_R_ADDR 637
#define S_DMIC1_R_ADDR_END 648
#define S_DMIC1_R_sizeof 12
#define S_DMIC2_L_ADDR 649
#define S_DMIC2_L_ADDR_END 660
#define S_DMIC2_L_sizeof 12
#define S_DMIC2_R_ADDR 661
#define S_DMIC2_R_ADDR_END 672
#define S_DMIC2_R_sizeof 12
#define S_DMIC3_L_ADDR 673
#define S_DMIC3_L_ADDR_END 684
#define S_DMIC3_L_sizeof 12
#define S_DMIC3_R_ADDR 685
#define S_DMIC3_R_ADDR_END 696
#define S_DMIC3_R_sizeof 12
#define S_BT_UL_L_ADDR 697
#define S_BT_UL_L_ADDR_END 708
#define S_BT_UL_L_sizeof 12
#define S_BT_UL_R_ADDR 709
#define S_BT_UL_R_ADDR_END 720
#define S_BT_UL_R_sizeof 12
#define S_AMIC_L_ADDR 721
#define S_AMIC_L_ADDR_END 732
#define S_AMIC_L_sizeof 12
#define S_AMIC_R_ADDR 733
#define S_AMIC_R_ADDR_END 744
#define S_AMIC_R_sizeof 12
#define S_EchoRef_L_ADDR 745
#define S_EchoRef_L_ADDR_END 756
#define S_EchoRef_L_sizeof 12
#define S_EchoRef_R_ADDR 757
#define S_EchoRef_R_ADDR_END 768
#define S_EchoRef_R_sizeof 12
#define S_MM_DL_L_ADDR 769
#define S_MM_DL_L_ADDR_END 780
#define S_MM_DL_L_sizeof 12
#define S_MM_DL_R_ADDR 781
#define S_MM_DL_R_ADDR_END 792
#define S_MM_DL_R_sizeof 12
#define S_MM_UL_ADDR 793
#define S_MM_UL_ADDR_END 912
#define S_MM_UL_sizeof 120
#define S_AMIC_96k_ADDR 913
#define S_AMIC_96k_ADDR_END 936
#define S_AMIC_96k_sizeof 24
#define S_DMIC0_96k_ADDR 937
#define S_DMIC0_96k_ADDR_END 960
#define S_DMIC0_96k_sizeof 24
#define S_DMIC1_96k_ADDR 961
#define S_DMIC1_96k_ADDR_END 984
#define S_DMIC1_96k_sizeof 24
#define S_DMIC2_96k_ADDR 985
#define S_DMIC2_96k_ADDR_END 1008
#define S_DMIC2_96k_sizeof 24
#define S_UL_VX_UL_48_8K_ADDR 1009
#define S_UL_VX_UL_48_8K_ADDR_END 1020
#define S_UL_VX_UL_48_8K_sizeof 12
#define S_UL_VX_UL_48_16K_ADDR 1021
#define S_UL_VX_UL_48_16K_ADDR_END 1032
#define S_UL_VX_UL_48_16K_sizeof 12
#define S_UL_MIC_48K_ADDR 1033
#define S_UL_MIC_48K_ADDR_END 1044
#define S_UL_MIC_48K_sizeof 12
#define S_Voice_8k_UL_ADDR 1045
#define S_Voice_8k_UL_ADDR_END 1047
#define S_Voice_8k_UL_sizeof 3
#define S_Voice_8k_DL_ADDR 1048
#define S_Voice_8k_DL_ADDR_END 1049
#define S_Voice_8k_DL_sizeof 2
#define S_McPDM_Out1_ADDR 1050
#define S_McPDM_Out1_ADDR_END 1073
#define S_McPDM_Out1_sizeof 24
#define S_McPDM_Out2_ADDR 1074
#define S_McPDM_Out2_ADDR_END 1097
#define S_McPDM_Out2_sizeof 24
#define S_McPDM_Out3_ADDR 1098
#define S_McPDM_Out3_ADDR_END 1121
#define S_McPDM_Out3_sizeof 24
#define S_Voice_16k_UL_ADDR 1122
#define S_Voice_16k_UL_ADDR_END 1126
#define S_Voice_16k_UL_sizeof 5
#define S_Voice_16k_DL_ADDR 1127
#define S_Voice_16k_DL_ADDR_END 1130
#define S_Voice_16k_DL_sizeof 4
#define S_XinASRC_DL_VX_ADDR 1131
#define S_XinASRC_DL_VX_ADDR_END 1170
#define S_XinASRC_DL_VX_sizeof 40
#define S_XinASRC_UL_VX_ADDR 1171
#define S_XinASRC_UL_VX_ADDR_END 1210
#define S_XinASRC_UL_VX_sizeof 40
#define S_XinASRC_MM_EXT_IN_ADDR 1211
#define S_XinASRC_MM_EXT_IN_ADDR_END 1250
#define S_XinASRC_MM_EXT_IN_sizeof 40
#define S_VX_REC_ADDR 1251
#define S_VX_REC_ADDR_END 1262
#define S_VX_REC_sizeof 12
#define S_VX_REC_L_ADDR 1263
#define S_VX_REC_L_ADDR_END 1274
#define S_VX_REC_L_sizeof 12
#define S_VX_REC_R_ADDR 1275
#define S_VX_REC_R_ADDR_END 1286
#define S_VX_REC_R_sizeof 12
#define S_DL2_M_L_ADDR 1287
#define S_DL2_M_L_ADDR_END 1298
#define S_DL2_M_L_sizeof 12
#define S_DL2_M_R_ADDR 1299
#define S_DL2_M_R_ADDR_END 1310
#define S_DL2_M_R_sizeof 12
#define S_DL2_M_LR_EQ_data_ADDR 1311
#define S_DL2_M_LR_EQ_data_ADDR_END 1335
#define S_DL2_M_LR_EQ_data_sizeof 25
#define S_DL1_M_EQ_data_ADDR 1336
#define S_DL1_M_EQ_data_ADDR_END 1360
#define S_DL1_M_EQ_data_sizeof 25
#define S_EARP_48_96_LP_data_ADDR 1361
#define S_EARP_48_96_LP_data_ADDR_END 1375
#define S_EARP_48_96_LP_data_sizeof 15
#define S_IHF_48_96_LP_data_ADDR 1376
#define S_IHF_48_96_LP_data_ADDR_END 1390
#define S_IHF_48_96_LP_data_sizeof 15
#define S_VX_UL_8_TEMP_ADDR 1391
#define S_VX_UL_8_TEMP_ADDR_END 1392
#define S_VX_UL_8_TEMP_sizeof 2
#define S_VX_UL_16_TEMP_ADDR 1393
#define S_VX_UL_16_TEMP_ADDR_END 1396
#define S_VX_UL_16_TEMP_sizeof 4
#define S_VX_DL_8_48_LP_data_ADDR 1397
#define S_VX_DL_8_48_LP_data_ADDR_END 1407
#define S_VX_DL_8_48_LP_data_sizeof 11
#define S_VX_DL_8_48_HP_data_ADDR 1408
#define S_VX_DL_8_48_HP_data_ADDR_END 1414
#define S_VX_DL_8_48_HP_data_sizeof 7
#define S_VX_DL_16_48_LP_data_ADDR 1415
#define S_VX_DL_16_48_LP_data_ADDR_END 1425
#define S_VX_DL_16_48_LP_data_sizeof 11
#define S_VX_DL_16_48_HP_data_ADDR 1426
#define S_VX_DL_16_48_HP_data_ADDR_END 1430
#define S_VX_DL_16_48_HP_data_sizeof 5
#define S_VX_UL_48_8_LP_data_ADDR 1431
#define S_VX_UL_48_8_LP_data_ADDR_END 1441
#define S_VX_UL_48_8_LP_data_sizeof 11
#define S_VX_UL_48_8_HP_data_ADDR 1442
#define S_VX_UL_48_8_HP_data_ADDR_END 1448
#define S_VX_UL_48_8_HP_data_sizeof 7
#define S_VX_UL_48_16_LP_data_ADDR 1449
#define S_VX_UL_48_16_LP_data_ADDR_END 1459
#define S_VX_UL_48_16_LP_data_sizeof 11
#define S_VX_UL_48_16_HP_data_ADDR 1460
#define S_VX_UL_48_16_HP_data_ADDR_END 1466
#define S_VX_UL_48_16_HP_data_sizeof 7
#define S_BT_UL_8_48_LP_data_ADDR 1467
#define S_BT_UL_8_48_LP_data_ADDR_END 1477
#define S_BT_UL_8_48_LP_data_sizeof 11
#define S_BT_UL_8_48_HP_data_ADDR 1478
#define S_BT_UL_8_48_HP_data_ADDR_END 1484
#define S_BT_UL_8_48_HP_data_sizeof 7
#define S_BT_UL_16_48_LP_data_ADDR 1485
#define S_BT_UL_16_48_LP_data_ADDR_END 1495
#define S_BT_UL_16_48_LP_data_sizeof 11
#define S_BT_UL_16_48_HP_data_ADDR 1496
#define S_BT_UL_16_48_HP_data_ADDR_END 1500
#define S_BT_UL_16_48_HP_data_sizeof 5
#define S_BT_DL_48_8_LP_data_ADDR 1501
#define S_BT_DL_48_8_LP_data_ADDR_END 1511
#define S_BT_DL_48_8_LP_data_sizeof 11
#define S_BT_DL_48_8_HP_data_ADDR 1512
#define S_BT_DL_48_8_HP_data_ADDR_END 1518
#define S_BT_DL_48_8_HP_data_sizeof 7
#define S_BT_DL_48_16_LP_data_ADDR 1519
#define S_BT_DL_48_16_LP_data_ADDR_END 1529
#define S_BT_DL_48_16_LP_data_sizeof 11
#define S_BT_DL_48_16_HP_data_ADDR 1530
#define S_BT_DL_48_16_HP_data_ADDR_END 1534
#define S_BT_DL_48_16_HP_data_sizeof 5
#define S_ECHO_REF_48_8_LP_data_ADDR 1535
#define S_ECHO_REF_48_8_LP_data_ADDR_END 1545
#define S_ECHO_REF_48_8_LP_data_sizeof 11
#define S_ECHO_REF_48_8_HP_data_ADDR 1546
#define S_ECHO_REF_48_8_HP_data_ADDR_END 1552
#define S_ECHO_REF_48_8_HP_data_sizeof 7
#define S_ECHO_REF_48_16_LP_data_ADDR 1553
#define S_ECHO_REF_48_16_LP_data_ADDR_END 1563
#define S_ECHO_REF_48_16_LP_data_sizeof 11
#define S_ECHO_REF_48_16_HP_data_ADDR 1564
#define S_ECHO_REF_48_16_HP_data_ADDR_END 1568
#define S_ECHO_REF_48_16_HP_data_sizeof 5
#define S_APS_IIRmem1_ADDR 1569
#define S_APS_IIRmem1_ADDR_END 1577
#define S_APS_IIRmem1_sizeof 9
#define S_APS_M_IIRmem2_ADDR 1578
#define S_APS_M_IIRmem2_ADDR_END 1580
#define S_APS_M_IIRmem2_sizeof 3
#define S_APS_C_IIRmem2_ADDR 1581
#define S_APS_C_IIRmem2_ADDR_END 1583
#define S_APS_C_IIRmem2_sizeof 3
#define S_APS_DL1_OutSamples_ADDR 1584
#define S_APS_DL1_OutSamples_ADDR_END 1585
#define S_APS_DL1_OutSamples_sizeof 2
#define S_APS_DL1_COIL_OutSamples_ADDR 1586
#define S_APS_DL1_COIL_OutSamples_ADDR_END 1587
#define S_APS_DL1_COIL_OutSamples_sizeof 2
#define S_APS_DL2_L_OutSamples_ADDR 1588
#define S_APS_DL2_L_OutSamples_ADDR_END 1589
#define S_APS_DL2_L_OutSamples_sizeof 2
#define S_APS_DL2_L_COIL_OutSamples_ADDR 1590
#define S_APS_DL2_L_COIL_OutSamples_ADDR_END 1591
#define S_APS_DL2_L_COIL_OutSamples_sizeof 2
#define S_APS_DL2_R_OutSamples_ADDR 1592
#define S_APS_DL2_R_OutSamples_ADDR_END 1593
#define S_APS_DL2_R_OutSamples_sizeof 2
#define S_APS_DL2_R_COIL_OutSamples_ADDR 1594
#define S_APS_DL2_R_COIL_OutSamples_ADDR_END 1595
#define S_APS_DL2_R_COIL_OutSamples_sizeof 2
#define S_XinASRC_ECHO_REF_ADDR 1596
#define S_XinASRC_ECHO_REF_ADDR_END 1635
#define S_XinASRC_ECHO_REF_sizeof 40
#define S_ECHO_REF_16K_ADDR 1636
#define S_ECHO_REF_16K_ADDR_END 1640
#define S_ECHO_REF_16K_sizeof 5
#define S_ECHO_REF_8K_ADDR 1641
#define S_ECHO_REF_8K_ADDR_END 1643
#define S_ECHO_REF_8K_sizeof 3
#define S_DL1_EQ_ADDR 1644
#define S_DL1_EQ_ADDR_END 1655
#define S_DL1_EQ_sizeof 12
#define S_DL2_EQ_ADDR 1656
#define S_DL2_EQ_ADDR_END 1667
#define S_DL2_EQ_sizeof 12
#define S_DL1_GAIN_out_ADDR 1668
#define S_DL1_GAIN_out_ADDR_END 1679
#define S_DL1_GAIN_out_sizeof 12
#define S_DL2_GAIN_out_ADDR 1680
#define S_DL2_GAIN_out_ADDR_END 1691
#define S_DL2_GAIN_out_sizeof 12
#define S_APS_DL2_L_IIRmem1_ADDR 1692
#define S_APS_DL2_L_IIRmem1_ADDR_END 1700
#define S_APS_DL2_L_IIRmem1_sizeof 9
#define S_APS_DL2_R_IIRmem1_ADDR 1701
#define S_APS_DL2_R_IIRmem1_ADDR_END 1709
#define S_APS_DL2_R_IIRmem1_sizeof 9
#define S_APS_DL2_L_M_IIRmem2_ADDR 1710
#define S_APS_DL2_L_M_IIRmem2_ADDR_END 1712
#define S_APS_DL2_L_M_IIRmem2_sizeof 3
#define S_APS_DL2_R_M_IIRmem2_ADDR 1713
#define S_APS_DL2_R_M_IIRmem2_ADDR_END 1715
#define S_APS_DL2_R_M_IIRmem2_sizeof 3
#define S_APS_DL2_L_C_IIRmem2_ADDR 1716
#define S_APS_DL2_L_C_IIRmem2_ADDR_END 1718
#define S_APS_DL2_L_C_IIRmem2_sizeof 3
#define S_APS_DL2_R_C_IIRmem2_ADDR 1719
#define S_APS_DL2_R_C_IIRmem2_ADDR_END 1721
#define S_APS_DL2_R_C_IIRmem2_sizeof 3
#define S_DL1_APS_ADDR 1722
#define S_DL1_APS_ADDR_END 1733
#define S_DL1_APS_sizeof 12
#define S_DL2_L_APS_ADDR 1734
#define S_DL2_L_APS_ADDR_END 1745
#define S_DL2_L_APS_sizeof 12
#define S_DL2_R_APS_ADDR 1746
#define S_DL2_R_APS_ADDR_END 1757
#define S_DL2_R_APS_sizeof 12
#define S_APS_DL1_EQ_data_ADDR 1758
#define S_APS_DL1_EQ_data_ADDR_END 1766
#define S_APS_DL1_EQ_data_sizeof 9
#define S_APS_DL2_EQ_data_ADDR 1767
#define S_APS_DL2_EQ_data_ADDR_END 1775
#define S_APS_DL2_EQ_data_sizeof 9
#define S_DC_DCvalue_ADDR 1776
#define S_DC_DCvalue_ADDR_END 1776
#define S_DC_DCvalue_sizeof 1
#define S_VIBRA_ADDR 1777
#define S_VIBRA_ADDR_END 1782
#define S_VIBRA_sizeof 6
#define S_Vibra2_in_ADDR 1783
#define S_Vibra2_in_ADDR_END 1788
#define S_Vibra2_in_sizeof 6
#define S_Vibra2_addr_ADDR 1789
#define S_Vibra2_addr_ADDR_END 1789
#define S_Vibra2_addr_sizeof 1
#define S_VibraCtrl_forRightSM_ADDR 1790
#define S_VibraCtrl_forRightSM_ADDR_END 1813
#define S_VibraCtrl_forRightSM_sizeof 24
#define S_Rnoise_mem_ADDR 1814
#define S_Rnoise_mem_ADDR_END 1814
#define S_Rnoise_mem_sizeof 1
#define S_Ctrl_ADDR 1815
#define S_Ctrl_ADDR_END 1832
#define S_Ctrl_sizeof 18
#define S_Vibra1_in_ADDR 1833
#define S_Vibra1_in_ADDR_END 1838
#define S_Vibra1_in_sizeof 6
#define S_Vibra1_temp_ADDR 1839
#define S_Vibra1_temp_ADDR_END 1862
#define S_Vibra1_temp_sizeof 24
#define S_VibraCtrl_forLeftSM_ADDR 1863
#define S_VibraCtrl_forLeftSM_ADDR_END 1886
#define S_VibraCtrl_forLeftSM_sizeof 24
#define S_Vibra1_mem_ADDR 1887
#define S_Vibra1_mem_ADDR_END 1897
#define S_Vibra1_mem_sizeof 11
#define S_VibraCtrl_Stereo_ADDR 1898
#define S_VibraCtrl_Stereo_ADDR_END 1921
#define S_VibraCtrl_Stereo_sizeof 24
#define S_AMIC_96_48_data_ADDR 1922
#define S_AMIC_96_48_data_ADDR_END 1940
#define S_AMIC_96_48_data_sizeof 19
#define S_DMIC0_96_48_data_ADDR 1941
#define S_DMIC0_96_48_data_ADDR_END 1959
#define S_DMIC0_96_48_data_sizeof 19
#define S_DMIC1_96_48_data_ADDR 1960
#define S_DMIC1_96_48_data_ADDR_END 1978
#define S_DMIC1_96_48_data_sizeof 19
#define S_DMIC2_96_48_data_ADDR 1979
#define S_DMIC2_96_48_data_ADDR_END 1997
#define S_DMIC2_96_48_data_sizeof 19
#define S_DBG_8K_PATTERN_ADDR 1998
#define S_DBG_8K_PATTERN_ADDR_END 1999
#define S_DBG_8K_PATTERN_sizeof 2
#define S_DBG_16K_PATTERN_ADDR 2000
#define S_DBG_16K_PATTERN_ADDR_END 2003
#define S_DBG_16K_PATTERN_sizeof 4
#define S_DBG_24K_PATTERN_ADDR 2004
#define S_DBG_24K_PATTERN_ADDR_END 2009
#define S_DBG_24K_PATTERN_sizeof 6
#define S_DBG_48K_PATTERN_ADDR 2010
#define S_DBG_48K_PATTERN_ADDR_END 2021
#define S_DBG_48K_PATTERN_sizeof 12
#define S_DBG_96K_PATTERN_ADDR 2022
#define S_DBG_96K_PATTERN_ADDR_END 2045
#define S_DBG_96K_PATTERN_sizeof 24
#define S_MM_EXT_IN_ADDR 2046
#define S_MM_EXT_IN_ADDR_END 2057
#define S_MM_EXT_IN_sizeof 12
#define S_MM_EXT_IN_L_ADDR 2058
#define S_MM_EXT_IN_L_ADDR_END 2069
#define S_MM_EXT_IN_L_sizeof 12
#define S_MM_EXT_IN_R_ADDR 2070
#define S_MM_EXT_IN_R_ADDR_END 2081
#define S_MM_EXT_IN_R_sizeof 12
#define S_MIC4_ADDR 2082
#define S_MIC4_ADDR_END 2093
#define S_MIC4_sizeof 12
#define S_MIC4_L_ADDR 2094
#define S_MIC4_L_ADDR_END 2105
#define S_MIC4_L_sizeof 12
#define S_MIC4_R_ADDR 2106
#define S_MIC4_R_ADDR_END 2117
#define S_MIC4_R_sizeof 12
#define S_HW_TEST_ADDR 2118
#define S_HW_TEST_ADDR_END 2118
#define S_HW_TEST_sizeof 1
#define S_XinASRC_BT_UL_ADDR 2119
#define S_XinASRC_BT_UL_ADDR_END 2158
#define S_XinASRC_BT_UL_sizeof 40
#define S_XinASRC_BT_DL_ADDR 2159
#define S_XinASRC_BT_DL_ADDR_END 2198
#define S_XinASRC_BT_DL_sizeof 40
#define S_BT_DL_8k_TEMP_ADDR 2199
#define S_BT_DL_8k_TEMP_ADDR_END 2200
#define S_BT_DL_8k_TEMP_sizeof 2
#define S_BT_DL_16k_TEMP_ADDR 2201
#define S_BT_DL_16k_TEMP_ADDR_END 2204
#define S_BT_DL_16k_TEMP_sizeof 4
#endif/* _ABESM_ADDR_H_ */
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