Porting architecture portion of av8100 driver from .35 to .38

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

11 files changed, 1626 insertions, 0 deletions

diff --git a/include/video/av8100.h b/include/video/av8100.h
new file mode 100644
index 00000000000..2cec097c73d
--- /dev/null
+++ b/include/video/av8100.h
@@ -0,0 +1,561 @@
+/*
+ * Copyright (C) ST-Ericsson AB 2010
+ *
+ * AV8100 driver
+ *
+ * Author: Per Persson <per.xb.persson@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __AV8100__H__
+#define __AV8100__H__
+
+#define AV8100_CEC_MESSAGE_SIZE		16
+#define AV8100_HDCP_SEND_KEY_SIZE	16
+#define AV8100_INFOFRAME_SIZE		28
+#define AV8100_FUSE_KEY_SIZE		16
+#define AV8100_CHIPVER_1		1
+#define AV8100_CHIPVER_2		2
+
+struct av8100_platform_data {
+	unsigned	gpio_base;
+	int		irq;
+	int		reset;
+	const char	*inputclk_id;
+	const char	*regulator_pwr_id;
+};
+
+enum av8100_error {
+	AV8100_OK = 0x0,
+	AV8100_INVALID_COMMAND = 0x1,
+	AV8100_INVALID_INTERFACE = 0x2,
+	AV8100_INVALID_IOCTL = 0x3,
+	AV8100_COMMAND_FAIL = 0x4,
+	AV8100_FWDOWNLOAD_FAIL = 0x5,
+	AV8100_FAIL = 0xFF,
+};
+
+enum av8100_command_type {
+	AV8100_COMMAND_VIDEO_INPUT_FORMAT  = 0x1,
+	AV8100_COMMAND_AUDIO_INPUT_FORMAT,
+	AV8100_COMMAND_VIDEO_OUTPUT_FORMAT,
+	AV8100_COMMAND_VIDEO_SCALING_FORMAT,
+	AV8100_COMMAND_COLORSPACECONVERSION,
+	AV8100_COMMAND_CEC_MESSAGE_WRITE,
+	AV8100_COMMAND_CEC_MESSAGE_READ_BACK,
+	AV8100_COMMAND_DENC,
+	AV8100_COMMAND_HDMI,
+	AV8100_COMMAND_HDCP_SENDKEY,
+	AV8100_COMMAND_HDCP_MANAGEMENT,
+	AV8100_COMMAND_INFOFRAMES,
+	AV8100_COMMAND_EDID_SECTION_READBACK,
+	AV8100_COMMAND_PATTERNGENERATOR,
+	AV8100_COMMAND_FUSE_AES_KEY,
+};
+
+enum interface_type {
+	I2C_INTERFACE = 0x0,
+	DSI_INTERFACE = 0x1,
+};
+
+enum av8100_dsi_mode {
+	AV8100_HDMI_DSI_OFF,
+	AV8100_HDMI_DSI_COMMAND_MODE,
+	AV8100_HDMI_DSI_VIDEO_MODE
+};
+
+enum av8100_pixel_format {
+	AV8100_INPUT_PIX_RGB565,
+	AV8100_INPUT_PIX_RGB666,
+	AV8100_INPUT_PIX_RGB666P,
+	AV8100_INPUT_PIX_RGB888,
+	AV8100_INPUT_PIX_YCBCR422
+};
+
+enum av8100_video_mode {
+	AV8100_VIDEO_INTERLACE,
+	AV8100_VIDEO_PROGRESSIVE
+};
+
+enum av8100_dsi_nb_data_lane {
+	AV8100_DATA_LANES_USED_0,
+	AV8100_DATA_LANES_USED_1,
+	AV8100_DATA_LANES_USED_2,
+	AV8100_DATA_LANES_USED_3,
+	AV8100_DATA_LANES_USED_4
+};
+
+enum av8100_te_config {
+	AV8100_TE_OFF,		/* NO TE*/
+	AV8100_TE_DSI_LANE,	/* TE generated on DSI lane */
+	AV8100_TE_IT_LINE,	/* TE generated on IT line (GPIO) */
+	AV8100_TE_DSI_IT,	/* TE generatedon both DSI lane & IT line*/
+	AV8100_TE_GPIO_IT	/* TE on GPIO I2S DAT3 & or IT line*/
+};
+
+enum av8100_audio_if_format {
+	AV8100_AUDIO_I2S_MODE,
+	AV8100_AUDIO_I2SDELAYED_MODE, /* I2S Mode by default*/
+	AV8100_AUDIO_TDM_MODE         /* 8 Channels by default*/
+};
+
+enum av8100_sample_freq {
+	AV8100_AUDIO_FREQ_32KHZ,
+	AV8100_AUDIO_FREQ_44_1KHZ,
+	AV8100_AUDIO_FREQ_48KHZ,
+	AV8100_AUDIO_FREQ_64KHZ,
+	AV8100_AUDIO_FREQ_88_2KHZ,
+	AV8100_AUDIO_FREQ_96KHZ,
+	AV8100_AUDIO_FREQ_128KHZ,
+	AV8100_AUDIO_FREQ_176_1KHZ,
+	AV8100_AUDIO_FREQ_192KHZ
+};
+
+enum av8100_audio_word_length {
+	AV8100_AUDIO_16BITS,
+	AV8100_AUDIO_20BITS,
+	AV8100_AUDIO_24BITS
+};
+
+enum av8100_audio_format {
+	AV8100_AUDIO_LPCM_MODE,
+	AV8100_AUDIO_COMPRESS_MODE
+};
+
+enum av8100_audio_if_mode {
+	AV8100_AUDIO_SLAVE,
+	AV8100_AUDIO_MASTER
+};
+
+enum av8100_audio_mute {
+	AV8100_AUDIO_MUTE_DISABLE,
+	AV8100_AUDIO_MUTE_ENABLE
+};
+
+enum av8100_output_CEA_VESA {
+	AV8100_CUSTOM,
+	AV8100_CEA1_640X480P_59_94HZ,
+	AV8100_CEA2_3_720X480P_59_94HZ,
+	AV8100_CEA4_1280X720P_60HZ,
+	AV8100_CEA5_1920X1080I_60HZ,
+	AV8100_CEA6_7_NTSC_60HZ,
+	AV8100_CEA14_15_480p_60HZ,
+	AV8100_CEA16_1920X1080P_60HZ,
+	AV8100_CEA17_18_720X576P_50HZ,
+	AV8100_CEA19_1280X720P_50HZ,
+	AV8100_CEA20_1920X1080I_50HZ,
+	AV8100_CEA21_22_576I_PAL_50HZ,
+	AV8100_CEA29_30_576P_50HZ,
+	AV8100_CEA31_1920x1080P_50Hz,
+	AV8100_CEA32_1920X1080P_24HZ,
+	AV8100_CEA33_1920X1080P_25HZ,
+	AV8100_CEA34_1920X1080P_30HZ,
+	AV8100_CEA60_1280X720P_24HZ,
+	AV8100_CEA61_1280X720P_25HZ,
+	AV8100_CEA62_1280X720P_30HZ,
+	AV8100_VESA9_800X600P_60_32HZ,
+	AV8100_VESA14_848X480P_60HZ,
+	AV8100_VESA16_1024X768P_60HZ,
+	AV8100_VESA22_1280X768P_59_99HZ,
+	AV8100_VESA23_1280X768P_59_87HZ,
+	AV8100_VESA27_1280X800P_59_91HZ,
+	AV8100_VESA28_1280X800P_59_81HZ,
+	AV8100_VESA39_1360X768P_60_02HZ,
+	AV8100_VESA81_1366X768P_59_79HZ,
+	AV8100_VIDEO_OUTPUT_CEA_VESA_MAX
+};
+
+enum av8100_video_sync_pol {
+	AV8100_SYNC_POSITIVE,
+	AV8100_SYNC_NEGATIVE
+};
+
+enum av8100_hdmi_mode {
+	AV8100_HDMI_OFF,
+	AV8100_HDMI_ON,
+	AV8100_HDMI_AVMUTE
+};
+
+enum av8100_hdmi_format {
+	AV8100_HDMI,
+	AV8100_DVI
+};
+
+enum av8100_DVI_format {
+	AV8100_DVI_CTRL_CTL0,
+	AV8100_DVI_CTRL_CTL1,
+	AV8100_DVI_CTRL_CTL2
+};
+
+enum av8100_pattern_type {
+	AV8100_PATTERN_OFF,
+	AV8100_PATTERN_GENERATOR,
+	AV8100_PRODUCTION_TESTING
+};
+
+enum av8100_pattern_format {
+	AV8100_NO_PATTERN,
+	AV8100_PATTERN_VGA,
+	AV8100_PATTERN_720P,
+	AV8100_PATTERN_1080P
+};
+
+enum av8100_pattern_audio {
+	AV8100_PATTERN_AUDIO_OFF,
+	AV8100_PATTERN_AUDIO_ON,
+	AV8100_PATTERN_AUDIO_I2S_MEM
+};
+
+struct av8100_video_input_format_cmd {
+	enum av8100_dsi_mode		dsi_input_mode;
+	enum av8100_pixel_format	input_pixel_format;
+	unsigned short			total_horizontal_pixel;
+	unsigned short			total_horizontal_active_pixel;
+	unsigned short			total_vertical_lines;
+	unsigned short			total_vertical_active_lines;
+	enum av8100_video_mode		video_mode;
+	enum av8100_dsi_nb_data_lane	nb_data_lane;
+	unsigned char			nb_virtual_ch_command_mode;
+	unsigned char			nb_virtual_ch_video_mode;
+	unsigned short			TE_line_nb;
+	enum av8100_te_config		TE_config;
+	unsigned long			master_clock_freq;
+	unsigned char			ui_x4;
+};
+
+struct av8100_audio_input_format_cmd {
+	enum av8100_audio_if_format	audio_input_if_format;
+	unsigned char			i2s_input_nb;
+	enum av8100_sample_freq		sample_audio_freq;
+	enum av8100_audio_word_length	audio_word_lg;
+	enum av8100_audio_format	audio_format;
+	enum av8100_audio_if_mode	audio_if_mode;
+	enum av8100_audio_mute		audio_mute;
+};
+
+struct av8100_video_output_format_cmd {
+	enum av8100_output_CEA_VESA	video_output_cea_vesa;
+	enum av8100_video_sync_pol	vsync_polarity;
+	enum av8100_video_sync_pol	hsync_polarity;
+	unsigned short		total_horizontal_pixel;
+	unsigned short		total_horizontal_active_pixel;
+	unsigned short		total_vertical_in_half_lines;
+	unsigned short		total_vertical_active_in_half_lines;
+	unsigned short		hsync_start_in_pixel;
+	unsigned short		hsync_length_in_pixel;
+	unsigned short		vsync_start_in_half_line;
+	unsigned short		vsync_length_in_half_line;
+	unsigned short		hor_video_start_pixel;
+	unsigned short		vert_video_start_pixel;
+	enum av8100_video_mode	video_type;
+	unsigned short		pixel_repeat;
+	unsigned long		pixel_clock_freq_Hz;
+};
+
+struct av8100_video_scaling_format_cmd {
+	unsigned short	h_start_in_pixel;
+	unsigned short	h_stop_in_pixel;
+	unsigned short	v_start_in_line;
+	unsigned short	v_stop_in_line;
+	unsigned short	h_start_out_pixel;
+	unsigned short	h_stop_out_pixel;
+	unsigned short	v_start_out_line;
+	unsigned short	v_stop_out_line;
+};
+
+enum av8100_color_transform {
+	AV8100_COLOR_TRANSFORM_INDENTITY,
+	AV8100_COLOR_TRANSFORM_INDENTITY_CLAMP_YUV,
+	AV8100_COLOR_TRANSFORM_YUV_TO_RGB,
+	AV8100_COLOR_TRANSFORM_YUV_TO_DENC,
+	AV8100_COLOR_TRANSFORM_RGB_TO_DENC,
+};
+
+struct av8100_cec_message_write_format_cmd {
+	unsigned char buffer_length;
+	unsigned char buffer[AV8100_CEC_MESSAGE_SIZE];
+};
+
+struct av8100_cec_message_read_back_format_cmd {
+};
+
+enum av8100_cvbs_video_format {
+	AV8100_CVBS_625,
+	AV8100_CVBS_525,
+};
+
+enum av8100_standard_selection {
+	AV8100_PAL_BDGHI,
+	AV8100_PAL_N,
+	AV8100_NTSC_M,
+	AV8100_PAL_M
+};
+
+struct av8100_denc_format_cmd {
+	enum av8100_cvbs_video_format cvbs_video_format;
+	enum av8100_standard_selection standard_selection;
+	unsigned char enable;
+	unsigned char macrovision_enable;
+	unsigned char internal_generator;
+};
+
+struct av8100_hdmi_cmd {
+	enum av8100_hdmi_mode	hdmi_mode;
+	enum av8100_hdmi_format	hdmi_format;
+	enum av8100_DVI_format	dvi_format; /* used only if HDMI_format = DVI*/
+};
+
+struct av8100_hdcp_send_key_format_cmd {
+	unsigned char key_number;
+	unsigned char data_len;
+	unsigned char data[AV8100_HDCP_SEND_KEY_SIZE];
+};
+
+enum av8100_hdcp_auth_req_type {
+	AV8100_HDCP_AUTH_REQ_OFF = 0,
+	AV8100_HDCP_AUTH_REQ_ON = 1,
+	AV8100_HDCP_REV_LIST_REQ = 2,
+	AV8100_HDCP_AUTH_CONT = 3,
+};
+
+enum av8100_hdcp_encr_req_type {
+	AV8100_HDCP_ENCR_REQ_OFF = 0,
+	AV8100_HDCP_ENCR_REQ_ON = 1,
+};
+
+enum av8100_hdcp_encr_use {
+	AV8100_HDCP_ENCR_USE_OESS = 0,
+	AV8100_HDCP_ENCR_USE_EESS = 1,
+};
+
+struct av8100_hdcp_management_format_cmd {
+	unsigned char req_type;
+	unsigned char req_encr;
+	unsigned char encr_use;
+};
+
+struct av8100_infoframes_format_cmd {
+	unsigned char type;
+	unsigned char version;
+	unsigned char length;
+	unsigned char crc;
+	unsigned char data[AV8100_INFOFRAME_SIZE];
+};
+
+struct av8100_edid_section_readback_format_cmd {
+	unsigned char address;
+	unsigned char block_number;
+};
+
+struct av8100_pattern_generator_format_cmd {
+	enum av8100_pattern_type	pattern_type;
+	enum av8100_pattern_format	pattern_video_format;
+	enum av8100_pattern_audio	pattern_audio_mode;
+};
+
+enum av8100_fuse_operation {
+	AV8100_FUSE_READ = 0,
+	AV8100_FUSE_WRITE = 1,
+};
+
+struct av8100_fuse_aes_key_format_cmd {
+	unsigned char fuse_operation;
+	unsigned char key[AV8100_FUSE_KEY_SIZE];
+};
+
+union av8100_configuration {
+	struct av8100_video_input_format_cmd	video_input_format;
+	struct av8100_audio_input_format_cmd	audio_input_format;
+	struct av8100_video_output_format_cmd	video_output_format;
+	struct av8100_video_scaling_format_cmd	video_scaling_format;
+	enum   av8100_color_transform           color_transform;
+	struct av8100_cec_message_write_format_cmd
+		cec_message_write_format;
+	struct av8100_cec_message_read_back_format_cmd
+		cec_message_read_back_format;
+	struct av8100_denc_format_cmd		denc_format;
+	struct av8100_hdmi_cmd			hdmi_format;
+	struct av8100_hdcp_send_key_format_cmd	hdcp_send_key_format;
+	struct av8100_hdcp_management_format_cmd hdcp_management_format;
+	struct av8100_infoframes_format_cmd	infoframes_format;
+	struct av8100_edid_section_readback_format_cmd
+		edid_section_readback_format;
+	struct av8100_pattern_generator_format_cmd pattern_generator_format;
+	struct av8100_fuse_aes_key_format_cmd	fuse_aes_key_format;
+};
+
+enum av8100_operating_mode {
+	AV8100_OPMODE_UNDEFINED = 0,
+	AV8100_OPMODE_SHUTDOWN,
+	AV8100_OPMODE_STANDBY,
+	AV8100_OPMODE_SCAN,
+	AV8100_OPMODE_INIT,
+	AV8100_OPMODE_IDLE,
+	AV8100_OPMODE_VIDEO,
+};
+
+enum av8100_plugin_status {
+	AV8100_PLUGIN_NONE = 0x0,
+	AV8100_HDMI_PLUGIN = 0x1,
+	AV8100_CVBS_PLUGIN = 0x2,
+};
+
+enum av8100_hdmi_event {
+	AV8100_HDMI_EVENT_NONE =		0x0,
+	AV8100_HDMI_EVENT_HDMI_PLUGIN =		0x1,
+	AV8100_HDMI_EVENT_HDMI_PLUGOUT =	0x2,
+	AV8100_HDMI_EVENT_CEC =			0x4,
+	AV8100_HDMI_EVENT_HDCP =		0x8,
+	AV8100_HDMI_EVENT_CECTXERR =		0x10,
+};
+
+struct av8100_status {
+	enum av8100_operating_mode	av8100_state;
+	enum av8100_plugin_status	av8100_plugin_status;
+	int				hdmi_on;
+};
+
+
+int av8100_init(void);
+void av8100_exit(void);
+int av8100_powerup(void);
+int av8100_powerdown(void);
+int av8100_disable_interrupt(void);
+int av8100_enable_interrupt(void);
+int av8100_download_firmware(char *fw_buff, int numOfBytes,
+	enum interface_type if_type);
+int av8100_reg_stby_w(
+		unsigned char cpd,
+		unsigned char stby,
+		unsigned char mclkrng);
+int av8100_reg_hdmi_5_volt_time_w(
+		unsigned char denc_off_time,
+		unsigned char hdmi_off_time,
+		unsigned char on_time);
+int av8100_reg_stby_int_mask_w(
+		unsigned char hpdm,
+		unsigned char cpdm,
+		unsigned char stbygpiocfg,
+		unsigned char ipol);
+int av8100_reg_stby_pend_int_w(
+		unsigned char hpdi,
+		unsigned char cpdi,
+		unsigned char oni);
+int av8100_reg_gen_int_mask_w(
+		unsigned char eocm,
+		unsigned char vsim,
+		unsigned char vsom,
+		unsigned char cecm,
+		unsigned char hdcpm,
+		unsigned char uovbm,
+		unsigned char tem);
+int av8100_reg_gen_int_w(
+		unsigned char eoci,
+		unsigned char vsii,
+		unsigned char vsoi,
+		unsigned char ceci,
+		unsigned char hdcpi,
+		unsigned char uovbi);
+int av8100_reg_gpio_conf_w(
+		unsigned char dat3dir,
+		unsigned char dat3val,
+		unsigned char dat2dir,
+		unsigned char dat2val,
+		unsigned char dat1dir,
+		unsigned char dat1val,
+		unsigned char ucdbg);
+int av8100_reg_gen_ctrl_w(
+		unsigned char fdl,
+		unsigned char hld,
+		unsigned char wa,
+		unsigned char ra);
+int av8100_reg_fw_dl_entry_w(
+	unsigned char mbyte_code_entry);
+int av8100_reg_w(
+		unsigned char offset,
+		unsigned char value);
+int av8100_reg_stby_r(
+		unsigned char *cpd,
+		unsigned char *stby,
+		unsigned char *hpds,
+		unsigned char *cpds,
+		unsigned char *mclkrng);
+int av8100_reg_hdmi_5_volt_time_r(
+		unsigned char *denc_off_time,
+		unsigned char *hdmi_off_time,
+		unsigned char *on_time);
+int av8100_reg_stby_int_mask_r(
+		unsigned char *hpdm,
+		unsigned char *cpdm,
+		unsigned char *stbygpiocfg,
+		unsigned char *ipol);
+int av8100_reg_stby_pend_int_r(
+		unsigned char *hpdi,
+		unsigned char *cpdi,
+		unsigned char *oni,
+		unsigned char *sid);
+int av8100_reg_gen_int_mask_r(
+		unsigned char *eocm,
+		unsigned char *vsim,
+		unsigned char *vsom,
+		unsigned char *cecm,
+		unsigned char *hdcpm,
+		unsigned char *uovbm,
+		unsigned char *tem);
+int av8100_reg_gen_int_r(
+		unsigned char *eoci,
+		unsigned char *vsii,
+		unsigned char *vsoi,
+		unsigned char *ceci,
+		unsigned char *hdcpi,
+		unsigned char *uovbi,
+		unsigned char *tei);
+int av8100_reg_gen_status_r(
+		unsigned char *cectxerr,
+		unsigned char *cecrec,
+		unsigned char *cectrx,
+		unsigned char *uc,
+		unsigned char *onuvb,
+		unsigned char *hdcps);
+int av8100_reg_gpio_conf_r(
+		unsigned char *dat3dir,
+		unsigned char *dat3val,
+		unsigned char *dat2dir,
+		unsigned char *dat2val,
+		unsigned char *dat1dir,
+		unsigned char *dat1val,
+		unsigned char *ucdbg);
+int av8100_reg_gen_ctrl_r(
+		unsigned char *fdl,
+		unsigned char *hld,
+		unsigned char *wa,
+		unsigned char *ra);
+int av8100_reg_fw_dl_entry_r(
+	unsigned char *mbyte_code_entry);
+int av8100_reg_r(
+		unsigned char offset,
+		unsigned char *value);
+int av8100_conf_get(enum av8100_command_type command_type,
+	union av8100_configuration *config);
+int av8100_conf_prep(enum av8100_command_type command_type,
+	union av8100_configuration *config);
+int av8100_conf_w(enum av8100_command_type command_type,
+		unsigned char *return_buffer_length,
+		unsigned char *return_buffer, enum interface_type if_type);
+int av8100_conf_w_raw(enum av8100_command_type command_type,
+	unsigned char buffer_length,
+	unsigned char *buffer,
+	unsigned char *return_buffer_length,
+	unsigned char *return_buffer);
+struct av8100_status av8100_status_get(void);
+enum av8100_output_CEA_VESA av8100_video_output_format_get(int xres,
+	int yres,
+	int htot,
+	int vtot,
+	int pixelclk,
+	bool interlaced);
+void av8100_hdmi_event_cb_set(void (*event_callback)(enum av8100_hdmi_event));
+u8 av8100_ver_get(void);
+
+#endif /* __AV8100__H__ */
diff --git a/include/video/hdmi.h b/include/video/hdmi.h
new file mode 100644
index 00000000000..18a8e34bd67
--- /dev/null
+++ b/include/video/hdmi.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) ST-Ericsson AB 2010
+ *
+ * HDMI driver
+ *
+ * Author: Per Persson <per.xb.persson@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __HDMI__H__
+#define __HDMI__H__
+
+#define HDMI_RESULT_OK			0
+#define HDMI_RESULT_NOT_OK		1
+#define HDMI_AES_NOT_FUSED		2
+#define HDMI_RESULT_CRC_MISMATCH	3
+
+#define HDMI_CEC_READ_MAXSIZE		16
+#define HDMI_CEC_WRITE_MAXSIZE		15
+#define HDMI_INFOFRAME_MAX_SIZE		27
+#define HDMI_HDCP_FUSEAES_KEYSIZE	16
+#define HDMI_HDCP_AES_BLOCK_START	128
+#define HDMI_HDCP_KSV_BLOCK		40
+#define HDMI_HDCP_AES_NR_OF_BLOCKS	18
+#define HDMI_HDCP_AES_KEYSIZE		16
+#define HDMI_HDCP_AES_KSVSIZE		5
+#define HDMI_HDCP_AES_KSVZEROESSIZE	3
+#define HDMI_EDID_DATA_SIZE		128
+#define HDMI_CEC_SIZE			15
+#define HDMI_INFOFR_SIZE		27
+#define HDMI_FUSE_KEYSIZE		16
+#define HDMI_AES_KSVSIZE		5
+#define HDMI_AES_KEYSIZE		288
+#define HDMI_CRC32_SIZE			4
+#define HDMI_REVOC_LIST_SIZE		30
+
+#define HDMI_STOREASTEXT_TEXT_SIZE	2
+#define HDMI_STOREASTEXT_BIN_SIZE	1
+#define HDMI_PLUGDETEN_TEXT_SIZE	6
+#define HDMI_PLUGDETEN_BIN_SIZE		3
+#define HDMI_EDIDREAD_TEXT_SIZE		4
+#define HDMI_EDIDREAD_BIN_SIZE		2
+#define HDMI_CECEVEN_TEXT_SIZE		2
+#define HDMI_CECEVEN_BIN_SIZE		1
+#define HDMI_CECSEND_TEXT_SIZE_MAX	37
+#define HDMI_CECSEND_TEXT_SIZE_MIN	6
+#define HDMI_CECSEND_BIN_SIZE_MAX	18
+#define HDMI_CECSEND_BIN_SIZE_MIN	3
+#define HDMI_INFOFRSEND_TEXT_SIZE_MIN	8
+#define HDMI_INFOFRSEND_TEXT_SIZE_MAX	63
+#define HDMI_INFOFRSEND_BIN_SIZE_MIN	4
+#define HDMI_INFOFRSEND_BIN_SIZE_MAX	31
+#define HDMI_HDCPEVEN_TEXT_SIZE		2
+#define HDMI_HDCPEVEN_BIN_SIZE		1
+#define HDMI_HDCP_FUSEAES_TEXT_SIZE	34
+#define HDMI_HDCP_FUSEAES_BIN_SIZE	17
+#define HDMI_HDCP_LOADAES_TEXT_SIZE	594
+#define HDMI_HDCP_LOADAES_BIN_SIZE	297
+#define HDMI_HDCPAUTHENCR_TEXT_SIZE	4
+#define HDMI_HDCPAUTHENCR_BIN_SIZE	2
+#define HDMI_EVCLR_TEXT_SIZE		2
+#define HDMI_EVCLR_BIN_SIZE		1
+#define HDMI_AUDIOCFG_TEXT_SIZE		14
+#define HDMI_AUDIOCFG_BIN_SIZE		7
+#define HDMI_POWERONOFF_TEXT_SIZE	2
+#define HDMI_POWERONOFF_BIN_SIZE	1
+
+#define HDMI_IOC_MAGIC 0xcc
+
+/** IOCTL Operations */
+#define IOC_PLUG_DETECT_ENABLE		_IOWR(HDMI_IOC_MAGIC, 1, int)
+#define IOC_EDID_READ			_IOWR(HDMI_IOC_MAGIC, 2, int)
+#define IOC_CEC_EVENT_ENABLE		_IOWR(HDMI_IOC_MAGIC, 3, int)
+#define IOC_CEC_READ			_IOWR(HDMI_IOC_MAGIC, 4, int)
+#define IOC_CEC_SEND			_IOWR(HDMI_IOC_MAGIC, 5, int)
+#define IOC_INFOFRAME_SEND		_IOWR(HDMI_IOC_MAGIC, 6, int)
+#define IOC_HDCP_EVENT_ENABLE		_IOWR(HDMI_IOC_MAGIC, 7, int)
+#define IOC_HDCP_CHKAESOTP		_IOWR(HDMI_IOC_MAGIC, 8, int)
+#define IOC_HDCP_FUSEAES		_IOWR(HDMI_IOC_MAGIC, 9, int)
+#define IOC_HDCP_LOADAES		_IOWR(HDMI_IOC_MAGIC, 10, int)
+#define IOC_HDCP_AUTHENCR_REQ		_IOWR(HDMI_IOC_MAGIC, 11, int)
+#define IOC_HDCP_STATE_GET		_IOWR(HDMI_IOC_MAGIC, 12, int)
+#define IOC_EVENTS_READ			_IOWR(HDMI_IOC_MAGIC, 13, int)
+#define IOC_EVENTS_CLEAR		_IOWR(HDMI_IOC_MAGIC, 14, int)
+#define IOC_AUDIO_CFG			_IOWR(HDMI_IOC_MAGIC, 15, int)
+#define IOC_PLUG_STATUS			_IOWR(HDMI_IOC_MAGIC, 16, int)
+#define IOC_POWERONOFF			_IOWR(HDMI_IOC_MAGIC, 17, int)
+
+
+/* HDMI driver */
+void hdmi_event(enum av8100_hdmi_event);
+int hdmi_init(void);
+void hdmi_exit(void);
+
+enum hdmi_event {
+	HDMI_EVENT_NONE =		0x0,
+	HDMI_EVENT_HDMI_PLUGIN =	0x1,
+	HDMI_EVENT_HDMI_PLUGOUT =	0x2,
+	HDMI_EVENT_CEC =		0x4,
+	HDMI_EVENT_HDCP =		0x8,
+	HDMI_EVENT_CECTXERR =		0x10,
+};
+
+enum hdmi_hdcp_auth_type {
+	HDMI_HDCP_AUTH_OFF = 0,
+	HDMI_HDCP_AUTH_START = 1,
+	HDMI_HDCP_AUTH_REV_LIST_REQ = 2,
+	HDMI_HDCP_AUTH_CONT = 3,
+};
+
+enum hdmi_hdcp_encr_type {
+	HDMI_HDCP_ENCR_OFF = 0,
+	HDMI_HDCP_ENCR_OESS = 1,
+	HDMI_HDCP_ENCR_EESS = 2,
+};
+
+struct plug_detect {
+	u8 hdmi_detect_enable;
+	u8 on_time;
+	u8 hdmi_off_time;
+};
+
+struct edid_read {
+	u8 address;
+	u8 block_nr;
+	u8 data_length;
+	u8 data[HDMI_EDID_DATA_SIZE];
+};
+
+struct cec_rw  {
+	u8 src;
+	u8 dest;
+	u8 length;
+	u8 data[HDMI_CEC_SIZE];
+};
+
+struct info_fr {
+	u8 type;
+	u8 ver;
+	u8 crc;
+	u8 length;
+	u8 data[HDMI_INFOFR_SIZE];
+};
+
+struct hdcp_fuseaes {
+	u8 key[HDMI_FUSE_KEYSIZE];
+	u8 crc;
+	u8 result;
+};
+
+struct hdcp_loadaesall {
+	u8 key[HDMI_AES_KEYSIZE];
+	u8 ksv[HDMI_AES_KSVSIZE];
+	u8 crc32[HDMI_CRC32_SIZE];
+	u8 result;
+};
+
+struct hdcp_authencr {
+	u8 auth_type;
+	u8 encr_type;
+	u8 result;
+	u8 revoc_list[HDMI_REVOC_LIST_SIZE];
+};
+
+struct audio_cfg {
+	u8 if_format;
+	u8 i2s_entries;
+	u8 freq;
+	u8 word_length;
+	u8 format;
+	u8 if_mode;
+	u8 mute;
+};
+
+#endif /* __HDMI__H__ */
diff --git a/include/video/mcde.h b/include/video/mcde.h
new file mode 100644
index 00000000000..1777e272329
--- /dev/null
+++ b/include/video/mcde.h
@@ -0,0 +1,434 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * ST-Ericsson MCDE base driver
+ *
+ * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __MCDE__H__
+#define __MCDE__H__
+
+/* Physical interface types */
+enum mcde_port_type {
+	MCDE_PORTTYPE_DSI = 0,
+	MCDE_PORTTYPE_DPI = 1,
+};
+
+/* Interface mode */
+enum mcde_port_mode {
+	MCDE_PORTMODE_CMD = 0,
+	MCDE_PORTMODE_VID = 1,
+};
+
+/* MCDE fifos */
+enum mcde_fifo {
+	MCDE_FIFO_A  = 0,
+	MCDE_FIFO_B  = 1,
+	MCDE_FIFO_C0 = 2,
+	MCDE_FIFO_C1 = 3,
+};
+
+/* MCDE channels (pixel pipelines) */
+enum mcde_chnl {
+	MCDE_CHNL_A  = 0,
+	MCDE_CHNL_B  = 1,
+	MCDE_CHNL_C0 = 2,
+	MCDE_CHNL_C1 = 3,
+};
+
+/* Channel path */
+#define MCDE_CHNLPATH(__chnl, __fifo, __type, __ifc, __link) \
+	(((__chnl) << 16) | ((__fifo) << 12) | \
+	 ((__type) << 8) | ((__ifc) << 4) | ((__link) << 0))
+enum mcde_chnl_path {
+	/* Channel A */
+	MCDE_CHNLPATH_CHNLA_FIFOA_DPI_0 = MCDE_CHNLPATH(MCDE_CHNL_A,
+		MCDE_FIFO_A, MCDE_PORTTYPE_DPI, 0, 0),
+	MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_A,
+		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 0),
+	MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_A,
+		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 1),
+	MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_A,
+		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 0, 2),
+	MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_A,
+		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 0),
+	MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_A,
+		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 1),
+	MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_A,
+		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 1, 2),
+	/* Channel B */
+	MCDE_CHNLPATH_CHNLB_FIFOB_DPI_1 = MCDE_CHNLPATH(MCDE_CHNL_B,
+		MCDE_FIFO_B, MCDE_PORTTYPE_DPI, 0, 1),
+	MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_B,
+		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 0),
+	MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_B,
+		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 1),
+	MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_B,
+		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 0, 2),
+	MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_B,
+		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 0),
+	MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_B,
+		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 1),
+	MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_B,
+		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 1, 2),
+	/* Channel C0 */
+	MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_C0,
+		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 0),
+	MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_C0,
+		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 1),
+	MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_C0,
+		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 0, 2),
+	MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_C0,
+		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 0),
+	MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_C0,
+		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 1),
+	MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_C0,
+		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 1, 2),
+	/* Channel C1 */
+	MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_C1,
+		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 0),
+	MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_C1,
+		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 1),
+	MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_C1,
+		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 0, 2),
+	MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_C1,
+		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 0),
+	MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_C1,
+		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 1),
+	MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_C1,
+		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 1, 2),
+};
+
+/* Update sync mode */
+enum mcde_sync_src {
+	MCDE_SYNCSRC_OFF = 0, /* No sync */
+	MCDE_SYNCSRC_TE0 = 1, /* MCDE ext TE0 */
+	MCDE_SYNCSRC_TE1 = 2, /* MCDE ext TE1 */
+	MCDE_SYNCSRC_BTA = 3, /* DSI BTA */
+	MCDE_SYNCSRC_TE_POLLING = 4, /* DSI TE_POLLING */
+};
+
+/* Interface pixel formats (output) */
+/*
+* REVIEW: Define formats
+* Add explanatory comments how the formats are ordered in memory
+*/
+enum mcde_port_pix_fmt {
+	/* MIPI standard formats */
+
+	MCDE_PORTPIXFMT_DPI_16BPP_C1 =     0x21,
+	MCDE_PORTPIXFMT_DPI_16BPP_C2 =     0x22,
+	MCDE_PORTPIXFMT_DPI_16BPP_C3 =     0x23,
+	MCDE_PORTPIXFMT_DPI_18BPP_C1 =     0x24,
+	MCDE_PORTPIXFMT_DPI_18BPP_C2 =     0x25,
+	MCDE_PORTPIXFMT_DPI_24BPP =        0x26,
+
+	MCDE_PORTPIXFMT_DSI_16BPP =        0x31,
+	MCDE_PORTPIXFMT_DSI_18BPP =        0x32,
+	MCDE_PORTPIXFMT_DSI_18BPP_PACKED = 0x33,
+	MCDE_PORTPIXFMT_DSI_24BPP =        0x34,
+
+	/* Custom formats */
+	MCDE_PORTPIXFMT_DSI_YCBCR422 =     0x40,
+};
+
+enum mcde_hdmi_sdtv_switch {
+	HDMI_SWITCH,
+	SDTV_SWITCH
+};
+
+struct mcde_col_convert {
+	u16 matrix[3][3];
+	u16 offset[3];
+};
+
+#define MCDE_PORT_DPI_NO_CLOCK_DIV	0
+
+#define DPI_ACT_HIGH_ALL	0 /* all signals are active high	  */
+#define DPI_ACT_LOW_HSYNC	1 /* horizontal sync signal is active low */
+#define DPI_ACT_LOW_VSYNC	2 /* vertical sync signal is active low	  */
+#define DPI_ACT_LOW_DATA_ENABLE	4 /* data enable signal is active low	  */
+#define DPI_ACT_ON_FALLING_EDGE	8 /* drive data on the falling edge of the
+				   * pixel clock
+				   */
+
+struct mcde_port {
+	enum mcde_port_type type;
+	enum mcde_port_mode mode;
+	enum mcde_port_pix_fmt pixel_format;
+	u8 ifc;
+	u8 link;
+	enum mcde_sync_src sync_src;
+	bool update_auto_trig;
+	enum mcde_hdmi_sdtv_switch hdmi_sdtv_switch;
+	union {
+		struct {
+			u8 virt_id;
+			u8 num_data_lanes;
+			u8 ui;
+			bool clk_cont;
+
+			/* DSI data lanes are swapped if true */
+			bool data_lanes_swap;
+		} dsi;
+		struct {
+			u8 bus_width;
+			bool tv_mode;
+			u16 clock_div; /* use 0 or 1 for no clock divider */
+			u32 polarity;    /* see DPI_ACT_LOW_* definitions */
+		} dpi;
+	} phy;
+};
+
+/* Overlay pixel formats (input) *//* REVIEW: Define byte order */
+enum mcde_ovly_pix_fmt {
+	MCDE_OVLYPIXFMT_RGB565   = 1,
+	MCDE_OVLYPIXFMT_RGBA5551 = 2,
+	MCDE_OVLYPIXFMT_RGBA4444 = 3,
+	MCDE_OVLYPIXFMT_RGB888   = 4,
+	MCDE_OVLYPIXFMT_RGBX8888 = 5,
+	MCDE_OVLYPIXFMT_RGBA8888 = 6,
+	MCDE_OVLYPIXFMT_YCbCr422 = 7,/* REVIEW: Capitalize */
+};
+
+/* Display power modes */
+enum mcde_display_power_mode {
+	MCDE_DISPLAY_PM_OFF     = 0, /* Power off */
+	MCDE_DISPLAY_PM_STANDBY = 1, /* DCS sleep mode */
+	MCDE_DISPLAY_PM_ON      = 2, /* DCS normal mode, display on */
+};
+
+/* Display rotation */
+enum mcde_display_rotation {
+	MCDE_DISPLAY_ROT_0       = 0,
+	MCDE_DISPLAY_ROT_90_CCW  = 90,
+	MCDE_DISPLAY_ROT_180_CCW = 180,
+	MCDE_DISPLAY_ROT_270_CCW = 270,
+	MCDE_DISPLAY_ROT_90_CW   = MCDE_DISPLAY_ROT_270_CCW,
+	MCDE_DISPLAY_ROT_180_CW  = MCDE_DISPLAY_ROT_180_CCW,
+	MCDE_DISPLAY_ROT_270_CW  = MCDE_DISPLAY_ROT_90_CCW,
+};
+
+/* REVIEW: Verify */
+#define MCDE_MIN_WIDTH  16
+#define MCDE_MIN_HEIGHT 16
+#define MCDE_MAX_WIDTH  2048
+#define MCDE_MAX_HEIGHT 2048
+#define MCDE_BUF_START_ALIGMENT 8
+#define MCDE_BUF_LINE_ALIGMENT 8
+
+#define MCDE_FIFO_AB_SIZE 640
+#define MCDE_FIFO_C0C1_SIZE 160
+
+#define MCDE_PIXFETCH_LARGE_WTRMRKLVL 128
+#define MCDE_PIXFETCH_MEDIUM_WTRMRKLVL 64
+#define MCDE_PIXFETCH_SMALL_WTRMRKLVL 16
+
+/* Tv-out defines */
+#define MCDE_CONFIG_TVOUT_HBORDER 2
+#define MCDE_CONFIG_TVOUT_VBORDER 2
+#define MCDE_CONFIG_TVOUT_BACKGROUND_LUMINANCE		0x83
+#define MCDE_CONFIG_TVOUT_BACKGROUND_CHROMINANCE_CB	0x9C
+#define MCDE_CONFIG_TVOUT_BACKGROUND_CHROMINANCE_CR	0x2C
+
+/* In seconds */
+#define MCDE_AUTO_SYNC_WATCHDOG 5
+
+/* Hardware versions */
+#define MCDE_CHIP_VERSION_1_0_4 3	/* U5500 V1 */
+#define MCDE_CHIP_VERSION_3_0_8 2	/* U8500 V2 */
+#define MCDE_CHIP_VERSION_3_0_5 1	/* U8500 V1 */
+#define MCDE_CHIP_VERSION_3	0
+
+/* DSI modes */
+#define DSI_VIDEO_MODE	0
+#define DSI_CMD_MODE	1
+
+/* Video mode descriptor */
+struct mcde_video_mode {/* REVIEW: Join 1 & 2 */
+	u32 xres;
+	u32 yres;
+	u32 pixclock;	/* pixel clock in ps (pico seconds) */
+	u32 hbp;	/* hor back porch = left_margin */
+	u32 hfp;	/* hor front porch equals to right_margin */
+	u32 hsw;	/* horizontal sync width */
+	u32 vbp1;	/* field 1: vert back porch equals to upper_margin */
+	u32 vfp1;	/* field 1: vert front porch equals to lower_margin */
+	u32 vbp2;	/* field 2: vert back porch equals to upper_margin */
+	u32 vfp2;	/* field 2: vert front porch equals to lower_margin */
+	u32 vsw;	/* vertical sync width*/
+	bool interlaced;
+	bool force_update; /* when switching between hdmi and sdtv */
+};
+
+struct mcde_rectangle {
+	u16 x;
+	u16 y;
+	u16 w;
+	u16 h;
+};
+
+struct mcde_overlay_info {
+	u32 paddr;
+	u16 stride; /* buffer line len in bytes */
+	enum mcde_ovly_pix_fmt fmt;
+
+	u16 src_x;
+	u16 src_y;
+	u16 dst_x;
+	u16 dst_y;
+	u16 dst_z;
+	u16 w;
+	u16 h;
+	struct mcde_rectangle dirty;
+};
+
+struct mcde_overlay {
+	struct kobject kobj;
+	struct list_head list; /* mcde_display_device.ovlys */
+
+	struct mcde_display_device *ddev;
+	struct mcde_overlay_info info;
+	struct mcde_ovly_state *state;
+};
+
+/*
+ * Three functions for mapping 8 bits colour channels on 12 bits colour
+ * channels. The colour channels (ch0, ch1, ch2) can represent (r, g, b) or
+ * (Y, Cb, Cr) respectively.
+ */
+struct mcde_palette_table {
+	u16 (*map_col_ch0)(u8);
+	u16 (*map_col_ch1)(u8);
+	u16 (*map_col_ch2)(u8);
+};
+
+struct mcde_chnl_state;
+
+struct mcde_chnl_state *mcde_chnl_get(enum mcde_chnl chnl_id,
+			enum mcde_fifo fifo, const struct mcde_port *port);
+int mcde_chnl_set_pixel_format(struct mcde_chnl_state *chnl,
+					enum mcde_port_pix_fmt pix_fmt);
+int mcde_chnl_set_palette(struct mcde_chnl_state *chnl,
+					struct mcde_palette_table *palette);
+void mcde_chnl_set_col_convert(struct mcde_chnl_state *chnl,
+					struct mcde_col_convert *col_convert);
+int mcde_chnl_set_video_mode(struct mcde_chnl_state *chnl,
+					struct mcde_video_mode *vmode);
+/* TODO: Remove rotbuf* parameters when ESRAM allocator is implemented*/
+int mcde_chnl_set_rotation(struct mcde_chnl_state *chnl,
+		enum mcde_display_rotation rotation, u32 rotbuf1, u32 rotbuf2);
+int mcde_chnl_enable_synchronized_update(struct mcde_chnl_state *chnl,
+								bool enable);
+int mcde_chnl_set_power_mode(struct mcde_chnl_state *chnl,
+				enum mcde_display_power_mode power_mode);
+
+int mcde_chnl_apply(struct mcde_chnl_state *chnl);
+int mcde_chnl_update(struct mcde_chnl_state *chnl,
+					struct mcde_rectangle *update_area);
+void mcde_chnl_put(struct mcde_chnl_state *chnl);
+
+void mcde_chnl_stop_flow(struct mcde_chnl_state *chnl);
+
+void mcde_chnl_enable(struct mcde_chnl_state *chnl);
+void mcde_chnl_disable(struct mcde_chnl_state *chnl);
+
+/* MCDE overlay */
+struct mcde_ovly_state;
+
+struct mcde_ovly_state *mcde_ovly_get(struct mcde_chnl_state *chnl);
+void mcde_ovly_set_source_buf(struct mcde_ovly_state *ovly,
+	u32 paddr);
+void mcde_ovly_set_source_info(struct mcde_ovly_state *ovly,
+	u32 stride, enum mcde_ovly_pix_fmt pix_fmt);
+void mcde_ovly_set_source_area(struct mcde_ovly_state *ovly,
+	u16 x, u16 y, u16 w, u16 h);
+void mcde_ovly_set_dest_pos(struct mcde_ovly_state *ovly,
+	u16 x, u16 y, u8 z);
+void mcde_ovly_apply(struct mcde_ovly_state *ovly);
+void mcde_ovly_put(struct mcde_ovly_state *ovly);
+
+/* MCDE dsi */
+
+#define DCS_CMD_ENTER_IDLE_MODE       0x39
+#define DCS_CMD_ENTER_INVERT_MODE     0x21
+#define DCS_CMD_ENTER_NORMAL_MODE     0x13
+#define DCS_CMD_ENTER_PARTIAL_MODE    0x12
+#define DCS_CMD_ENTER_SLEEP_MODE      0x10
+#define DCS_CMD_EXIT_IDLE_MODE        0x38
+#define DCS_CMD_EXIT_INVERT_MODE      0x20
+#define DCS_CMD_EXIT_SLEEP_MODE       0x11
+#define DCS_CMD_GET_ADDRESS_MODE      0x0B
+#define DCS_CMD_GET_BLUE_CHANNEL      0x08
+#define DCS_CMD_GET_DIAGNOSTIC_RESULT 0x0F
+#define DCS_CMD_GET_DISPLAY_MODE      0x0D
+#define DCS_CMD_GET_GREEN_CHANNEL     0x07
+#define DCS_CMD_GET_PIXEL_FORMAT      0x0C
+#define DCS_CMD_GET_POWER_MODE        0x0A
+#define DCS_CMD_GET_RED_CHANNEL       0x06
+#define DCS_CMD_GET_SCANLINE          0x45
+#define DCS_CMD_GET_SIGNAL_MODE       0x0E
+#define DCS_CMD_NOP                   0x00
+#define DCS_CMD_READ_DDB_CONTINUE     0xA8
+#define DCS_CMD_READ_DDB_START        0xA1
+#define DCS_CMD_READ_MEMORY_CONTINE   0x3E
+#define DCS_CMD_READ_MEMORY_START     0x2E
+#define DCS_CMD_SET_ADDRESS_MODE      0x36
+#define DCS_CMD_SET_COLUMN_ADDRESS    0x2A
+#define DCS_CMD_SET_DISPLAY_OFF       0x28
+#define DCS_CMD_SET_DISPLAY_ON        0x29
+#define DCS_CMD_SET_GAMMA_CURVE       0x26
+#define DCS_CMD_SET_PAGE_ADDRESS      0x2B
+#define DCS_CMD_SET_PARTIAL_AREA      0x30
+#define DCS_CMD_SET_PIXEL_FORMAT      0x3A
+#define DCS_CMD_SET_SCROLL_AREA       0x33
+#define DCS_CMD_SET_SCROLL_START      0x37
+#define DCS_CMD_SET_TEAR_OFF          0x34
+#define DCS_CMD_SET_TEAR_ON           0x35
+#define DCS_CMD_SET_TEAR_SCANLINE     0x44
+#define DCS_CMD_SOFT_RESET            0x01
+#define DCS_CMD_WRITE_LUT             0x2D
+#define DCS_CMD_WRITE_CONTINUE        0x3C
+#define DCS_CMD_WRITE_START           0x2C
+
+#define MCDE_MAX_DCS_READ   4
+#define MCDE_MAX_DCS_WRITE 15
+
+int mcde_dsi_dcs_write(struct mcde_chnl_state *chnl, u8 cmd, u8* data, int len);
+int mcde_dsi_dcs_read(struct mcde_chnl_state *chnl, u8 cmd, u8* data, int *len);
+
+/* MCDE */
+
+/* Driver data */
+#define MCDE_IRQ     "MCDE IRQ"
+#define MCDE_IO_AREA "MCDE I/O Area"
+
+struct mcde_platform_data {
+	/* DSI */
+	int num_dsilinks;
+
+	/* DPI */
+	u8 outmux[5]; /* MCDE_CONF0.OUTMUXx */
+	u8 syncmux;   /* MCDE_CONF0.SYNCMUXx */
+
+	const char *regulator_vana_id;
+	const char *regulator_mcde_epod_id;
+	const char *regulator_esram_epod_id;
+	int num_channels;
+	int num_overlays;
+	const char *clock_dsi_id;
+	const char *clock_dsi_lp_id;
+	const char *clock_dpi_id;
+	const char *clock_mcde_id;
+
+	int (*platform_enable)(void);
+	int (*platform_disable)(void);
+};
+
+int mcde_init(void);
+void mcde_exit(void);
+
+#endif /* __MCDE__H__ */
diff --git a/include/video/mcde_display-ab8500.h b/include/video/mcde_display-ab8500.h
new file mode 100644
index 00000000000..ce0633313f1
--- /dev/null
+++ b/include/video/mcde_display-ab8500.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * AB8500 tvout driver interface
+ *
+ * Author: Marcel Tunnissen <marcel.tuennissen@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __DISPLAY_AB8500__H__
+#define __DISPLAY_AB8500__H__
+
+#include <video/mcde.h>
+
+struct ab8500_display_platform_data {
+	/* Platform info */
+	const char *denc_regulator_id;
+	struct mcde_col_convert rgb_2_yCbCr_transform;
+};
+
+#endif /* __DISPLAY_AB8500__H__*/
+
diff --git a/include/video/mcde_display-av8100.h b/include/video/mcde_display-av8100.h
new file mode 100644
index 00000000000..79e806a8391
--- /dev/null
+++ b/include/video/mcde_display-av8100.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * ST-Ericsson MCDE HDMI display driver
+ *
+ * Author: Per Persson <per-xb-persson@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __DISPLAY_AV8100__H__
+#define __DISPLAY_AV8100__H__
+
+#include <linux/regulator/consumer.h>
+
+#include "mcde_display.h"
+
+#define GPIO_AV8100_RSTN	196
+#define NATIVE_XRES_HDMI	1280
+#define NATIVE_YRES_HDMI	720
+#define NATIVE_XRES_SDTV	720
+#define NATIVE_YRES_SDTV	576
+
+struct mcde_display_hdmi_platform_data {
+	/* Platform info */
+	int reset_gpio;
+	bool reset_high;
+	const char *regulator_id;
+	int reset_delay; /* ms */
+	u32 ddb_id;
+	struct mcde_col_convert rgb_2_yCbCr_transform;
+
+	/* Driver data */ /* TODO: move to driver data instead */
+	bool hdmi_platform_enable;
+	struct regulator *regulator;
+};
+
+#endif /* __DISPLAY_AV8100__H__ */
diff --git a/include/video/mcde_display-generic_dsi.h b/include/video/mcde_display-generic_dsi.h
new file mode 100644
index 00000000000..87ef6baf67a
--- /dev/null
+++ b/include/video/mcde_display-generic_dsi.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * ST-Ericsson MCDE generic DCS display driver
+ *
+ * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __MCDE_DISPLAY_GENERIC__H__
+#define __MCDE_DISPLAY_GENERIC__H__
+
+#include <linux/regulator/consumer.h>
+
+#include "mcde_display.h"
+
+struct mcde_display_generic_platform_data {
+	/* Platform info */
+	int reset_gpio;
+	bool reset_high;
+	const char *regulator_id;
+	int reset_delay; /* ms */
+	int sleep_out_delay; /* ms */
+	u32 ddb_id;
+
+	/* Driver data */
+	bool generic_platform_enable;
+	struct regulator *regulator;
+	int max_supply_voltage;
+	int min_supply_voltage;
+};
+
+#endif /* __MCDE_DISPLAY_GENERIC__H__ */
+
diff --git a/include/video/mcde_display-sony_sy35560_dsi.h b/include/video/mcde_display-sony_sy35560_dsi.h
new file mode 100644
index 00000000000..997a7ed1f85
--- /dev/null
+++ b/include/video/mcde_display-sony_sy35560_dsi.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * ST-Ericsson MCDE Sony sy35560 DCS display driver
+ *
+ * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __MCDE_DISPLAY_SONY_SY35560__H__
+#define __MCDE_DISPLAY_SONY_SY35560__H__
+
+#include <linux/regulator/consumer.h>
+
+#include "mcde_display.h"
+#include <linux/workqueue.h>
+
+/* period between ESD status checks */
+#define SONY_SY35560_ESD_CHECK_PERIOD	msecs_to_jiffies(10000)
+
+struct sony_sy35560_platform_data {
+	/* Platform info */
+	int reset_gpio;
+	bool reset_high;
+	const char *regulator_id;
+	bool skip_init;
+
+	/* Driver data */
+	int max_supply_voltage;
+	int min_supply_voltage;
+};
+
+struct sony_sy35560_device {
+	struct mcde_display_device base;
+
+	struct regulator *regulator;
+
+	/* ESD workqueue */
+	struct workqueue_struct *esd_wq;
+	struct delayed_work esd_work;
+};
+
+#endif /* __MCDE_DISPLAY_SONY_SY35560__H__ */
+
diff --git a/include/video/mcde_display-vuib500-dpi.h b/include/video/mcde_display-vuib500-dpi.h
new file mode 100644
index 00000000000..94bad83bf97
--- /dev/null
+++ b/include/video/mcde_display-vuib500-dpi.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * ST-Ericsson MCDE DPI display driver
+ *
+ * Author: Torbjorn Svensson <torbjorn.x.svensson@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __MCDE_DISPLAY_DPI__H__
+#define __MCDE_DISPLAY_DPI__H__
+
+#include <linux/regulator/consumer.h>
+
+#include "mcde_display.h"
+
+struct mcde_display_dpi_platform_data {
+	/* Platform info */
+	int reset_gpio;
+	bool reset_high;
+	const char *regulator_id;
+	int reset_delay;
+
+	/* Driver data */
+	struct regulator *regulator;
+	int max_supply_voltage;
+	int min_supply_voltage;
+};
+#endif /* __MCDE_DISPLAY_DPI__H__ */
diff --git a/include/video/mcde_display.h b/include/video/mcde_display.h
new file mode 100644
index 00000000000..aa184cb6162
--- /dev/null
+++ b/include/video/mcde_display.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * ST-Ericsson MCDE display driver
+ *
+ * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __MCDE_DISPLAY__H__
+#define __MCDE_DISPLAY__H__
+
+#include <linux/device.h>
+#include <linux/pm.h>
+
+#include <video/mcde.h>
+
+#define UPDATE_FLAG_PIXEL_FORMAT	0x1
+#define UPDATE_FLAG_VIDEO_MODE		0x2
+#define UPDATE_FLAG_ROTATION		0x4
+
+#define to_mcde_display_device(__dev) \
+	container_of((__dev), struct mcde_display_device, dev)
+
+struct mcde_display_device {
+	/* MCDE driver static */
+	struct device     dev;
+	const char       *name;
+	int               id;
+	struct mcde_port *port;
+
+	/* MCDE dss driver internal */
+	bool initialized;
+	enum mcde_chnl chnl_id;
+	enum mcde_fifo fifo;
+	bool first_update;
+
+	bool enabled;
+	struct mcde_chnl_state *chnl_state;
+	struct list_head ovlys;
+	struct mcde_rectangle update_area;
+	/* TODO: Remove once ESRAM allocator is done */
+	u32 rotbuf1;
+	u32 rotbuf2;
+
+	/* Display driver internal */
+	u16 native_x_res;
+	u16 native_y_res;
+	u16 physical_width;
+	u16 physical_height;
+	enum mcde_display_power_mode power_mode;
+	enum mcde_ovly_pix_fmt default_pixel_format;
+	enum mcde_ovly_pix_fmt pixel_format;
+	enum mcde_display_rotation rotation;
+	bool synchronized_update;
+	struct mcde_video_mode video_mode;
+	int update_flags;
+
+	/* Driver API */
+	void (*get_native_resolution)(struct mcde_display_device *dev,
+		u16 *x_res, u16 *y_res);
+	enum mcde_ovly_pix_fmt (*get_default_pixel_format)(
+		struct mcde_display_device *dev);
+	void (*get_physical_size)(struct mcde_display_device *dev,
+		u16 *x_size, u16 *y_size);
+
+	int (*set_power_mode)(struct mcde_display_device *dev,
+		enum mcde_display_power_mode power_mode);
+	enum mcde_display_power_mode (*get_power_mode)(
+		struct mcde_display_device *dev);
+
+	int (*try_video_mode)(struct mcde_display_device *dev,
+		struct mcde_video_mode *video_mode);
+	int (*set_video_mode)(struct mcde_display_device *dev,
+		struct mcde_video_mode *video_mode);
+	void (*get_video_mode)(struct mcde_display_device *dev,
+		struct mcde_video_mode *video_mode);
+
+	int (*set_pixel_format)(struct mcde_display_device *dev,
+		enum mcde_ovly_pix_fmt pix_fmt);
+	enum mcde_ovly_pix_fmt (*get_pixel_format)(
+		struct mcde_display_device *dev);
+	enum mcde_port_pix_fmt (*get_port_pixel_format)(
+		struct mcde_display_device *dev);
+
+	int (*set_rotation)(struct mcde_display_device *dev,
+		enum mcde_display_rotation rotation);
+	enum mcde_display_rotation (*get_rotation)(
+		struct mcde_display_device *dev);
+
+	int (*set_synchronized_update)(struct mcde_display_device *dev,
+		bool enable);
+	bool (*get_synchronized_update)(struct mcde_display_device *dev);
+
+	int (*apply_config)(struct mcde_display_device *dev);
+	int (*invalidate_area)(struct mcde_display_device *dev,
+						struct mcde_rectangle *area);
+	int (*update)(struct mcde_display_device *dev);
+	int (*prepare_for_update)(struct mcde_display_device *dev,
+		u16 x, u16 y, u16 w, u16 h);
+	int (*on_first_update)(struct mcde_display_device *dev);
+	int (*platform_enable)(struct mcde_display_device *dev);
+	int (*platform_disable)(struct mcde_display_device *dev);
+};
+
+struct mcde_display_driver {
+	int (*probe)(struct mcde_display_device *dev);
+	int (*remove)(struct mcde_display_device *dev);
+	void (*shutdown)(struct mcde_display_device *dev);
+	int (*suspend)(struct mcde_display_device *dev,
+		pm_message_t state);
+	int (*resume)(struct mcde_display_device *dev);
+
+	struct device_driver driver;
+};
+
+/* MCDE dsi (Used by MCDE display drivers) */
+
+int mcde_display_dsi_dcs_write(struct mcde_display_device *dev,
+	u8 cmd, u8 *data, int len);
+int mcde_display_dsi_dcs_read(struct mcde_display_device *dev,
+	u8 cmd, u8 *data, int *len);
+int mcde_display_dsi_bta_sync(struct mcde_display_device *dev);
+
+/* MCDE display bus */
+
+int mcde_display_driver_register(struct mcde_display_driver *drv);
+void mcde_display_driver_unregister(struct mcde_display_driver *drv);
+int mcde_display_device_register(struct mcde_display_device *dev);
+void mcde_display_device_unregister(struct mcde_display_device *dev);
+
+void mcde_display_init_device(struct mcde_display_device *dev);
+
+int mcde_display_init(void);
+void mcde_display_exit(void);
+
+#endif /* __MCDE_DISPLAY__H__ */
+
diff --git a/include/video/mcde_dss.h b/include/video/mcde_dss.h
new file mode 100644
index 00000000000..6a149a5dee6
--- /dev/null
+++ b/include/video/mcde_dss.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) ST-Ericsson AB 2010
+ *
+ * ST-Ericsson MCDE display sub system driver
+ *
+ * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __MCDE_DSS__H__
+#define __MCDE_DSS__H__
+
+#include <linux/kobject.h>
+#include <linux/notifier.h>
+
+#include "mcde.h"
+#include "mcde_display.h"
+
+/* Public MCDE dss (Used by MCDE fb ioctl & MCDE display sysfs) */
+int mcde_dss_open_channel(struct mcde_display_device *ddev);
+void mcde_dss_close_channel(struct mcde_display_device *ddev);
+int mcde_dss_enable_display(struct mcde_display_device *ddev);
+void mcde_dss_disable_display(struct mcde_display_device *ddev);
+int mcde_dss_apply_channel(struct mcde_display_device *ddev);
+struct mcde_overlay *mcde_dss_create_overlay(struct mcde_display_device *ddev,
+	struct mcde_overlay_info *info);
+void mcde_dss_destroy_overlay(struct mcde_overlay *ovl);
+int mcde_dss_enable_overlay(struct mcde_overlay *ovl);
+void mcde_dss_disable_overlay(struct mcde_overlay *ovl);
+int mcde_dss_apply_overlay(struct mcde_overlay *ovl,
+						struct mcde_overlay_info *info);
+int mcde_dss_update_overlay(struct mcde_overlay *ovl);
+
+void mcde_dss_get_native_resolution(struct mcde_display_device *ddev,
+	u16 *x_res, u16 *y_res);
+enum mcde_ovl_pix_fmt mcde_dss_get_default_color_format(
+	struct mcde_display_device *ddev);
+void mcde_dss_get_physical_size(struct mcde_display_device *ddev,
+	u16 *x_size, u16 *y_size); /* mm */
+
+int mcde_dss_try_video_mode(struct mcde_display_device *ddev,
+	struct mcde_video_mode *video_mode);
+int mcde_dss_set_video_mode(struct mcde_display_device *ddev,
+	struct mcde_video_mode *video_mode);
+void mcde_dss_get_video_mode(struct mcde_display_device *ddev,
+	struct mcde_video_mode *video_mode);
+
+int mcde_dss_set_pixel_format(struct mcde_display_device *ddev,
+	enum mcde_ovly_pix_fmt pix_fmt);
+int mcde_dss_get_pixel_format(struct mcde_display_device *ddev);
+
+int mcde_dss_set_rotation(struct mcde_display_device *ddev,
+	enum mcde_display_rotation rotation);
+enum mcde_display_rotation mcde_dss_get_rotation(
+	struct mcde_display_device *ddev);
+
+int mcde_dss_set_synchronized_update(struct mcde_display_device *ddev,
+	bool enable);
+bool mcde_dss_get_synchronized_update(struct mcde_display_device *ddev);
+
+/* MCDE dss events */
+
+/*      A display device and driver has been loaded, probed and bound */
+#define MCDE_DSS_EVENT_DISPLAY_REGISTERED    1
+/*      A display device has been removed */
+#define MCDE_DSS_EVENT_DISPLAY_UNREGISTERED  2
+
+/*      Note! Notifier callback will be called holding the dev sem */
+int mcde_dss_register_notifier(struct notifier_block *nb);
+int mcde_dss_unregister_notifier(struct notifier_block *nb);
+
+/* MCDE dss driver */
+
+int mcde_dss_init(void);
+void mcde_dss_exit(void);
+
+#endif /* __MCDE_DSS__H__ */
+
diff --git a/include/video/mcde_fb.h b/include/video/mcde_fb.h
new file mode 100644
index 00000000000..60d8b244688
--- /dev/null
+++ b/include/video/mcde_fb.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) ST-Ericsson AB 2010
+ *
+ * ST-Ericsson MCDE display sub system frame buffer driver
+ *
+ * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __MCDE_FB__H__
+#define __MCDE_FB__H__
+
+#include <linux/fb.h>
+#include <linux/ioctl.h>
+#if !defined(__KERNEL__) && !defined(_KERNEL)
+#include <stdint.h>
+#else
+#include <linux/types.h>
+#include <linux/hwmem.h>
+#endif
+
+#ifdef __KERNEL__
+#include "mcde_dss.h"
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif
+#endif
+
+#define MCDE_GET_BUFFER_NAME_IOC _IO('M', 1)
+
+#ifdef __KERNEL__
+#define to_mcde_fb(x) ((struct mcde_fb *)(x)->par)
+
+#define MCDE_FB_MAX_NUM_OVERLAYS 3
+
+struct mcde_fb {
+	int num_ovlys;
+	struct mcde_overlay *ovlys[MCDE_FB_MAX_NUM_OVERLAYS];
+	u32 pseudo_palette[17];
+	enum mcde_ovly_pix_fmt pix_fmt;
+	int id;
+	struct hwmem_alloc *alloc;
+	int alloc_name;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	struct early_suspend early_suspend;
+#endif
+};
+
+/* MCDE fbdev API */
+struct fb_info *mcde_fb_create(struct mcde_display_device *ddev,
+		uint16_t w, uint16_t h, uint16_t vw, uint16_t vh,
+		enum mcde_ovly_pix_fmt pix_fmt,	uint32_t rotate);
+
+int mcde_fb_attach_overlay(struct fb_info *fb_info,
+	struct mcde_overlay *ovl);
+void mcde_fb_destroy(struct fb_info *fb_info);
+
+/* MCDE fb driver */
+int mcde_fb_init(void);
+void mcde_fb_exit(void);
+#endif
+
+#endif /* __MCDE_FB__H__ */
+