diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-01-13 16:29:28 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-13 16:58:46 -0600 |
| commit | b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 (patch) | |
| tree | 86bc278f77095fe7d3279605e972eb45007e976c | |
| parent | 950264317eb9594b2b5ee2fb65206200a1c6007a (diff) | |
Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| -rw-r--r-- | board/freescale/mpc8572ds/tlb.c | 7 | ||||
| -rw-r--r-- | include/configs/MPC8572DS.h | 1 |
2 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 8d1f646fa..829896ac0 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 0), - /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, @@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4K, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 37c3f4200..6c7a36454 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -92,6 +92,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ +#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |