* Update Intel IXP4xx support

- Add IXP4xx NPE ethernet MAC support
- Add support for Intel IXDPG425 board
- Add support for Prodrive PDNB3 board
- Add IRQ support
Patch by Stefan Roese, 23 May 2006

[This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still
 sufferes from licensing issues. Blame Intel.]

8 files changed, 1350 insertions, 0 deletions

diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c
new file mode 100644
index 000000000..8630cc166
--- /dev/null
+++ b/board/prodrive/common/flash.c
@@ -0,0 +1,556 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*
+ * Functions
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_SST020:	printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST040:	printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CFG_FLASH_READ0];
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CFG_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF020:
+		info->flash_id += FLASH_SST020;
+		info->sector_count = 64;
+		info->size = 0x00040000;
+		break;				/* => 256 kB		*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF040:
+		info->flash_id += FLASH_SST040;
+		info->sector_count = 128;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00001000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect)
+		if (info->protect[sect])
+			prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+
+				/* re-enable interrupts if necessary */
+				if (flag) {
+					enable_interrupts();
+					flag = 0;
+				}
+
+				/* data polling for D7 */
+				start = get_timer (0);
+				while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+				       (CFG_FLASH_WORD_SIZE)0x00800080) {
+					if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+						return (1);
+				}
+			} else {
+				if (sect == s_first) {
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				}
+				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+			}
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i)
+			data = (data << 8) | *src++;
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *)cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
diff --git a/board/prodrive/common/fpga.c b/board/prodrive/common/fpga.c
new file mode 100644
index 000000000..f9412a21e
--- /dev/null
+++ b/board/prodrive/common/fpga.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2001-2004
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define FPGA_PRG		CFG_FPGA_PRG /* FPGA program pin (cpu output)*/
+#define FPGA_CLK		CFG_FPGA_CLK /* FPGA clk pin (cpu output)    */
+#define FPGA_DATA		CFG_FPGA_DATA /* FPGA data pin (cpu output)  */
+#define FPGA_DONE		CFG_FPGA_DONE /* FPGA done pin (cpu input)   */
+#define FPGA_INIT		CFG_FPGA_INIT /* FPGA init pin (cpu input)   */
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
+
+#ifndef OLD_VAL
+# define OLD_VAL		0
+#endif
+
+#if 0 /* test-only */
+#define FPGA_WRITE_1 { \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set clock to 0 */ \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set data to 1  */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 { \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set clock to 0 */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | 0        );  /* set data to 0  */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0        );  /* set clock to 1 */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+#else
+#define FPGA_WRITE_1 { \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set data to 1  */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 { \
+		SET_FPGA(OLD_VAL | FPGA_PRG | 0        | 0        );   /* set data to 0  */	\
+		SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0        );}  /* set data to 1  */
+#endif
+
+static int fpga_boot(unsigned char *fpgadata, int size)
+{
+	int i,index,len;
+	int count;
+	int j;
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = fpgadata[index];
+		DBG("FPGA: %s\n", &(fpgadata[index+1]));
+		index += len+3;
+	}
+
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
+		    (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
+			break; /* preamble found */
+		else
+			index++;
+	}
+
+	DBG("FPGA: configdata starts at position 0x%x\n",index);
+	DBG("FPGA: length of fpga-data %d\n", size-index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);            /* set pins to high */
+
+	DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+	DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA(0 | FPGA_CLK | FPGA_DATA);             /* set prog active */
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (FPGA_INIT_STATE) {
+		udelay(1000); /* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			DBG("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+	DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+	/* deassert PROGRAM* */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);           /* set prog inactive */
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(FPGA_INIT_STATE)) {
+		udelay(1000); /* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+	DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+	DBG("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i=index; i<size; i++) {
+		for (j=0; j<8; j++) {
+			if ((fpgadata[i] & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			fpgadata[i] <<= 1;
+		}
+	}
+
+	DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+	DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(FPGA_DONE_STATE)) {
+		udelay(1000); /* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	DBG("FPGA: Booting successful!\n");
+	return 0;
+}
diff --git a/board/prodrive/pdnb3/Makefile b/board/prodrive/pdnb3/Makefile
new file mode 100644
index 000000000..f3cd5a3f1
--- /dev/null
+++ b/board/prodrive/pdnb3/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= flash.o pdnb3.o nand.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/prodrive/pdnb3/config.mk b/board/prodrive/pdnb3/config.mk
new file mode 100644
index 000000000..6b0f18b30
--- /dev/null
+++ b/board/prodrive/pdnb3/config.mk
@@ -0,0 +1,4 @@
+TEXT_BASE = 0x01f00000
+
+# include NPE ethernet driver
+BOARDLIBS = cpu/ixp/npe/libnpe.a
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
new file mode 100644
index 000000000..d0e5fe703
--- /dev/null
+++ b/board/prodrive/pdnb3/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ixp425.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*
+ * Prototypes
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+
+static inline ulong ld(ulong x)
+{
+	ulong k = 0;
+
+	while (x >>= 1)
+		++k;
+
+	return k;
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; i++)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN)
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+
+	/* Reconfigure CS0 to actual FLASH size */
+	*IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10);
+
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
+		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+	/* Environment protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+	/* Redundant environment protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR_REDUND,
+		      CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+	flash_info[0].size = size;
+
+	return size;
+}
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
new file mode 100644
index 000000000..1931d64de
--- /dev/null
+++ b/board/prodrive/pdnb3/nand.c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+
+struct pdnb3_ndfc_regs {
+	uchar cmd;
+	uchar wait;
+	uchar addr;
+	uchar term;
+	uchar data;
+};
+
+static u8 hwctl;
+static struct pdnb3_ndfc_regs *pdnb3_ndfc;
+
+#define readb(addr)	*(volatile u_char *)(addr)
+#define readl(addr)	*(volatile u_long *)(addr)
+#define writeb(d,addr)	*(volatile u_char *)(addr) = (d)
+
+/*
+ * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
+ * the NAND devices.  The NDFC has command, address and data registers that
+ * when accessed will set up the NAND flash pins appropriately.  We'll use the
+ * hwcontrol function to save the configuration in a global variable.
+ * We can then use this information in the read and write functions to
+ * determine which NDFC register to access.
+ *
+ * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
+ */
+static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		hwctl |= 0x1;
+		break;
+	case NAND_CTL_CLRCLE:
+		hwctl &= ~0x1;
+		break;
+
+	case NAND_CTL_SETALE:
+		hwctl |= 0x2;
+		break;
+	case NAND_CTL_CLRALE:
+		hwctl &= ~0x2;
+		break;
+
+	case NAND_CTL_SETNCE:
+		break;
+	case NAND_CTL_CLRNCE:
+		writeb(0x00, &(pdnb3_ndfc->term));
+		break;
+	}
+}
+
+static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+	if (hwctl & 0x1)
+		writeb(byte, &(pdnb3_ndfc->cmd));
+	else if (hwctl & 0x2)
+		writeb(byte, &(pdnb3_ndfc->addr));
+	else
+		writeb(byte, &(pdnb3_ndfc->data));
+}
+
+static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
+{
+	return readb(&(pdnb3_ndfc->data));
+}
+
+static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if (hwctl & 0x1)
+			writeb(buf[i], &(pdnb3_ndfc->cmd));
+		else if (hwctl & 0x2)
+			writeb(buf[i], &(pdnb3_ndfc->addr));
+		else
+			writeb(buf[i], &(pdnb3_ndfc->data));
+	}
+}
+
+static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	int i;
+
+	if (len % 4) {
+		for (i = 0; i < len; i++)
+			buf[i] = readb(&(pdnb3_ndfc->data));
+	} else {
+		ulong *ptr = (ulong *)buf;
+		int count = len >> 2;
+
+		for (i = 0; i < count; i++)
+			*ptr++ = readl(&(pdnb3_ndfc->data));
+	}
+}
+
+static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != readb(&(pdnb3_ndfc->data)))
+			return i;
+
+	return 0;
+}
+
+static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
+{
+	volatile u_char val;
+
+	/*
+	 * Blocking read to wait for NAND to be ready
+	 */
+	val = readb(&(pdnb3_ndfc->wait));
+
+	/*
+	 * Return always true
+	 */
+	return 1;
+}
+
+void board_nand_init(struct nand_chip *nand)
+{
+	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
+
+	nand->eccmode = NAND_ECC_SOFT;
+
+	/* Set address of NAND IO lines (Using Linear Data Access Region) */
+	nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
+	nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
+	/* Reference hardware control function */
+	nand->hwcontrol  = pdnb3_nand_hwcontrol;
+	/* Set command delay time */
+	nand->hwcontrol  = pdnb3_nand_hwcontrol;
+	nand->write_byte = pdnb3_nand_write_byte;
+	nand->read_byte  = pdnb3_nand_read_byte;
+	nand->write_buf  = pdnb3_nand_write_buf;
+	nand->read_buf   = pdnb3_nand_read_buf;
+	nand->verify_buf = pdnb3_nand_verify_buf;
+	nand->dev_ready  = pdnb3_nand_dev_ready;
+}
+#endif
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
new file mode 100644
index 000000000..e2fed5d74
--- /dev/null
+++ b/board/prodrive/pdnb3/pdnb3.c
@@ -0,0 +1,249 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/ixp425.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* predefine these here for FPGA programming (before including fpga.c) */
+#define SET_FPGA(data)	*IXP425_GPIO_GPOUTR = (data)
+#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_DONE)
+#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_INIT)
+#define OLD_VAL		old_val
+
+static unsigned long old_val = 0;
+
+/*
+ * include common fpga code (for prodrive boards)
+ */
+#include "../common/fpga.c"
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_post_init(void)
+{
+	return (0);
+}
+
+int board_init(void)
+{
+	/* arch number of PDNB3 */
+	gd->bd->bi_arch_number = MACH_TYPE_PDNB3;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_ENABLE(CFG_GPIO_FPGA_RESET);
+
+	GPIO_OUTPUT_SET(CFG_GPIO_SYS_RUNNING);
+	GPIO_OUTPUT_ENABLE(CFG_GPIO_SYS_RUNNING);
+
+	/*
+	 * Setup GPIO's for FPGA programming
+	 */
+	GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG);
+	GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK);
+	GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA);
+	GPIO_OUTPUT_ENABLE(CFG_GPIO_PRG);
+	GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK);
+	GPIO_OUTPUT_ENABLE(CFG_GPIO_DATA);
+	GPIO_OUTPUT_DISABLE(CFG_GPIO_INIT);
+	GPIO_OUTPUT_DISABLE(CFG_GPIO_DONE);
+
+	/*
+	 * Setup GPIO's for interrupts
+	 */
+	GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTORE_INT);
+	GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTORE_INT);
+	GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTART_INT);
+	GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTART_INT);
+
+	/*
+	 * Setup GPIO's for 33MHz clock output
+	 */
+	*IXP425_GPIO_GPCLKR = 0x01FF0000;
+	GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK_33M);
+
+	/*
+	 * Setup other chip select's
+	 */
+	*IXP425_EXP_CS1 = CFG_EXP_CS1;
+
+	return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: PDNB3");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+int do_fpga_boot(unsigned char *fpgadata)
+{
+	unsigned char *dst;
+	int status;
+	int index;
+	int i;
+	ulong len = CFG_MALLOC_LEN;
+
+	/*
+	 * Setup GPIO's for FPGA programming
+	 */
+	GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG);
+	GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK);
+	GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA);
+
+	/*
+	 * Save value so no readback is required upon programming
+	 */
+	old_val = *IXP425_GPIO_GPOUTR;
+
+	/*
+	 * First try to decompress fpga image (gzip compressed?)
+	 */
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf("Error: Image has to be gzipp'ed!\n");
+		return -1;
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=5; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA
+	 */
+	GPIO_OUTPUT_CLEAR(CFG_GPIO_FPGA_RESET);
+	udelay(10);
+	GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET);
+
+	return (0);
+}
+
+int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+
+	if (argc < 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	return do_fpga_boot((unsigned char *)addr);
+}
+
+U_BOOT_CMD(
+	fpga,     2,     0,      do_fpga,
+	"fpga    - boot FPGA\n",
+	"address size\n    - boot FPGA with gzipped image at <address>\n"
+);
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_PCI)
+extern struct pci_controller hose;
+extern void pci_ixp_init(struct pci_controller * hose);
+
+void pci_init_board(void)
+{
+	extern void pci_ixp_init (struct pci_controller *hose);
+
+	pci_ixp_init(&hose);
+}
+#endif
diff --git a/board/prodrive/pdnb3/u-boot.lds b/board/prodrive/pdnb3/u-boot.lds
new file mode 100644
index 000000000..f05f09344
--- /dev/null
+++ b/board/prodrive/pdnb3/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/ixp/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}