diff options
| author | Torbjorn Svensson <torbjorn.x.svensson@stericsson.com> | 2010-12-15 12:05:18 +0100 |
|---|---|---|
| committer | Michael BRANDT <michael.brandt@stericsson.com> | 2011-01-18 09:07:11 +0100 |
| commit | 80c29457c21dbe1f9994bf2d173c329cf3c7227a (patch) | |
| tree | 9c3ca1b1f6a9944fdae53e29d14c6950a39307b1 /board/st/u8500/mcde_regs.h | |
| parent | c6458cdfa19cb2fdc37febf8341efcc5fb023bbf (diff) | |
U8500: Generic display driver
This patch introduces combined DSI and DPI display support for u-boot.
The code is also similar to the kernel code for easy maintenance.
ST-Ericsson ID: ER319241
ST-Ericsson FOSS-OUT ID: STETL-FOSS-OUT-10069
Change-Id: Ic232b6f738348cbedb67e27418678ddd223d7800
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/11038
Reviewed-by: Jimmy RUBIN <jimmy.rubin@stericsson.com>
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Torbjorn SVENSSON <torbjorn.x.svensson@stericsson.com>
Diffstat (limited to 'board/st/u8500/mcde_regs.h')
| -rw-r--r-- | board/st/u8500/mcde_regs.h | 38 |
1 files changed, 21 insertions, 17 deletions
diff --git a/board/st/u8500/mcde_regs.h b/board/st/u8500/mcde_regs.h index d4682b860..9e25f2dfe 100644 --- a/board/st/u8500/mcde_regs.h +++ b/board/st/u8500/mcde_regs.h @@ -3055,9 +3055,13 @@ #define MCDE_CRB1_CDWIN_12BBP_C2 2 #define MCDE_CRB1_CDWIN_16BBP_C1 3 #define MCDE_CRB1_CDWIN_16BBP_C2 4 -#define MCDE_CRB1_CDWIN_18BBP_C1 5 -#define MCDE_CRB1_CDWIN_18BBP_C2 6 -#define MCDE_CRB1_CDWIN_24BBP 7 +#define MCDE_CRB1_CDWIN_V1_18BBP_C1 5 +#define MCDE_CRB1_CDWIN_V1_18BBP_C2 6 +#define MCDE_CRB1_CDWIN_V1_24BBP 7 +#define MCDE_CRB1_CDWIN_V2_16BBP_C3 5 +#define MCDE_CRB1_CDWIN_V2_18BBP_C1 6 +#define MCDE_CRB1_CDWIN_V2_18BBP_C2 7 +#define MCDE_CRB1_CDWIN_V2_24BBP 8 #define MCDE_CRB1_CDWIN_ENUM(__x) \ MCDE_VAL2REG(MCDE_CRB1, CDWIN, MCDE_CRB1_CDWIN_##__x) #define MCDE_CRB1_CDWIN(__x) \ @@ -3507,23 +3511,23 @@ MCDE_VAL2REG(MCDE_TVTIM1B, DHO, __x) #define MCDE_TVLBALWA 0x00000850 #define MCDE_TVLBALWA_GROUPOFFSET 0x200 -#define MCDE_TVLBALWA_ALW_SHIFT 0 -#define MCDE_TVLBALWA_ALW_MASK 0x000007FF -#define MCDE_TVLBALWA_ALW(__x) \ - MCDE_VAL2REG(MCDE_TVLBALWA, ALW, __x) #define MCDE_TVLBALWA_LBW_SHIFT 16 #define MCDE_TVLBALWA_LBW_MASK 0x07FF0000 #define MCDE_TVLBALWA_LBW(__x) \ MCDE_VAL2REG(MCDE_TVLBALWA, LBW, __x) +#define MCDE_TVLBALWA_ALW_SHIFT 0 +#define MCDE_TVLBALWA_ALW_MASK 0x000007FF +#define MCDE_TVLBALWA_ALW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWA, ALW, __x) #define MCDE_TVLBALWB 0x00000A50 -#define MCDE_TVLBALWB_ALW_SHIFT 0 -#define MCDE_TVLBALWB_ALW_MASK 0x000007FF -#define MCDE_TVLBALWB_ALW(__x) \ - MCDE_VAL2REG(MCDE_TVLBALWB, ALW, __x) #define MCDE_TVLBALWB_LBW_SHIFT 16 #define MCDE_TVLBALWB_LBW_MASK 0x07FF0000 #define MCDE_TVLBALWB_LBW(__x) \ MCDE_VAL2REG(MCDE_TVLBALWB, LBW, __x) +#define MCDE_TVLBALWB_ALW_SHIFT 0 +#define MCDE_TVLBALWB_ALW_MASK 0x000007FF +#define MCDE_TVLBALWB_ALW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWB, ALW, __x) #define MCDE_TVBL2A 0x00000854 #define MCDE_TVBL2A_GROUPOFFSET 0x200 #define MCDE_TVBL2A_BEL2_SHIFT 0 @@ -3962,9 +3966,9 @@ #define MCDE_CTRLA_FORMID_DSI0VID 0 #define MCDE_CTRLA_FORMID_DSI0CMD 1 #define MCDE_CTRLA_FORMID_DSI1VID 2 -#define MCDE_CTRLA_FORMID_DSI1CMD 0 -#define MCDE_CTRLA_FORMID_DSI2VID 1 -#define MCDE_CTRLA_FORMID_DSI2CMD 2 +#define MCDE_CTRLA_FORMID_DSI1CMD 3 +#define MCDE_CTRLA_FORMID_DSI2VID 4 +#define MCDE_CTRLA_FORMID_DSI2CMD 5 #define MCDE_CTRLA_FORMID_DPIA 0 #define MCDE_CTRLA_FORMID_DPIB 1 #define MCDE_CTRLA_FORMID_ENUM(__x) \ @@ -3998,9 +4002,9 @@ #define MCDE_CTRLB_FORMID_DSI0VID 0 #define MCDE_CTRLB_FORMID_DSI0CMD 1 #define MCDE_CTRLB_FORMID_DSI1VID 2 -#define MCDE_CTRLB_FORMID_DSI1CMD 0 -#define MCDE_CTRLB_FORMID_DSI2VID 1 -#define MCDE_CTRLB_FORMID_DSI2CMD 2 +#define MCDE_CTRLB_FORMID_DSI1CMD 3 +#define MCDE_CTRLB_FORMID_DSI2VID 4 +#define MCDE_CTRLB_FORMID_DSI2CMD 5 #define MCDE_CTRLB_FORMID_DPIA 0 #define MCDE_CTRLB_FORMID_DPIB 1 #define MCDE_CTRLB_FORMID_ENUM(__x) \ |