prcm: fix DB8500v2 TCDM base address and I2C chip id

Handle the changed TCDM base address on DB8500v2, and the required chip
bits to the I2C slave address.  Based on the Linux modifications.

Change-Id: I9fc8df1553824bd03a908a5c4285be284ea158db
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/4213
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>

2 files changed, 52 insertions, 181 deletions

diff --git a/board/st/u8500/prcmu-fw.h b/board/st/u8500/prcmu-fw.h
deleted file mode 100644
index 0e4362629..000000000
--- a/board/st/u8500/prcmu-fw.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson SA
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * Copied from the Linux version:
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- */
-
-#ifndef __MACH_PRCMU_FW_V1_H
-#define __MACH_PRCMU_FW_V1_H
-
-#include "prcmu-fw-defs_v1.h"
-
-#define _PRCMU_TCDM_BASE    U8500_PRCMU_TCDM_BASE
-#define PRCM_BOOT_STATUS    (_PRCMU_TCDM_BASE + 0xFFF)
-#define PRCM_ROMCODE_A2P    (_PRCMU_TCDM_BASE + 0xFFE)
-#define PRCM_ROMCODE_P2A    (_PRCMU_TCDM_BASE + 0xFFD)
-#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC)      /* 4 BYTES */
-
-
-#define _PRCM_MBOX_HEADER	    	(_PRCMU_TCDM_BASE + 0xFE8)/*16 bytes*/
-#define PRCM_MBOX_HEADER_REQ_MB0	(_PRCM_MBOX_HEADER + 0x0)
-#define PRCM_MBOX_HEADER_REQ_MB1	(_PRCM_MBOX_HEADER + 0x1)
-#define PRCM_MBOX_HEADER_REQ_MB2	(_PRCM_MBOX_HEADER + 0x2)
-#define PRCM_MBOX_HEADER_REQ_MB3	(_PRCM_MBOX_HEADER + 0x3)
-#define PRCM_MBOX_HEADER_REQ_MB4	(_PRCM_MBOX_HEADER + 0x4)
-#define PRCM_MBOX_HEADER_REQ_MB5	(_PRCM_MBOX_HEADER + 0x5)
-#define PRCM_MBOX_HEADER_REQ_MB6	(_PRCM_MBOX_HEADER + 0x6)
-#define PRCM_MBOX_HEADER_REQ_MB7	(_PRCM_MBOX_HEADER + 0x7)
-#define PRCM_MBOX_HEADER_ACK_MB0	(_PRCM_MBOX_HEADER + 0x8)
-#define PRCM_MBOX_HEADER_ACK_MB1	(_PRCM_MBOX_HEADER + 0x9)
-#define PRCM_MBOX_HEADER_ACK_MB2	(_PRCM_MBOX_HEADER + 0xA)
-#define PRCM_MBOX_HEADER_ACK_MB3	(_PRCM_MBOX_HEADER + 0xB)
-#define PRCM_MBOX_HEADER_ACK_MB4	(_PRCM_MBOX_HEADER + 0xC)
-#define PRCM_MBOX_HEADER_ACK_MB5	(_PRCM_MBOX_HEADER + 0xD)
-#define PRCM_MBOX_HEADER_ACK_MB6	(_PRCM_MBOX_HEADER + 0xE)
-#define PRCM_MBOX_HEADER_ACK_MB7	(_PRCM_MBOX_HEADER + 0xF)
-
-/*Req Mailboxes */
-#define PRCM_REQ_MB0        (_PRCMU_TCDM_BASE + 0xFDC)    /* 12 bytes  */
-#define PRCM_REQ_MB1        (_PRCMU_TCDM_BASE + 0xFD0)    /* 12 bytes  */
-#define PRCM_REQ_MB2        (_PRCMU_TCDM_BASE + 0xFC0)    /* 16 bytes  */
-#define PRCM_REQ_MB3        (_PRCMU_TCDM_BASE + 0xE4C)    /* 372 bytes  */
-#define PRCM_REQ_MB4        (_PRCMU_TCDM_BASE + 0xE48)    /* 4 bytes  */
-#define PRCM_REQ_MB5        (_PRCMU_TCDM_BASE + 0xE44)    /* 4 bytes  */
-#define PRCM_REQ_MB6        (_PRCMU_TCDM_BASE + 0xE40)    /* 4 bytes  */
-#define PRCM_REQ_MB7        (_PRCMU_TCDM_BASE + 0xE3C)    /* 4 bytes  */
-
-/*Ack Mailboxes */
-#define PRCM_ACK_MB0        (_PRCMU_TCDM_BASE + 0xE08)    /* 52 bytes  */
-#define PRCM_ACK_MB1        (_PRCMU_TCDM_BASE + 0xE04)    /* 4 bytes */
-#define PRCM_ACK_MB2        (_PRCMU_TCDM_BASE + 0xE00)    /* 4 bytes */
-#define PRCM_ACK_MB3        (_PRCMU_TCDM_BASE + 0xDFC)    /* 4 bytes */
-#define PRCM_ACK_MB4        (_PRCMU_TCDM_BASE + 0xDF8)    /* 4 bytes */
-#define PRCM_ACK_MB5        (_PRCMU_TCDM_BASE + 0xDF4)    /* 4 bytes */
-#define PRCM_ACK_MB6        (_PRCMU_TCDM_BASE + 0xDF0)    /* 4 bytes */
-#define PRCM_ACK_MB7	    (_PRCMU_TCDM_BASE + 0xDEC)    /* 4 bytes  */
-
-/* Mailbox 0 REQs */
-#define PRCM_REQ_MB0_PWRSTTRH		(PRCM_REQ_MB0 + 0x0)
-#define PRCM_REQ_MB0_PWRSTTRH_APPWRST	(PRCM_REQ_MB0 + 0x0)
-#define PRCM_REQ_MB0_PWRSTTRH_APPLLST	(PRCM_REQ_MB0 + 0x1)
-#define PRCM_REQ_MB0_PWRSTTRH_ULPCLKST	(PRCM_REQ_MB0 + 0x2)
-#define PRCM_REQ_MB0_PWRSTTRH_BYTEFILL	(PRCM_REQ_MB0 + 0x3)
-#define PRCM_REQ_MB0_WKUP_8500	(PRCM_REQ_MB0 + 0x4)
-#define PRCM_REQ_MB0_WKUP_4500	(PRCM_REQ_MB0 + 0x8)
-
-
-/* Mailbox 0 ACKs */
-#define PRCM_ACK_MB0_AP_PWRST_STATUS	(PRCM_ACK_MB0 + 0x0)
-#define PRCM_ACK_MB0_PINGPONG_RDP	(PRCM_ACK_MB0 + 0x1)
-#define PRCM_ACK_MB0_PINGPONG_WKUP_RST_0 (PRCM_ACK_MB0 + 0x2)
-#define PRCM_ACK_MB0_PINGPONG_WKUP_RST_1 (PRCM_ACK_MB0 + 0x3)
-#define PRCM_ACK_MB0_WK0_EVENT_8500     (_PRCMU_TCDM_BASE + 0xE0C)
-#define PRCM_ACK_MB0_WK0_EVENT_4500     (_PRCMU_TCDM_BASE + 0xE10)
-#define PRCM_ACK_MB0_WK1_EVENT_8500     (_PRCMU_TCDM_BASE + 0xE24)
-#define PRCM_ACK_MB0_WK1_EVENT_4500     (_PRCMU_TCDM_BASE + 0xE28)
-#define PRCM_ACK_MB0_EVENT_4500_NUMBERS	20
-
-
-/* Mailbox 1 Requests */
-#define PRCM_REQ_MB1_ARMOPP     (PRCM_REQ_MB1 + 0x0)
-#define PRCM_REQ_MB1_APEOPP     (PRCM_REQ_MB1 + 0x1)
-#define PRCM_REQ_MB1_BOOSTOPP   (PRCM_REQ_MB1 + 0x2)
-
-/* Mailbox 1 ACKs */
-#define PRCM_ACK_MB1_CURR_ARMOPP        (PRCM_ACK_MB1 + 0x0)
-#define PRCM_ACK_MB1_CURR_APEOPP        (PRCM_ACK_MB1 + 0x1)
-#define PRCM_ACK_MB1_CURR_BOOSTOPP      (PRCM_ACK_MB1 + 0x2)
-#define PRCM_ACK_MB1_CURR_DVFS_STATUS   (PRCM_ACK_MB1 + 0x3)
-
-/* Mailbox 2 REQs */
-#define PRCM_REQ_MB2_DPS_SVAMMDSP        (PRCM_REQ_MB2 + 0x0)
-#define PRCM_REQ_MB2_DPS_SVAPIPE         (PRCM_REQ_MB2 + 0x1)
-#define PRCM_REQ_MB2_DPS_SIAMMDSP        (PRCM_REQ_MB2 + 0x2)
-#define PRCM_REQ_MB2_DPS_SIAPIPE         (PRCM_REQ_MB2 + 0x3)
-#define PRCM_REQ_MB2_DPS_SGA             (PRCM_REQ_MB2 + 0x4)
-#define PRCM_REQ_MB2_DPS_B2R2MCDE        (PRCM_REQ_MB2 + 0x5)
-#define PRCM_REQ_MB2_DPS_ESRAM12         (PRCM_REQ_MB2 + 0x6)
-#define PRCM_REQ_MB2_DPS_ESRAM34         (PRCM_REQ_MB2 + 0x7)
-#define PRCM_REQ_MB2_AUTOPWR_APSLEEP     (PRCM_REQ_MB2 + 0x8)
-#define PRCM_REQ_MB2_AUTOPWR_APSLEEP_SIA_PWRON_ENABLE     (PRCM_REQ_MB2 + 0x9)
-#define PRCM_REQ_MB2_AUTOPWR_APSLEEP_SVA_PWRON_ENABLE     (PRCM_REQ_MB2 + 0xA)
-#define PRCM_REQ_MB2_AUTOPWR_APSLEEP_AUTO_PWRON_ENABLE     (PRCM_REQ_MB2 + 0xB)
-#define PRCM_REQ_MB2_AUTOPWR_APIDLE     (PRCM_REQ_MB2 + 0xC)
-#define PRCM_REQ_MB2_AUTOPWR_APIDLE_SIA_PWRON_ENABLE     (PRCM_REQ_MB2 + 0xD)
-#define PRCM_REQ_MB2_AUTOPWR_APIDLE_SVA_PWRON_ENABLE     (PRCM_REQ_MB2 + 0xE)
-#define PRCM_REQ_MB2_AUTOPWR_APIDLE_AUTO_PWRON_ENABLE     (PRCM_REQ_MB2 + 0xF)
-
-/* Mailbox 2 ACKs */
-#define PRCM_ACK_MB2_DPS_STATUS          (PRCM_ACK_MB2 + 0x0)
-
-/* Mailbox 5 Requests */
-#define PRCM_REQ_MB5_I2COPTYPE_REG	(PRCM_REQ_MB5 + 0x0)
-#define PRCM_REQ_MB5_BIT_FIELDS		(PRCM_REQ_MB5 + 0x1)
-#define PRCM_REQ_MB5_I2CSLAVE		(PRCM_REQ_MB5 + 0x2)
-#define PRCM_REQ_MB5_I2CVAL		(PRCM_REQ_MB5 + 0x3)
-
-/* Mailbox 5 ACKs */
-#define PRCM_ACK_MB5_STATUS	(PRCM_ACK_MB5 + 0x1)
-#define PRCM_ACK_MB5_SLAVE	(PRCM_ACK_MB5 + 0x2)
-#define PRCM_ACK_MB5_VAL	(PRCM_ACK_MB5 + 0x3)
-
-#define LOW_POWER_WAKEUP	1
-#define EXE_WAKEUP		0
-
-/* FIXME : Need to Cleanup Code */
-
-#define PRCM_SVAMMDSPSTATUS PRCM_REQ_MB6
-#define PRCM_SIAMMDSPSTATUS PRCM_REQ_MB7
-
-
-#define PRCM_XP70_TRIG_IT10	(1 << 0)
-#define PRCM_XP70_TRIG_IT11	(1 << 1)
-#define PRCM_XP70_TRIG_IT12	(1 << 2)
-#define PRCM_XP70_TRIG_IT14	(1 << 4)
-#define PRCM_XP70_TRIG_IT17	(1 << 5)
-
-enum mailbox_t {
-	REQ_MB0 = 0,	/* Uses XP70_IT_EVENT_10 */
-	REQ_MB1 = 1,	/* Uses XP70_IT_EVENT_11 */
-	REQ_MB2 = 2,	/* Uses XP70_IT_EVENT_12 */
-	REQ_MB5 = 5,	/* Uses XP70_IT_EVENT_17 */
-};
-
-/* Union declaration */
-
-
-
-/* ARM to XP70 mailbox definition */
-union req_mb0_t {
-	struct {
-		enum ap_pwrst_trans_t ap_pwrst_trans:8;
-		enum intr_wakeup_t fifo_4500wu:8;
-		enum ddr_pwrst_t ddr_pwrst:8;
-		unsigned int unused:8;
-	} req_field;
-	unsigned int complete_field;
-};
-
-/* mailbox definition for ARM/APE operation */
-union req_mb1_t {
-	struct {
-		enum arm_opp_t arm_opp:8;
-		enum ape_opp_t ape_opp:8;
-	} req_field;
-	unsigned short complete_field;
-};
-
-#endif /* __MACH_PRCMU_FW_V1_H */
diff --git a/board/st/u8500/prcmu.c b/board/st/u8500/prcmu.c
index 43e4cbef5..3c34e4f6f 100644
--- a/board/st/u8500/prcmu.c
+++ b/board/st/u8500/prcmu.c
@@ -23,7 +23,8 @@
 
 #include <asm/arch/ab8500.h>
 
-#include "prcmu-fw.h"
+#include "common.h"
+#include "prcmu-fw-defs_v1.h"
 
 #define DEBUG 0
 #define dbg_printk(format, arg...)			\
@@ -32,16 +33,59 @@
 
 #define PRCMU_BASE			U8500_PRCMU_BASE
 
-/* CPU mailbox registers */
-#define PRCM_MBOX_CPU_VAL       	(PRCMU_BASE + 0x0fc)
-#define PRCM_MBOX_CPU_SET       	(PRCMU_BASE + 0x100)
-#define PRCM_MBOX_CPU_CLR       	(PRCMU_BASE + 0x104)
+#define PRCM_MBOX_CPU_VAL		(PRCMU_BASE + 0x0fc)
+#define PRCM_MBOX_CPU_SET		(PRCMU_BASE + 0x100)
+
+#define PRCM_XP70_CUR_PWR_STATE		(tcdm_base + 0xFFC)
+
+#define PRCM_REQ_MB5			(tcdm_base + 0xE44)
+#define PRCM_ACK_MB5			(tcdm_base + 0xDF4)
+
+/* Mailbox 5 Requests */
+#define PRCM_REQ_MB5_I2COPTYPE_REG	(PRCM_REQ_MB5 + 0x0)
+#define PRCM_REQ_MB5_BIT_FIELDS		(PRCM_REQ_MB5 + 0x1)
+#define PRCM_REQ_MB5_I2CSLAVE		(PRCM_REQ_MB5 + 0x2)
+#define PRCM_REQ_MB5_I2CVAL		(PRCM_REQ_MB5 + 0x3)
+
+/* Mailbox 5 ACKs */
+#define PRCM_ACK_MB5_STATUS	(PRCM_ACK_MB5 + 0x1)
+#define PRCM_ACK_MB5_SLAVE	(PRCM_ACK_MB5 + 0x2)
+#define PRCM_ACK_MB5_VAL	(PRCM_ACK_MB5 + 0x3)
+
+#define PRCMU_I2C_WRITE(slave)	\
+	(((slave) << 1) | I2CWRITE | (cpu_is_u8500v2() ? (1 << 6) : 0))
+
+#define PRCMU_I2C_READ(slave) \
+	(((slave) << 1) | I2CREAD | (cpu_is_u8500v2() ? (1 << 6) : 0))
+
+enum mailbox_t {
+	REQ_MB0 = 0,	/* Uses XP70_IT_EVENT_10 */
+	REQ_MB1 = 1,	/* Uses XP70_IT_EVENT_11 */
+	REQ_MB2 = 2,	/* Uses XP70_IT_EVENT_12 */
+	REQ_MB5 = 5,	/* Uses XP70_IT_EVENT_17 */
+};
+
+static void *tcdm_base;
 
 static int prcmu_is_ready(void)
 {
-	int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
+	int ready;
+
+	if (!tcdm_base) {
+		if (cpu_is_u8500v1())
+			tcdm_base = (void *) U8500_PRCMU_TCDM_BASE_V1;
+		else if (cpu_is_u8500v2())
+			tcdm_base = (void *) U8500_PRCMU_TCDM_BASE;
+		else {
+			printf("PRCMU: Unsupported chip version\n");
+			return 0;
+		}
+	}
+
+	ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
 	if (!ready)
 		printf("PRCMU firmware not ready\n");
+
 	return ready;
 }
 
@@ -87,7 +131,7 @@ int prcmu_i2c_read(u8 reg, u16 slave)
 			reg, slave);
 
 	/* prepare the data for mailbox 5 */
-	writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG);
+	writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
 	writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
 	writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
 	writeb(0, PRCM_REQ_MB5_I2CVAL);
@@ -134,7 +178,7 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
 			reg, slave);
 
 	/* prepare the data for mailbox 5 */
-	writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG);
+	writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
 	writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
 	writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
 	writeb(reg_data, PRCM_REQ_MB5_I2CVAL);