MCDE: Update for DB8500 V2

This patch does the following:
* Adds support for DB8500 V2

ST Ericsson ID: AP 270849

Change-Id: Ica648dc1663b58ee3468e1dc8bd831ede56c102a
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/4418
Tested-by: Jimmy RUBIN <jimmy.rubin@stericsson.com>
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>

5 files changed, 906 insertions, 645 deletions

diff --git a/board/st/u8500/mcde.h b/board/st/u8500/mcde.h
index 592053cd3..b5d03762e 100644
--- a/board/st/u8500/mcde.h
+++ b/board/st/u8500/mcde.h
@@ -24,11 +24,17 @@ enum mcde_port_mode {
 /* MCDE fifos */
 enum mcde_fifo {
 	MCDE_FIFO_A  = 0,
+	MCDE_FIFO_B  = 1,
+	MCDE_FIFO_C0 = 2,
+	MCDE_FIFO_C1 = 3,
 };
 
 /* MCDE channels (pixel pipelines) */
 enum mcde_chnl {
+	MCDE_CHNL_A  = 0,
+	MCDE_CHNL_B  = 1,
 	MCDE_CHNL_C0 = 2,
+	MCDE_CHNL_C1 = 3,
 };
 
 /* Update sync mode */
@@ -63,6 +69,10 @@ enum mcde_port_pix_fmt {
 
 };
 
+/* DSI modes */
+#define DSI_VIDEO_MODE	0
+#define DSI_CMD_MODE	1
+
 struct mcde_chnl_state;
 
 struct mcde_chnl_state *mcde_chnl_get(enum mcde_chnl chnl_id,
diff --git a/board/st/u8500/mcde_display.c b/board/st/u8500/mcde_display.c
index b3116a03c..f3aa24bb9 100644
--- a/board/st/u8500/mcde_display.c
+++ b/board/st/u8500/mcde_display.c
@@ -189,13 +189,10 @@ static int mcde_display_power_init(void)
 {
 	int val;
 	int i;
-	int ret;
-
-	if (!cpu_is_u8500v11())
-		return 0;
 
 	/*
-	 * On v1.1 HREF boards (HREF+), Vaux1 needs to be enabled for the
+	 * On v1.1 HREF boards (HREF+) and V2 boards
+	 * Vaux1 needs to be enabled for the
 	 * display to work.  This is done by enabling the regulators in the
 	 * AB8500 via PRCMU I2C transactions.
 	 *
@@ -206,21 +203,18 @@ static int mcde_display_power_init(void)
 	 * Turn off and delay is required to have it work across soft reboots.
 	 */
 
-	ret = ab8500_read(AB8500_REGU_CTRL2,
+	val = ab8500_read(AB8500_REGU_CTRL2,
 		AB8500_REGU_VAUX12_REGU_REG);
-	if (ret < 0) {
+	if (val < 0) {
 		printf("Read vaux1 status failed\n");
-		goto out;
+		return -EINVAL;
 	}
 
-	val = ret;
-
 	/* Turn off */
-	ret = ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VAUX12_REGU_REG,
-			   val & ~MASK_LDO_VAUX1);
-	if (ret < 0) {
+	if (ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VAUX12_REGU_REG,
+			   val & ~MASK_LDO_VAUX1) < 0) {
 		printf("Turn off Vaux1 failed\n");
-		goto out;
+		return -EINVAL;
 	}
 
 	udelay(10 * 1000);
@@ -229,12 +223,11 @@ static int mcde_display_power_init(void)
 	/* Find voltage from vauxn table */
 	for (i = 0; i < ARRAY_SIZE(vauxn_table) ; i++) {
 		if (vauxn_table[i].voltage == CONFIG_SYS_DISPLAY_VOLTAGE) {
-			ret = ab8500_write(AB8500_REGU_CTRL2,
+			if (ab8500_write(AB8500_REGU_CTRL2,
 				AB8500_REGU_VAUX1_SEL_REG,
-				vauxn_table[i].regval);
-			if (ret < 0) {
+				vauxn_table[i].regval) < 0) {
 				printf("AB8500_REGU_VAUX1_SEL_REG failed\n");
-				goto out;
+				return -EINVAL;
 			}
 			break;
 		}
@@ -244,38 +237,34 @@ static int mcde_display_power_init(void)
 	val = val | (1 << MASK_LDO_VAUX1_SHIFT);
 
 	/* Turn on the supply */
-	ret = ab8500_write(AB8500_REGU_CTRL2,
-			AB8500_REGU_VAUX12_REGU_REG, val);
-	if (ret < 0) {
+	if (ab8500_write(AB8500_REGU_CTRL2,
+			AB8500_REGU_VAUX12_REGU_REG, val) < 0) {
 		printf("Turn on Vaux1 failed\n");
-		goto out;
+		return -EINVAL;
 	}
 
 	/*  DCI & CSI (DSI / PLL / Camera) */ /* Vana & Vpll HP mode */
-	ret = ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VPLLVANA_REGU_REG,
-						VANA_ENABLE_IN_HP_MODE);
-	if (ret < 0) {
+	if (ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VPLLVANA_REGU_REG,
+						VANA_ENABLE_IN_HP_MODE) < 0) {
 		printf("Turn on Vana failed\n");
-		goto out;
+		return -EINVAL;
 	}
 
 	/* Enable the PWM control for the backlight Main display */
-	ret = ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, ENABLE_PWM1);
-	if (ret < 0) {
+	if (ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG,
+							ENABLE_PWM1) < 0) {
 		printf("Enable PWM1 failed\n");
-		goto out;
+		return -EINVAL;
 	}
-	ret = ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL1_REG,
-						PWM_DUTY_LOW_1024_1024);
-	if (ret < 0) {
+	if (ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL1_REG,
+						PWM_DUTY_LOW_1024_1024) < 0) {
 		printf("PWM_DUTY_LOW_1024_1024 failed\n");
-		goto out;
+		return -EINVAL;
 	}
-	ret = ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL2_REG,
-						PWM_DUTY_HI_1024_1024);
-	if (ret < 0) {
+	if (ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL2_REG,
+						PWM_DUTY_HI_1024_1024) < 0) {
 		printf("PWM_DUTY_HI_1024_1024 failed\n");
-		goto out;
+		return -EINVAL;
 	}
 
 	if (!mcde_is_vaux1_enabled() || mcde_get_vaux1_voltage()
@@ -287,8 +276,6 @@ static int mcde_display_power_init(void)
 	}
 
 	return 0;
-out:
-	return ret;
 }
 
 
diff --git a/board/st/u8500/mcde_hw.c b/board/st/u8500/mcde_hw.c
index 67a36f5e9..a858e67aa 100644
--- a/board/st/u8500/mcde_hw.c
+++ b/board/st/u8500/mcde_hw.c
@@ -27,13 +27,13 @@
 u8 *mcdeio;
 u8 **dsiio;
 
-static inline u32 dsi_rreg(int __i, u32 __reg)
+static inline u32 dsi_rreg(int i, u32 reg)
 {
-	return readl(dsiio[__i] + __reg);
+	return readl(dsiio[i] + reg);
 }
-static inline void dsi_wreg(int __i, u32 __reg, u32 __val)
+static inline void dsi_wreg(int i, u32 reg, u32 val)
 {
-	writel(__val, dsiio[__i] + __reg);
+	writel(val, dsiio[i] + reg);
 }
 #define dsi_rfld(__i, __reg, __fld) \
 	((dsi_rreg(__i, __reg) & __reg##_##__fld##_MASK) >> \
@@ -43,13 +43,13 @@ static inline void dsi_wreg(int __i, u32 __reg, u32 __val)
 	~__reg##_##__fld##_MASK) | (((__val) << __reg##_##__fld##_SHIFT) & \
 		 __reg##_##__fld##_MASK))
 
-static inline u32 mcde_rreg(u32 __reg)
+static inline u32 mcde_rreg(u32 reg)
 {
-	return readl(mcdeio + __reg);
+	return readl(mcdeio + reg);
 }
-static inline void mcde_wreg(u32 __reg, u32 __val)
+static inline void mcde_wreg(u32 reg, u32 val)
 {
-	writel(__val, mcdeio + __reg);
+	writel(val, mcdeio + reg);
 }
 #define mcde_rfld(__reg, __fld) \
 	((mcde_rreg(__reg) & __reg##_##__fld##_MASK) >> \
@@ -127,10 +127,10 @@ struct chnl_regs {
 struct mcde_chnl_state {
 	t_bool inuse;
 	enum mcde_chnl id;
+	enum mcde_fifo fifo;
 	struct mcde_port port;
 	struct mcde_ovly_state *ovly0;
 	struct mcde_ovly_state *ovly1;
-	const struct chnl_config *cfg;
 	u32 transactionid;
 	u32 transactionid_regs;
 
@@ -154,7 +154,6 @@ static struct mcde_chnl_state channels[] = {
 	},
 };
 
-
 /* MCDE internal helpers */
 static u8 portfmt2dsipacking(enum mcde_port_pix_fmt pix_fmt)
 {
@@ -175,21 +174,98 @@ static u8 portfmt2bpp(enum mcde_port_pix_fmt pix_fmt)
 	}
 }
 
+static u8 get_dsi_formid(const struct mcde_port *port)
+{
+	if (port->ifc == DSI_VIDEO_MODE && port->link == 0)
+		return MCDE_CTRLA_FORMID_DSI0VID;
+	else if (port->ifc == DSI_VIDEO_MODE && port->link == 1)
+		return MCDE_CTRLA_FORMID_DSI1VID;
+	else if (port->ifc == DSI_VIDEO_MODE && port->link == 2)
+		return MCDE_CTRLA_FORMID_DSI2VID;
+	else if (port->ifc == DSI_CMD_MODE && port->link == 0)
+		return MCDE_CTRLA_FORMID_DSI0CMD;
+	else if (port->ifc == DSI_CMD_MODE && port->link == 1)
+		return MCDE_CTRLA_FORMID_DSI1CMD;
+	else if (port->ifc == DSI_CMD_MODE && port->link == 2)
+		return MCDE_CTRLA_FORMID_DSI2CMD;
+	return 0;
+}
+
 #define DSI_UNIT_INTERVAL_0	0x9
 
-void update_channel_static_registers(struct mcde_chnl_state *chnl)
+static int update_channel_static_registers(struct mcde_chnl_state *chnl)
 {
 	const struct mcde_port *port = &chnl->port;
 	int i = 0;
 	u8 idx = 2 * port->link + port->ifc;
 	u8 lnk = port->link;
-	/* Fifo & muxing */
-	mcde_wfld(MCDE_CONF0, SWAP_A_C0, TRUE);
-	mcde_wfld(MCDE_CR, FABMUX, FALSE);
+
+	if (!cpu_is_u8500v2()) {
+		/* Fifo & muxing */
+		mcde_wfld(MCDE_CONF0, SWAP_A_C0_V1, TRUE);
+		mcde_wfld(MCDE_CR, FABMUX_V1, FALSE);
+
+		if (port->ifc == DSI_VIDEO_MODE && port->link == 0)
+			mcde_wfld(MCDE_CR, DSIVID0_EN_V1, TRUE);
+		else if (port->ifc == DSI_VIDEO_MODE && port->link == 1)
+			mcde_wfld(MCDE_CR, DSIVID1_EN_V1, TRUE);
+		else if (port->ifc == DSI_VIDEO_MODE && port->link == 2)
+			mcde_wfld(MCDE_CR, DSIVID2_EN_V1, TRUE);
+		else if (port->ifc == DSI_CMD_MODE && port->link == 0)
+			mcde_wfld(MCDE_CR, DSICMD0_EN_V1, TRUE);
+		else if (port->ifc == DSI_CMD_MODE && port->link == 1)
+			mcde_wfld(MCDE_CR, DSICMD1_EN_V1, TRUE);
+		else if (port->ifc == DSI_CMD_MODE && port->link == 2)
+			mcde_wfld(MCDE_CR, DSICMD2_EN_V1, TRUE);
+
+		mcde_wreg(MCDE_CTRLC0, MCDE_CTRLC0_FIFOWTRMRK(0xa0));
+	} else {
+		switch (chnl->fifo) {
+		case MCDE_FIFO_A:
+			mcde_wreg(MCDE_CHNL0MUXING_V2 + chnl->id *
+			MCDE_CHNL0MUXING_V2_GROUPOFFSET,
+			MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(FIFO_A));
+			mcde_wfld(MCDE_CTRLA, FORMTYPE,
+					MCDE_CTRLA_FORMTYPE_DSI);
+			mcde_wfld(MCDE_CTRLA, FORMID,
+						get_dsi_formid(port));
+			mcde_wfld(MCDE_CTRLA, FIFOWTRMRK, 0x280);
+			break;
+		case MCDE_FIFO_B:
+			mcde_wreg(MCDE_CHNL0MUXING_V2 + chnl->id *
+			MCDE_CHNL0MUXING_V2_GROUPOFFSET,
+			MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(FIFO_B));
+			mcde_wfld(MCDE_CTRLB, FORMTYPE,
+					MCDE_CTRLB_FORMTYPE_DSI);
+			mcde_wfld(MCDE_CTRLB, FORMID,
+						get_dsi_formid(port));
+			mcde_wfld(MCDE_CTRLB, FIFOWTRMRK, 0x280);
+			break;
+		case MCDE_FIFO_C0:
+			mcde_wreg(MCDE_CHNL0MUXING_V2 + chnl->id *
+				MCDE_CHNL0MUXING_V2_GROUPOFFSET,
+				MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(FIFO_C0));
+			mcde_wfld(MCDE_CTRLC0, FORMTYPE,
+						MCDE_CTRLC0_FORMTYPE_DSI);
+			mcde_wfld(MCDE_CTRLC0, FORMID, get_dsi_formid(port));
+			mcde_wfld(MCDE_CTRLC0, FIFOWTRMRK, 0xa0);
+			break;
+		case MCDE_FIFO_C1:
+			mcde_wreg(MCDE_CHNL0MUXING_V2 + chnl->id *
+				MCDE_CHNL0MUXING_V2_GROUPOFFSET,
+				MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(FIFO_C1));
+			mcde_wfld(MCDE_CTRLC1, FORMTYPE,
+						MCDE_CTRLC1_FORMTYPE_DSI);
+			mcde_wfld(MCDE_CTRLC1, FORMID, get_dsi_formid(port));
+			mcde_wfld(MCDE_CTRLC1, FIFOWTRMRK, 0xa0);
+			break;
+		default:
+			return -EINVAL;
+		}
+	}
 
 	/* Formatter */
 	dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, LINK_EN, TRUE);
-
 	dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, BTA_EN, TRUE);
 	dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, READ_EN, TRUE);
 	dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, REG_TE_EN, TRUE);
@@ -209,7 +285,7 @@ void update_channel_static_registers(struct mcde_chnl_state *chnl)
 		DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME(1) |
 		DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME(1));
 	dsi_wfld(lnk, DSI_CMD_MODE_CTL, ARB_MODE, FALSE);
-	dsi_wfld(lnk, DSI_CMD_MODE_CTL, ARB_PRI, port->ifc == 1);
+	dsi_wfld(lnk, DSI_CMD_MODE_CTL, ARB_PRI, port->ifc == DSI_CMD_MODE);
 	dsi_wfld(lnk, DSI_CMD_MODE_CTL, TE_TIMEOUT, 0x3ff);
 	dsi_wreg(lnk, DSI_MCTL_MAIN_EN,
 		DSI_MCTL_MAIN_EN_PLL_START(TRUE) |
@@ -217,29 +293,18 @@ void update_channel_static_registers(struct mcde_chnl_state *chnl)
 		DSI_MCTL_MAIN_EN_DAT1_EN(TRUE) |
 		DSI_MCTL_MAIN_EN_DAT2_EN(port->phy.dsi.num_data_lanes
 			== 2) |
-		DSI_MCTL_MAIN_EN_IF1_EN(port->ifc == 0) |
-		DSI_MCTL_MAIN_EN_IF2_EN(port->ifc == 1));
+		DSI_MCTL_MAIN_EN_IF1_EN(port->ifc == DSI_VIDEO_MODE) |
+		DSI_MCTL_MAIN_EN_IF2_EN(port->ifc == DSI_CMD_MODE));
 	while (dsi_rfld(lnk, DSI_MCTL_MAIN_STS, CLKLANE_READY) == 0 ||
 	       dsi_rfld(lnk, DSI_MCTL_MAIN_STS, DAT1_READY) == 0 ||
 	       dsi_rfld(lnk, DSI_MCTL_MAIN_STS, DAT2_READY) == 0) {
 		mdelay(1);
-		if (i++ == 10)
+		if (i++ == 10) {
 			printf("DSI lane not ready (link=%d)!\n", lnk);
+			return -EINVAL;
+		}
 	}
 
-
-	if (port->ifc == 0 && port->link == 0)
-		mcde_wfld(MCDE_CR, DSIVID0_EN, TRUE);
-	else if (port->ifc == 0 && port->link == 1)
-		mcde_wfld(MCDE_CR, DSIVID1_EN, TRUE);
-	else if (port->ifc == 0 && port->link == 2)
-		mcde_wfld(MCDE_CR, DSIVID2_EN, TRUE);
-	else if (port->ifc == 1 && port->link == 0)
-		mcde_wfld(MCDE_CR, DSICMD0_EN, TRUE);
-	else if (port->ifc == 1 && port->link == 1)
-		mcde_wfld(MCDE_CR, DSICMD1_EN, TRUE);
-	else if (port->ifc == 1 && port->link == 2)
-		mcde_wfld(MCDE_CR, DSICMD2_EN, TRUE);
 	mcde_wreg(MCDE_DSIVID0CONF0 +
 		idx * MCDE_DSIVID0CONF0_GROUPOFFSET,
 		MCDE_DSIVID0CONF0_BLANKING(0) |
@@ -249,10 +314,10 @@ void update_channel_static_registers(struct mcde_chnl_state *chnl)
 		MCDE_DSIVID0CONF0_BYTE_SWAP(FALSE) |
 		MCDE_DSIVID0CONF0_DCSVID_NOTGEN(TRUE));
 
-	if (port->ifc == 0)
+	if (port->ifc == DSI_VIDEO_MODE)
 		dsi_wfld(port->link, DSI_CMD_MODE_CTL, IF1_ID,
 			port->phy.dsi.virt_id);
-	else if (port->ifc == 1)
+	else if (port->ifc == DSI_CMD_MODE)
 		dsi_wfld(port->link, DSI_CMD_MODE_CTL, IF2_ID,
 			port->phy.dsi.virt_id);
 
@@ -260,10 +325,11 @@ void update_channel_static_registers(struct mcde_chnl_state *chnl)
 	mcde_wreg(MCDE_VSCRC0,
 		MCDE_VSCRC0_VSPMIN(1) |
 		MCDE_VSCRC0_VSPMAX(0xff));
-	mcde_wreg(MCDE_CTRLC0, MCDE_CTRLC0_FIFOWTRMRK(0xa0));
 
 	mcde_wfld(MCDE_CR, MCDEEN, TRUE);
 	dbg_printk("Static registers setup, chnl=%d\n", chnl->id);
+
+	return 0;
 }
 
 static void update_overlay_registers(u8 idx, struct ovly_regs *regs,
@@ -310,9 +376,9 @@ static void update_overlay_registers(u8 idx, struct ovly_regs *regs,
 		MCDE_OVL0CR_OVLB(FALSE) |
 		MCDE_OVL0CR_FETCH_ROPC(0) |
 		MCDE_OVL0CR_STBPRIO(0) |
-		MCDE_OVL0CR_BURSTSIZE(11) | /* TODO: _HW_8W */
-		MCDE_OVL0CR_MAXOUTSTANDING(2) | /* TODO: get from ovly */
-		MCDE_OVL0CR_ROTBURSTSIZE(2)); /* TODO: _4W, calculate? */
+		MCDE_OVL0CR_BURSTSIZE_ENUM(HW_8W) |
+		MCDE_OVL0CR_MAXOUTSTANDING_ENUM(4_REQ) |
+		MCDE_OVL0CR_ROTBURSTSIZE_ENUM(HW_8W));
 	mcde_wreg(MCDE_OVL0CONF + idx * MCDE_OVL0CONF_GROUPOFFSET,
 		MCDE_OVL0CONF_PPL(ppl) |
 		MCDE_OVL0CONF_EXTSRC_ID(idx) |
@@ -360,8 +426,6 @@ void update_channel_registers(enum mcde_chnl chnl_id, struct chnl_regs *regs,
 		MCDE_CHNL0BCKGNDCOL_B(255) | /* TODO: Temp */
 		MCDE_CHNL0BCKGNDCOL_G(255) |
 		MCDE_CHNL0BCKGNDCOL_R(255));
-	mcde_wreg(MCDE_CHNL0PRIO + idx * MCDE_CHNL0PRIO_GROUPOFFSET,
-		MCDE_CHNL0PRIO_CHNLPRIO(0));
 
 	mcde_wfld(MCDE_CRC, POWEREN, TRUE);
 	mcde_wfld(MCDE_CRC, FLOEN, TRUE);
@@ -424,16 +488,19 @@ struct mcde_chnl_state *mcde_chnl_get(enum mcde_chnl chnl_id,
 	}
 
 	chnl->port = *port;
+	chnl->fifo = fifo;
+
+	if (update_channel_static_registers(chnl) < 0)
+		return ERR_PTR(-EINVAL);
+
 	chnl->synchronized_update = FALSE;
 	chnl->update_x = 0;
 	chnl->update_y = 0;
 	chnl->update_w = 0;
 	chnl->update_h = 0;
 	mcde_chnl_apply(chnl);
-
-	update_channel_static_registers(chnl);
-
 	chnl->inuse = TRUE;
+
 	return chnl;
 }
 
@@ -607,7 +674,7 @@ void mcde_ovly_apply(struct mcde_ovly_state *ovly)
 	case MCDE_OVLYPIXFMT_RGB888:
 		ovly->regs.bits_per_pixel = 24;
 		ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_RGB888;
-		ovly->regs.bgr = TRUE;
+		ovly->regs.bgr = FALSE;
 		ovly->regs.bebo = FALSE;
 		ovly->regs.opq = TRUE;
 		break;
diff --git a/board/st/u8500/mcde_regs.h b/board/st/u8500/mcde_regs.h
index 57433b810..d4682b860 100644
--- a/board/st/u8500/mcde_regs.h
+++ b/board/st/u8500/mcde_regs.h
@@ -16,58 +16,58 @@
 	(((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT)
 
 #define MCDE_CR 0x00000000
-#define MCDE_CR_DSICMD2_EN_SHIFT 0
-#define MCDE_CR_DSICMD2_EN_MASK 0x00000001
-#define MCDE_CR_DSICMD2_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSICMD2_EN, __x)
-#define MCDE_CR_DSICMD1_EN_SHIFT 1
-#define MCDE_CR_DSICMD1_EN_MASK 0x00000002
-#define MCDE_CR_DSICMD1_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSICMD1_EN, __x)
-#define MCDE_CR_DSICMD0_EN_SHIFT 2
-#define MCDE_CR_DSICMD0_EN_MASK 0x00000004
-#define MCDE_CR_DSICMD0_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSICMD0_EN, __x)
-#define MCDE_CR_DSIVID2_EN_SHIFT 3
-#define MCDE_CR_DSIVID2_EN_MASK 0x00000008
-#define MCDE_CR_DSIVID2_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSIVID2_EN, __x)
-#define MCDE_CR_DSIVID1_EN_SHIFT 4
-#define MCDE_CR_DSIVID1_EN_MASK 0x00000010
-#define MCDE_CR_DSIVID1_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSIVID1_EN, __x)
-#define MCDE_CR_DSIVID0_EN_SHIFT 5
-#define MCDE_CR_DSIVID0_EN_MASK 0x00000020
-#define MCDE_CR_DSIVID0_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSIVID0_EN, __x)
-#define MCDE_CR_DBIC1_EN_SHIFT 6
-#define MCDE_CR_DBIC1_EN_MASK 0x00000040
-#define MCDE_CR_DBIC1_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DBIC1_EN, __x)
-#define MCDE_CR_DBIC0_EN_SHIFT 7
-#define MCDE_CR_DBIC0_EN_MASK 0x00000080
-#define MCDE_CR_DBIC0_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DBIC0_EN, __x)
-#define MCDE_CR_DPIB_EN_SHIFT 8
-#define MCDE_CR_DPIB_EN_MASK 0x00000100
-#define MCDE_CR_DPIB_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DPIB_EN, __x)
-#define MCDE_CR_DPIA_EN_SHIFT 9
-#define MCDE_CR_DPIA_EN_MASK 0x00000200
-#define MCDE_CR_DPIA_EN(__x) \
-	MCDE_VAL2REG(MCDE_CR, DPIA_EN, __x)
+#define MCDE_CR_DSICMD2_EN_V1_SHIFT 0
+#define MCDE_CR_DSICMD2_EN_V1_MASK 0x00000001
+#define MCDE_CR_DSICMD2_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DSICMD2_EN_V1, __x)
+#define MCDE_CR_DSICMD1_EN_V1_SHIFT 1
+#define MCDE_CR_DSICMD1_EN_V1_MASK 0x00000002
+#define MCDE_CR_DSICMD1_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DSICMD1_EN_V1, __x)
+#define MCDE_CR_DSICMD0_EN_V1_SHIFT 2
+#define MCDE_CR_DSICMD0_EN_V1_MASK 0x00000004
+#define MCDE_CR_DSICMD0_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DSICMD0_EN_V1, __x)
+#define MCDE_CR_DSIVID2_EN_V1_SHIFT 3
+#define MCDE_CR_DSIVID2_EN_V1_MASK 0x00000008
+#define MCDE_CR_DSIVID2_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DSIVID2_EN_V1, __x)
+#define MCDE_CR_DSIVID1_EN_V1_SHIFT 4
+#define MCDE_CR_DSIVID1_EN_V1_MASK 0x00000010
+#define MCDE_CR_DSIVID1_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DSIVID1_EN_V1, __x)
+#define MCDE_CR_DSIVID0_EN_V1_SHIFT 5
+#define MCDE_CR_DSIVID0_EN_V1_MASK 0x00000020
+#define MCDE_CR_DSIVID0_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DSIVID0_EN_V1, __x)
+#define MCDE_CR_DBIC1_EN_V1_SHIFT 6
+#define MCDE_CR_DBIC1_EN_V1_MASK 0x00000040
+#define MCDE_CR_DBIC1_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DBIC1_EN_V1, __x)
+#define MCDE_CR_DBIC0_EN_V1_SHIFT 7
+#define MCDE_CR_DBIC0_EN_V1_MASK 0x00000080
+#define MCDE_CR_DBIC0_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DBIC0_EN_V1, __x)
+#define MCDE_CR_DPIB_EN_V1_SHIFT 8
+#define MCDE_CR_DPIB_EN_V1_MASK 0x00000100
+#define MCDE_CR_DPIB_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DPIB_EN_V1, __x)
+#define MCDE_CR_DPIA_EN_V1_SHIFT 9
+#define MCDE_CR_DPIA_EN_V1_MASK 0x00000200
+#define MCDE_CR_DPIA_EN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, DPIA_EN_V1, __x)
 #define MCDE_CR_IFIFOCTRLEN_SHIFT 15
 #define MCDE_CR_IFIFOCTRLEN_MASK 0x00008000
 #define MCDE_CR_IFIFOCTRLEN(__x) \
 	MCDE_VAL2REG(MCDE_CR, IFIFOCTRLEN, __x)
-#define MCDE_CR_F01MUX_SHIFT 16
-#define MCDE_CR_F01MUX_MASK 0x00010000
-#define MCDE_CR_F01MUX(__x) \
-	MCDE_VAL2REG(MCDE_CR, F01MUX, __x)
-#define MCDE_CR_FABMUX_SHIFT 17
-#define MCDE_CR_FABMUX_MASK 0x00020000
-#define MCDE_CR_FABMUX(__x) \
-	MCDE_VAL2REG(MCDE_CR, FABMUX, __x)
+#define MCDE_CR_F01MUX_V1_SHIFT 16
+#define MCDE_CR_F01MUX_V1_MASK 0x00010000
+#define MCDE_CR_F01MUX_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, F01MUX_V1, __x)
+#define MCDE_CR_FABMUX_V1_SHIFT 17
+#define MCDE_CR_FABMUX_V1_MASK 0x00020000
+#define MCDE_CR_FABMUX_V1(__x) \
+	MCDE_VAL2REG(MCDE_CR, FABMUX_V1, __x)
 #define MCDE_CR_AUTOCLKG_EN_SHIFT 30
 #define MCDE_CR_AUTOCLKG_EN_MASK 0x40000000
 #define MCDE_CR_AUTOCLKG_EN(__x) \
@@ -109,22 +109,22 @@
 #define MCDE_CONF0_SYNCMUX7_MASK 0x00000080
 #define MCDE_CONF0_SYNCMUX7(__x) \
 	MCDE_VAL2REG(MCDE_CONF0, SYNCMUX7, __x)
-#define MCDE_CONF0_SWAP_A_C0_SHIFT 8
-#define MCDE_CONF0_SWAP_A_C0_MASK 0x00000100
-#define MCDE_CONF0_SWAP_A_C0(__x) \
-	MCDE_VAL2REG(MCDE_CONF0, SWAP_A_C0, __x)
-#define MCDE_CONF0_SWAP_B_C1_SHIFT 9
-#define MCDE_CONF0_SWAP_B_C1_MASK 0x00000200
-#define MCDE_CONF0_SWAP_B_C1(__x) \
-	MCDE_VAL2REG(MCDE_CONF0, SWAP_B_C1, __x)
-#define MCDE_CONF0_FSYNCTRLA_SHIFT 10
-#define MCDE_CONF0_FSYNCTRLA_MASK 0x00000400
-#define MCDE_CONF0_FSYNCTRLA(__x) \
-	MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLA, __x)
-#define MCDE_CONF0_FSYNCTRLB_SHIFT 11
-#define MCDE_CONF0_FSYNCTRLB_MASK 0x00000800
-#define MCDE_CONF0_FSYNCTRLB(__x) \
-	MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLB, __x)
+#define MCDE_CONF0_SWAP_A_C0_V1_SHIFT 8
+#define MCDE_CONF0_SWAP_A_C0_V1_MASK 0x00000100
+#define MCDE_CONF0_SWAP_A_C0_V1(__x) \
+	MCDE_VAL2REG(MCDE_CONF0, SWAP_A_C0_V1, __x)
+#define MCDE_CONF0_SWAP_B_C1_V1_SHIFT 9
+#define MCDE_CONF0_SWAP_B_C1_V1_MASK 0x00000200
+#define MCDE_CONF0_SWAP_B_C1_V1(__x) \
+	MCDE_VAL2REG(MCDE_CONF0, SWAP_B_C1_V1, __x)
+#define MCDE_CONF0_FSYNCTRLA_V1_SHIFT 10
+#define MCDE_CONF0_FSYNCTRLA_V1_MASK 0x00000400
+#define MCDE_CONF0_FSYNCTRLA_V1(__x) \
+	MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLA_V1, __x)
+#define MCDE_CONF0_FSYNCTRLB_V1_SHIFT 11
+#define MCDE_CONF0_FSYNCTRLB_V1_MASK 0x00000800
+#define MCDE_CONF0_FSYNCTRLB_V1(__x) \
+	MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLB_V1, __x)
 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12
 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL(__x) \
@@ -582,109 +582,109 @@
 	MCDE_VAL2REG(MCDE_PID, MAJOR_VERSION, __x)
 #define MCDE_EXTSRC0A0 0x00000200
 #define MCDE_EXTSRC0A0_GROUPOFFSET 0x20
-#define MCDE_EXTSRC0A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC0A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC0A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC0A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC0A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC0A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC1A0 0x00000220
-#define MCDE_EXTSRC1A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC1A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC1A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC1A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC1A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC1A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC2A0 0x00000240
-#define MCDE_EXTSRC2A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC2A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC2A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC2A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC2A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC2A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC3A0 0x00000260
-#define MCDE_EXTSRC3A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC3A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC3A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC3A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC3A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC3A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC4A0 0x00000280
-#define MCDE_EXTSRC4A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC4A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC4A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC4A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC4A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC4A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC5A0 0x000002A0
-#define MCDE_EXTSRC5A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC5A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC5A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC5A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC5A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC5A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC6A0 0x000002C0
-#define MCDE_EXTSRC6A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC6A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC6A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC6A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC6A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC6A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC7A0 0x000002E0
-#define MCDE_EXTSRC7A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC7A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC7A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC7A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC7A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC7A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC8A0 0x00000300
-#define MCDE_EXTSRC8A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC8A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC8A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC8A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC8A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC8A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC9A0 0x00000320
-#define MCDE_EXTSRC9A0_BASEADDRESS0_SHIFT 0
-#define MCDE_EXTSRC9A0_BASEADDRESS0_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC9A0_BASEADDRESS0_SHIFT 3
+#define MCDE_EXTSRC9A0_BASEADDRESS0_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC9A0_BASEADDRESS0(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC9A0, BASEADDRESS0, __x)
 #define MCDE_EXTSRC0A1 0x00000204
 #define MCDE_EXTSRC0A1_GROUPOFFSET 0x20
-#define MCDE_EXTSRC0A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC0A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC0A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC0A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC0A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC0A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC1A1 0x00000224
-#define MCDE_EXTSRC1A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC1A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC1A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC1A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC1A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC1A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC2A1 0x00000244
-#define MCDE_EXTSRC2A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC2A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC2A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC2A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC2A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC2A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC3A1 0x00000264
-#define MCDE_EXTSRC3A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC3A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC3A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC3A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC3A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC3A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC4A1 0x00000284
-#define MCDE_EXTSRC4A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC4A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC4A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC4A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC4A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC4A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC5A1 0x000002A4
-#define MCDE_EXTSRC5A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC5A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC5A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC5A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC5A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC5A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC6A1 0x000002C4
-#define MCDE_EXTSRC6A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC6A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC6A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC6A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC6A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC6A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC7A1 0x000002E4
-#define MCDE_EXTSRC7A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC7A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC7A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC7A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC7A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC7A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC8A1 0x00000304
-#define MCDE_EXTSRC8A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC8A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC8A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC8A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC8A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC8A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC9A1 0x00000324
-#define MCDE_EXTSRC9A1_BASEADDRESS1_SHIFT 0
-#define MCDE_EXTSRC9A1_BASEADDRESS1_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC9A1_BASEADDRESS1_SHIFT 3
+#define MCDE_EXTSRC9A1_BASEADDRESS1_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC9A1_BASEADDRESS1(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC9A1, BASEADDRESS1, __x)
 #define MCDE_EXTSRC6A2 0x000002C8
-#define MCDE_EXTSRC6A2_BASEADDRESS2_SHIFT 0
-#define MCDE_EXTSRC6A2_BASEADDRESS2_MASK 0xFFFFFFFF
+#define MCDE_EXTSRC6A2_BASEADDRESS2_SHIFT 3
+#define MCDE_EXTSRC6A2_BASEADDRESS2_MASK 0xFFFFFFF8
 #define MCDE_EXTSRC6A2_BASEADDRESS2(__x) \
 	MCDE_VAL2REG(MCDE_EXTSRC6A2, BASEADDRESS2, __x)
 #define MCDE_EXTSRC0CONF 0x0000020C
@@ -1554,14 +1554,46 @@
 	MCDE_VAL2REG(MCDE_OVL0CR, STBPRIO, __x)
 #define MCDE_OVL0CR_BURSTSIZE_SHIFT 20
 #define MCDE_OVL0CR_BURSTSIZE_MASK 0x00F00000
+#define MCDE_OVL0CR_BURSTSIZE_1W 0
+#define MCDE_OVL0CR_BURSTSIZE_2W 1
+#define MCDE_OVL0CR_BURSTSIZE_4W 2
+#define MCDE_OVL0CR_BURSTSIZE_8W 3
+#define MCDE_OVL0CR_BURSTSIZE_16W 4
+#define MCDE_OVL0CR_BURSTSIZE_HW_1W 8
+#define MCDE_OVL0CR_BURSTSIZE_HW_2W 9
+#define MCDE_OVL0CR_BURSTSIZE_HW_4W 10
+#define MCDE_OVL0CR_BURSTSIZE_HW_8W 11
+#define MCDE_OVL0CR_BURSTSIZE_HW_16W 12
+#define MCDE_OVL0CR_BURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL0CR, BURSTSIZE, MCDE_OVL0CR_BURSTSIZE_##__x)
 #define MCDE_OVL0CR_BURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL0CR, BURSTSIZE, __x)
 #define MCDE_OVL0CR_MAXOUTSTANDING_SHIFT 24
 #define MCDE_OVL0CR_MAXOUTSTANDING_MASK 0x0F000000
+#define MCDE_OVL0CR_MAXOUTSTANDING_1_REQ 0
+#define MCDE_OVL0CR_MAXOUTSTANDING_2_REQ 1
+#define MCDE_OVL0CR_MAXOUTSTANDING_4_REQ 2
+#define MCDE_OVL0CR_MAXOUTSTANDING_8_REQ 3
+#define MCDE_OVL0CR_MAXOUTSTANDING_16_REQ 4
+#define MCDE_OVL0CR_MAXOUTSTANDING_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL0CR, MAXOUTSTANDING, \
+	MCDE_OVL0CR_MAXOUTSTANDING_##__x)
 #define MCDE_OVL0CR_MAXOUTSTANDING(__x) \
 	MCDE_VAL2REG(MCDE_OVL0CR, MAXOUTSTANDING, __x)
 #define MCDE_OVL0CR_ROTBURSTSIZE_SHIFT 28
 #define MCDE_OVL0CR_ROTBURSTSIZE_MASK 0xF0000000
+#define MCDE_OVL0CR_ROTBURSTSIZE_1W 0
+#define MCDE_OVL0CR_ROTBURSTSIZE_2W 1
+#define MCDE_OVL0CR_ROTBURSTSIZE_4W 2
+#define MCDE_OVL0CR_ROTBURSTSIZE_8W 3
+#define MCDE_OVL0CR_ROTBURSTSIZE_16W 4
+#define MCDE_OVL0CR_ROTBURSTSIZE_HW_1W 8
+#define MCDE_OVL0CR_ROTBURSTSIZE_HW_2W 9
+#define MCDE_OVL0CR_ROTBURSTSIZE_HW_4W 10
+#define MCDE_OVL0CR_ROTBURSTSIZE_HW_8W 11
+#define MCDE_OVL0CR_ROTBURSTSIZE_HW_16W 12
+#define MCDE_OVL0CR_ROTBURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL0CR, ROTBURSTSIZE, MCDE_OVL0CR_ROTBURSTSIZE_##__x)
 #define MCDE_OVL0CR_ROTBURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL0CR, ROTBURSTSIZE, __x)
 #define MCDE_OVL1CR 0x00000420
@@ -1608,14 +1640,46 @@
 	MCDE_VAL2REG(MCDE_OVL1CR, STBPRIO, __x)
 #define MCDE_OVL1CR_BURSTSIZE_SHIFT 20
 #define MCDE_OVL1CR_BURSTSIZE_MASK 0x00F00000
+#define MCDE_OVL1CR_BURSTSIZE_1W 0
+#define MCDE_OVL1CR_BURSTSIZE_2W 1
+#define MCDE_OVL1CR_BURSTSIZE_4W 2
+#define MCDE_OVL1CR_BURSTSIZE_8W 3
+#define MCDE_OVL1CR_BURSTSIZE_16W 4
+#define MCDE_OVL1CR_BURSTSIZE_HW_1W 8
+#define MCDE_OVL1CR_BURSTSIZE_HW_2W 9
+#define MCDE_OVL1CR_BURSTSIZE_HW_4W 10
+#define MCDE_OVL1CR_BURSTSIZE_HW_8W 11
+#define MCDE_OVL1CR_BURSTSIZE_HW_16W 12
+#define MCDE_OVL1CR_BURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL1CR, BURSTSIZE, MCDE_OVL1CR_BURSTSIZE_##__x)
 #define MCDE_OVL1CR_BURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL1CR, BURSTSIZE, __x)
 #define MCDE_OVL1CR_MAXOUTSTANDING_SHIFT 24
 #define MCDE_OVL1CR_MAXOUTSTANDING_MASK 0x0F000000
+#define MCDE_OVL1CR_MAXOUTSTANDING_1_REQ 0
+#define MCDE_OVL1CR_MAXOUTSTANDING_2_REQ 1
+#define MCDE_OVL1CR_MAXOUTSTANDING_4_REQ 2
+#define MCDE_OVL1CR_MAXOUTSTANDING_8_REQ 3
+#define MCDE_OVL1CR_MAXOUTSTANDING_16_REQ 4
+#define MCDE_OVL1CR_MAXOUTSTANDING_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL1CR, MAXOUTSTANDING, \
+	MCDE_OVL1CR_MAXOUTSTANDING_##__x)
 #define MCDE_OVL1CR_MAXOUTSTANDING(__x) \
 	MCDE_VAL2REG(MCDE_OVL1CR, MAXOUTSTANDING, __x)
 #define MCDE_OVL1CR_ROTBURSTSIZE_SHIFT 28
 #define MCDE_OVL1CR_ROTBURSTSIZE_MASK 0xF0000000
+#define MCDE_OVL1CR_ROTBURSTSIZE_1W 0
+#define MCDE_OVL1CR_ROTBURSTSIZE_2W 1
+#define MCDE_OVL1CR_ROTBURSTSIZE_4W 2
+#define MCDE_OVL1CR_ROTBURSTSIZE_8W 3
+#define MCDE_OVL1CR_ROTBURSTSIZE_16W 4
+#define MCDE_OVL1CR_ROTBURSTSIZE_HW_1W 8
+#define MCDE_OVL1CR_ROTBURSTSIZE_HW_2W 9
+#define MCDE_OVL1CR_ROTBURSTSIZE_HW_4W 10
+#define MCDE_OVL1CR_ROTBURSTSIZE_HW_8W 11
+#define MCDE_OVL1CR_ROTBURSTSIZE_HW_16W 12
+#define MCDE_OVL1CR_ROTBURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL1CR, ROTBURSTSIZE, MCDE_OVL1CR_ROTBURSTSIZE_##__x)
 #define MCDE_OVL1CR_ROTBURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL1CR, ROTBURSTSIZE, __x)
 #define MCDE_OVL2CR 0x00000440
@@ -1662,14 +1726,46 @@
 	MCDE_VAL2REG(MCDE_OVL2CR, STBPRIO, __x)
 #define MCDE_OVL2CR_BURSTSIZE_SHIFT 20
 #define MCDE_OVL2CR_BURSTSIZE_MASK 0x00F00000
+#define MCDE_OVL2CR_BURSTSIZE_1W 0
+#define MCDE_OVL2CR_BURSTSIZE_2W 1
+#define MCDE_OVL2CR_BURSTSIZE_4W 2
+#define MCDE_OVL2CR_BURSTSIZE_8W 3
+#define MCDE_OVL2CR_BURSTSIZE_16W 4
+#define MCDE_OVL2CR_BURSTSIZE_HW_1W 8
+#define MCDE_OVL2CR_BURSTSIZE_HW_2W 9
+#define MCDE_OVL2CR_BURSTSIZE_HW_4W 10
+#define MCDE_OVL2CR_BURSTSIZE_HW_8W 11
+#define MCDE_OVL2CR_BURSTSIZE_HW_16W 12
+#define MCDE_OVL2CR_BURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL2CR, BURSTSIZE, MCDE_OVL2CR_BURSTSIZE_##__x)
 #define MCDE_OVL2CR_BURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL2CR, BURSTSIZE, __x)
 #define MCDE_OVL2CR_MAXOUTSTANDING_SHIFT 24
 #define MCDE_OVL2CR_MAXOUTSTANDING_MASK 0x0F000000
+#define MCDE_OVL2CR_MAXOUTSTANDING_1_REQ 0
+#define MCDE_OVL2CR_MAXOUTSTANDING_2_REQ 1
+#define MCDE_OVL2CR_MAXOUTSTANDING_4_REQ 2
+#define MCDE_OVL2CR_MAXOUTSTANDING_8_REQ 3
+#define MCDE_OVL2CR_MAXOUTSTANDING_16_REQ 4
+#define MCDE_OVL2CR_MAXOUTSTANDING_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL2CR, MAXOUTSTANDING, \
+	MCDE_OVL2CR_MAXOUTSTANDING_##__x)
 #define MCDE_OVL2CR_MAXOUTSTANDING(__x) \
 	MCDE_VAL2REG(MCDE_OVL2CR, MAXOUTSTANDING, __x)
 #define MCDE_OVL2CR_ROTBURSTSIZE_SHIFT 28
 #define MCDE_OVL2CR_ROTBURSTSIZE_MASK 0xF0000000
+#define MCDE_OVL2CR_ROTBURSTSIZE_1W 0
+#define MCDE_OVL2CR_ROTBURSTSIZE_2W 1
+#define MCDE_OVL2CR_ROTBURSTSIZE_4W 2
+#define MCDE_OVL2CR_ROTBURSTSIZE_8W 3
+#define MCDE_OVL2CR_ROTBURSTSIZE_16W 4
+#define MCDE_OVL2CR_ROTBURSTSIZE_HW_1W 8
+#define MCDE_OVL2CR_ROTBURSTSIZE_HW_2W 9
+#define MCDE_OVL2CR_ROTBURSTSIZE_HW_4W 10
+#define MCDE_OVL2CR_ROTBURSTSIZE_HW_8W 11
+#define MCDE_OVL2CR_ROTBURSTSIZE_HW_16W 12
+#define MCDE_OVL2CR_ROTBURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL2CR, ROTBURSTSIZE, MCDE_OVL2CR_ROTBURSTSIZE_##__x)
 #define MCDE_OVL2CR_ROTBURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL2CR, ROTBURSTSIZE, __x)
 #define MCDE_OVL3CR 0x00000460
@@ -1716,14 +1812,46 @@
 	MCDE_VAL2REG(MCDE_OVL3CR, STBPRIO, __x)
 #define MCDE_OVL3CR_BURSTSIZE_SHIFT 20
 #define MCDE_OVL3CR_BURSTSIZE_MASK 0x00F00000
+#define MCDE_OVL3CR_BURSTSIZE_1W 0
+#define MCDE_OVL3CR_BURSTSIZE_2W 1
+#define MCDE_OVL3CR_BURSTSIZE_4W 2
+#define MCDE_OVL3CR_BURSTSIZE_8W 3
+#define MCDE_OVL3CR_BURSTSIZE_16W 4
+#define MCDE_OVL3CR_BURSTSIZE_HW_1W 8
+#define MCDE_OVL3CR_BURSTSIZE_HW_2W 9
+#define MCDE_OVL3CR_BURSTSIZE_HW_4W 10
+#define MCDE_OVL3CR_BURSTSIZE_HW_8W 11
+#define MCDE_OVL3CR_BURSTSIZE_HW_16W 12
+#define MCDE_OVL3CR_BURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL3CR, BURSTSIZE, MCDE_OVL3CR_BURSTSIZE_##__x)
 #define MCDE_OVL3CR_BURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL3CR, BURSTSIZE, __x)
 #define MCDE_OVL3CR_MAXOUTSTANDING_SHIFT 24
 #define MCDE_OVL3CR_MAXOUTSTANDING_MASK 0x0F000000
+#define MCDE_OVL3CR_MAXOUTSTANDING_1_REQ 0
+#define MCDE_OVL3CR_MAXOUTSTANDING_2_REQ 1
+#define MCDE_OVL3CR_MAXOUTSTANDING_4_REQ 2
+#define MCDE_OVL3CR_MAXOUTSTANDING_8_REQ 3
+#define MCDE_OVL3CR_MAXOUTSTANDING_16_REQ 4
+#define MCDE_OVL3CR_MAXOUTSTANDING_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL3CR, MAXOUTSTANDING, \
+	MCDE_OVL3CR_MAXOUTSTANDING_##__x)
 #define MCDE_OVL3CR_MAXOUTSTANDING(__x) \
 	MCDE_VAL2REG(MCDE_OVL3CR, MAXOUTSTANDING, __x)
 #define MCDE_OVL3CR_ROTBURSTSIZE_SHIFT 28
 #define MCDE_OVL3CR_ROTBURSTSIZE_MASK 0xF0000000
+#define MCDE_OVL3CR_ROTBURSTSIZE_1W 0
+#define MCDE_OVL3CR_ROTBURSTSIZE_2W 1
+#define MCDE_OVL3CR_ROTBURSTSIZE_4W 2
+#define MCDE_OVL3CR_ROTBURSTSIZE_8W 3
+#define MCDE_OVL3CR_ROTBURSTSIZE_16W 4
+#define MCDE_OVL3CR_ROTBURSTSIZE_HW_1W 8
+#define MCDE_OVL3CR_ROTBURSTSIZE_HW_2W 9
+#define MCDE_OVL3CR_ROTBURSTSIZE_HW_4W 10
+#define MCDE_OVL3CR_ROTBURSTSIZE_HW_8W 11
+#define MCDE_OVL3CR_ROTBURSTSIZE_HW_16W 12
+#define MCDE_OVL3CR_ROTBURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL3CR, ROTBURSTSIZE, MCDE_OVL3CR_ROTBURSTSIZE_##__x)
 #define MCDE_OVL3CR_ROTBURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL3CR, ROTBURSTSIZE, __x)
 #define MCDE_OVL4CR 0x00000480
@@ -1770,14 +1898,46 @@
 	MCDE_VAL2REG(MCDE_OVL4CR, STBPRIO, __x)
 #define MCDE_OVL4CR_BURSTSIZE_SHIFT 20
 #define MCDE_OVL4CR_BURSTSIZE_MASK 0x00F00000
+#define MCDE_OVL4CR_BURSTSIZE_1W 0
+#define MCDE_OVL4CR_BURSTSIZE_2W 1
+#define MCDE_OVL4CR_BURSTSIZE_4W 2
+#define MCDE_OVL4CR_BURSTSIZE_8W 3
+#define MCDE_OVL4CR_BURSTSIZE_16W 4
+#define MCDE_OVL4CR_BURSTSIZE_HW_1W 8
+#define MCDE_OVL4CR_BURSTSIZE_HW_2W 9
+#define MCDE_OVL4CR_BURSTSIZE_HW_4W 10
+#define MCDE_OVL4CR_BURSTSIZE_HW_8W 11
+#define MCDE_OVL4CR_BURSTSIZE_HW_16W 12
+#define MCDE_OVL4CR_BURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL4CR, BURSTSIZE, MCDE_OVL4CR_BURSTSIZE_##__x)
 #define MCDE_OVL4CR_BURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL4CR, BURSTSIZE, __x)
 #define MCDE_OVL4CR_MAXOUTSTANDING_SHIFT 24
 #define MCDE_OVL4CR_MAXOUTSTANDING_MASK 0x0F000000
+#define MCDE_OVL4CR_MAXOUTSTANDING_1_REQ 0
+#define MCDE_OVL4CR_MAXOUTSTANDING_2_REQ 1
+#define MCDE_OVL4CR_MAXOUTSTANDING_4_REQ 2
+#define MCDE_OVL4CR_MAXOUTSTANDING_8_REQ 3
+#define MCDE_OVL4CR_MAXOUTSTANDING_16_REQ 4
+#define MCDE_OVL4CR_MAXOUTSTANDING_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL4CR, MAXOUTSTANDING, \
+	MCDE_OVL4CR_MAXOUTSTANDING_##__x)
 #define MCDE_OVL4CR_MAXOUTSTANDING(__x) \
 	MCDE_VAL2REG(MCDE_OVL4CR, MAXOUTSTANDING, __x)
 #define MCDE_OVL4CR_ROTBURSTSIZE_SHIFT 28
 #define MCDE_OVL4CR_ROTBURSTSIZE_MASK 0xF0000000
+#define MCDE_OVL4CR_ROTBURSTSIZE_1W 0
+#define MCDE_OVL4CR_ROTBURSTSIZE_2W 1
+#define MCDE_OVL4CR_ROTBURSTSIZE_4W 2
+#define MCDE_OVL4CR_ROTBURSTSIZE_8W 3
+#define MCDE_OVL4CR_ROTBURSTSIZE_16W 4
+#define MCDE_OVL4CR_ROTBURSTSIZE_HW_1W 8
+#define MCDE_OVL4CR_ROTBURSTSIZE_HW_2W 9
+#define MCDE_OVL4CR_ROTBURSTSIZE_HW_4W 10
+#define MCDE_OVL4CR_ROTBURSTSIZE_HW_8W 11
+#define MCDE_OVL4CR_ROTBURSTSIZE_HW_16W 12
+#define MCDE_OVL4CR_ROTBURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL4CR, ROTBURSTSIZE, MCDE_OVL4CR_ROTBURSTSIZE_##__x)
 #define MCDE_OVL4CR_ROTBURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL4CR, ROTBURSTSIZE, __x)
 #define MCDE_OVL5CR 0x000004A0
@@ -1824,14 +1984,46 @@
 	MCDE_VAL2REG(MCDE_OVL5CR, STBPRIO, __x)
 #define MCDE_OVL5CR_BURSTSIZE_SHIFT 20
 #define MCDE_OVL5CR_BURSTSIZE_MASK 0x00F00000
+#define MCDE_OVL5CR_BURSTSIZE_1W 0
+#define MCDE_OVL5CR_BURSTSIZE_2W 1
+#define MCDE_OVL5CR_BURSTSIZE_4W 2
+#define MCDE_OVL5CR_BURSTSIZE_8W 3
+#define MCDE_OVL5CR_BURSTSIZE_16W 4
+#define MCDE_OVL5CR_BURSTSIZE_HW_1W 8
+#define MCDE_OVL5CR_BURSTSIZE_HW_2W 9
+#define MCDE_OVL5CR_BURSTSIZE_HW_4W 10
+#define MCDE_OVL5CR_BURSTSIZE_HW_8W 11
+#define MCDE_OVL5CR_BURSTSIZE_HW_16W 12
+#define MCDE_OVL5CR_BURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL5CR, BURSTSIZE, MCDE_OVL5CR_BURSTSIZE_##__x)
 #define MCDE_OVL5CR_BURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL5CR, BURSTSIZE, __x)
 #define MCDE_OVL5CR_MAXOUTSTANDING_SHIFT 24
 #define MCDE_OVL5CR_MAXOUTSTANDING_MASK 0x0F000000
+#define MCDE_OVL5CR_MAXOUTSTANDING_1_REQ 0
+#define MCDE_OVL5CR_MAXOUTSTANDING_2_REQ 1
+#define MCDE_OVL5CR_MAXOUTSTANDING_4_REQ 2
+#define MCDE_OVL5CR_MAXOUTSTANDING_8_REQ 3
+#define MCDE_OVL5CR_MAXOUTSTANDING_16_REQ 4
+#define MCDE_OVL5CR_MAXOUTSTANDING_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL5CR, MAXOUTSTANDING, \
+	MCDE_OVL5CR_MAXOUTSTANDING_##__x)
 #define MCDE_OVL5CR_MAXOUTSTANDING(__x) \
 	MCDE_VAL2REG(MCDE_OVL5CR, MAXOUTSTANDING, __x)
 #define MCDE_OVL5CR_ROTBURSTSIZE_SHIFT 28
 #define MCDE_OVL5CR_ROTBURSTSIZE_MASK 0xF0000000
+#define MCDE_OVL5CR_ROTBURSTSIZE_1W 0
+#define MCDE_OVL5CR_ROTBURSTSIZE_2W 1
+#define MCDE_OVL5CR_ROTBURSTSIZE_4W 2
+#define MCDE_OVL5CR_ROTBURSTSIZE_8W 3
+#define MCDE_OVL5CR_ROTBURSTSIZE_16W 4
+#define MCDE_OVL5CR_ROTBURSTSIZE_HW_1W 8
+#define MCDE_OVL5CR_ROTBURSTSIZE_HW_2W 9
+#define MCDE_OVL5CR_ROTBURSTSIZE_HW_4W 10
+#define MCDE_OVL5CR_ROTBURSTSIZE_HW_8W 11
+#define MCDE_OVL5CR_ROTBURSTSIZE_HW_16W 12
+#define MCDE_OVL5CR_ROTBURSTSIZE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_OVL5CR, ROTBURSTSIZE, MCDE_OVL5CR_ROTBURSTSIZE_##__x)
 #define MCDE_OVL5CR_ROTBURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_OVL5CR, ROTBURSTSIZE, __x)
 #define MCDE_OVL0CONF 0x00000404
@@ -2506,27 +2698,76 @@
 #define MCDE_CHNL3BCKGNDCOL_R_MASK 0x00FF0000
 #define MCDE_CHNL3BCKGNDCOL_R(__x) \
 	MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, R, __x)
-#define MCDE_CHNL0PRIO 0x00000614
-#define MCDE_CHNL0PRIO_GROUPOFFSET 0x20
-#define MCDE_CHNL0PRIO_CHNLPRIO_SHIFT 0
-#define MCDE_CHNL0PRIO_CHNLPRIO_MASK 0x0000000F
-#define MCDE_CHNL0PRIO_CHNLPRIO(__x) \
-	MCDE_VAL2REG(MCDE_CHNL0PRIO, CHNLPRIO, __x)
-#define MCDE_CHNL1PRIO 0x00000634
-#define MCDE_CHNL1PRIO_CHNLPRIO_SHIFT 0
-#define MCDE_CHNL1PRIO_CHNLPRIO_MASK 0x0000000F
-#define MCDE_CHNL1PRIO_CHNLPRIO(__x) \
-	MCDE_VAL2REG(MCDE_CHNL1PRIO, CHNLPRIO, __x)
-#define MCDE_CHNL2PRIO 0x00000654
-#define MCDE_CHNL2PRIO_CHNLPRIO_SHIFT 0
-#define MCDE_CHNL2PRIO_CHNLPRIO_MASK 0x0000000F
-#define MCDE_CHNL2PRIO_CHNLPRIO(__x) \
-	MCDE_VAL2REG(MCDE_CHNL2PRIO, CHNLPRIO, __x)
-#define MCDE_CHNL3PRIO 0x00000674
-#define MCDE_CHNL3PRIO_CHNLPRIO_SHIFT 0
-#define MCDE_CHNL3PRIO_CHNLPRIO_MASK 0x0000000F
-#define MCDE_CHNL3PRIO_CHNLPRIO(__x) \
-	MCDE_VAL2REG(MCDE_CHNL3PRIO, CHNLPRIO, __x)
+#define MCDE_CHNL0PRIO_V1 0x00000614
+#define MCDE_CHNL0PRIO_V1_GROUPOFFSET 0x20
+#define MCDE_CHNL0PRIO_V1_CHNLPRIO_SHIFT 0
+#define MCDE_CHNL0PRIO_V1_CHNLPRIO_MASK 0x0000000F
+#define MCDE_CHNL0PRIO_V1_CHNLPRIO(__x) \
+	MCDE_VAL2REG(MCDE_CHNL0PRIO_V1, CHNLPRIO, __x)
+#define MCDE_CHNL1PRIO_V1 0x00000634
+#define MCDE_CHNL1PRIO_V1_CHNLPRIO_SHIFT 0
+#define MCDE_CHNL1PRIO_V1_CHNLPRIO_MASK 0x0000000F
+#define MCDE_CHNL1PRIO_V1_CHNLPRIO(__x) \
+	MCDE_VAL2REG(MCDE_CHNL1PRIO_V1, CHNLPRIO, __x)
+#define MCDE_CHNL2PRIO_V1 0x00000654
+#define MCDE_CHNL2PRIO_V1_CHNLPRIO_SHIFT 0
+#define MCDE_CHNL2PRIO_V1_CHNLPRIO_MASK 0x0000000F
+#define MCDE_CHNL2PRIO_V1_CHNLPRIO(__x) \
+	MCDE_VAL2REG(MCDE_CHNL2PRIO_V1, CHNLPRIO, __x)
+#define MCDE_CHNL3PRIO_V1 0x00000674
+#define MCDE_CHNL3PRIO_V1_CHNLPRIO_SHIFT 0
+#define MCDE_CHNL3PRIO_V1_CHNLPRIO_MASK 0x0000000F
+#define MCDE_CHNL3PRIO_V1_CHNLPRIO(__x) \
+	MCDE_VAL2REG(MCDE_CHNL3PRIO_V1, CHNLPRIO, __x)
+#define MCDE_CHNL0MUXING_V2 0x00000614
+#define MCDE_CHNL0MUXING_V2_GROUPOFFSET 0x20
+#define MCDE_CHNL0MUXING_V2_FIFO_ID_SHIFT 0
+#define MCDE_CHNL0MUXING_V2_FIFO_ID_MASK 0x00000007
+#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_A 0
+#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_B 1
+#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_C0 2
+#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_C1 3
+#define MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CHNL0MUXING_V2, FIFO_ID, \
+	MCDE_CHNL0MUXING_V2_FIFO_ID_##__x)
+#define MCDE_CHNL0MUXING_V2_FIFO_ID(__x) \
+	MCDE_VAL2REG(MCDE_CHNL0MUXING_V2, FIFO_ID, __x)
+#define MCDE_CHNL1MUXING_V2 0x00000634
+#define MCDE_CHNL1MUXING_V2_FIFO_ID_SHIFT 0
+#define MCDE_CHNL1MUXING_V2_FIFO_ID_MASK 0x00000007
+#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_A 0
+#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_B 1
+#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_C0 2
+#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_C1 3
+#define MCDE_CHNL1MUXING_V2_FIFO_ID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CHNL1MUXING_V2, FIFO_ID, \
+	MCDE_CHNL1MUXING_V2_FIFO_ID_##__x)
+#define MCDE_CHNL1MUXING_V2_FIFO_ID(__x) \
+	MCDE_VAL2REG(MCDE_CHNL1MUXING_V2, FIFO_ID, __x)
+#define MCDE_CHNL2MUXING_V2 0x00000654
+#define MCDE_CHNL2MUXING_V2_FIFO_ID_SHIFT 0
+#define MCDE_CHNL2MUXING_V2_FIFO_ID_MASK 0x00000007
+#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_A 0
+#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_B 1
+#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_C0 2
+#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_C1 3
+#define MCDE_CHNL2MUXING_V2_FIFO_ID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CHNL2MUXING_V2, FIFO_ID, \
+	MCDE_CHNL2MUXING_V2_FIFO_ID_##__x)
+#define MCDE_CHNL2MUXING_V2_FIFO_ID(__x) \
+	MCDE_VAL2REG(MCDE_CHNL2MUXING_V2, FIFO_ID, __x)
+#define MCDE_CHNL3MUXING_V2 0x00000674
+#define MCDE_CHNL3MUXING_V2_FIFO_ID_SHIFT 0
+#define MCDE_CHNL3MUXING_V2_FIFO_ID_MASK 0x00000007
+#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_A 0
+#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_B 1
+#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_C0 2
+#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_C1 3
+#define MCDE_CHNL3MUXING_V2_FIFO_ID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CHNL3MUXING_V2, FIFO_ID, \
+	MCDE_CHNL3MUXING_V2_FIFO_ID_##__x)
+#define MCDE_CHNL3MUXING_V2_FIFO_ID(__x) \
+	MCDE_VAL2REG(MCDE_CHNL3MUXING_V2, FIFO_ID, __x)
 #define MCDE_CRA0 0x00000800
 #define MCDE_CRA0_GROUPOFFSET 0x200
 #define MCDE_CRA0_FLOEN_SHIFT 0
@@ -2611,21 +2852,22 @@
 #define MCDE_CRA0_ROTEN_MASK 0x01000000
 #define MCDE_CRA0_ROTEN(__x) \
 	MCDE_VAL2REG(MCDE_CRA0, ROTEN, __x)
-#define MCDE_CRA0_ROTBURSTSIZE_SHIFT 25
-#define MCDE_CRA0_ROTBURSTSIZE_MASK 0x0E000000
-#define MCDE_CRA0_ROTBURSTSIZE_1W 0
-#define MCDE_CRA0_ROTBURSTSIZE_2W 1
-#define MCDE_CRA0_ROTBURSTSIZE_4W 2
-#define MCDE_CRA0_ROTBURSTSIZE_8W 3
-#define MCDE_CRA0_ROTBURSTSIZE_16W 4
-#define MCDE_CRA0_ROTBURSTSIZE_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE, MCDE_CRA0_ROTBURSTSIZE_##__x)
-#define MCDE_CRA0_ROTBURSTSIZE(__x) \
-	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE, __x)
-#define MCDE_CRA0_ROTBURSTSIZE_HW_SHIFT 28
-#define MCDE_CRA0_ROTBURSTSIZE_HW_MASK 0x10000000
-#define MCDE_CRA0_ROTBURSTSIZE_HW(__x) \
-	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_HW, __x)
+#define MCDE_CRA0_ROTBURSTSIZE_V1_SHIFT 25
+#define MCDE_CRA0_ROTBURSTSIZE_V1_MASK 0x0E000000
+#define MCDE_CRA0_ROTBURSTSIZE_V1_1W 0
+#define MCDE_CRA0_ROTBURSTSIZE_V1_2W 1
+#define MCDE_CRA0_ROTBURSTSIZE_V1_4W 2
+#define MCDE_CRA0_ROTBURSTSIZE_V1_8W 3
+#define MCDE_CRA0_ROTBURSTSIZE_V1_16W 4
+#define MCDE_CRA0_ROTBURSTSIZE_V1_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_V1, \
+	MCDE_CRA0_ROTBURSTSIZE_V1_##__x)
+#define MCDE_CRA0_ROTBURSTSIZE_V1(__x) \
+	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_V1, __x)
+#define MCDE_CRA0_ROTBURSTSIZE_HW_V1_SHIFT 28
+#define MCDE_CRA0_ROTBURSTSIZE_HW_V1_MASK 0x10000000
+#define MCDE_CRA0_ROTBURSTSIZE_HW_V1(__x) \
+	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_HW_V1, __x)
 #define MCDE_CRB0 0x00000A00
 #define MCDE_CRB0_FLOEN_SHIFT 0
 #define MCDE_CRB0_FLOEN_MASK 0x00000001
@@ -2709,21 +2951,22 @@
 #define MCDE_CRB0_ROTEN_MASK 0x01000000
 #define MCDE_CRB0_ROTEN(__x) \
 	MCDE_VAL2REG(MCDE_CRB0, ROTEN, __x)
-#define MCDE_CRB0_ROTBURSTSIZE_SHIFT 25
-#define MCDE_CRB0_ROTBURSTSIZE_MASK 0x0E000000
-#define MCDE_CRB0_ROTBURSTSIZE_1W 0
-#define MCDE_CRB0_ROTBURSTSIZE_2W 1
-#define MCDE_CRB0_ROTBURSTSIZE_4W 2
-#define MCDE_CRB0_ROTBURSTSIZE_8W 3
-#define MCDE_CRB0_ROTBURSTSIZE_16W 4
-#define MCDE_CRB0_ROTBURSTSIZE_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE, MCDE_CRB0_ROTBURSTSIZE_##__x)
-#define MCDE_CRB0_ROTBURSTSIZE(__x) \
-	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE, __x)
-#define MCDE_CRB0_ROTBURSTSIZE_HW_SHIFT 28
-#define MCDE_CRB0_ROTBURSTSIZE_HW_MASK 0x10000000
-#define MCDE_CRB0_ROTBURSTSIZE_HW(__x) \
-	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_HW, __x)
+#define MCDE_CRB0_ROTBURSTSIZE_V1_SHIFT 25
+#define MCDE_CRB0_ROTBURSTSIZE_V1_MASK 0x0E000000
+#define MCDE_CRB0_ROTBURSTSIZE_V1_1W 0
+#define MCDE_CRB0_ROTBURSTSIZE_V1_2W 1
+#define MCDE_CRB0_ROTBURSTSIZE_V1_4W 2
+#define MCDE_CRB0_ROTBURSTSIZE_V1_8W 3
+#define MCDE_CRB0_ROTBURSTSIZE_V1_16W 4
+#define MCDE_CRB0_ROTBURSTSIZE_V1_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_V1, \
+	MCDE_CRB0_ROTBURSTSIZE_V1_##__x)
+#define MCDE_CRB0_ROTBURSTSIZE_V1(__x) \
+	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_V1, __x)
+#define MCDE_CRB0_ROTBURSTSIZE_HW_V1_SHIFT 28
+#define MCDE_CRB0_ROTBURSTSIZE_HW_V1_MASK 0x10000000
+#define MCDE_CRB0_ROTBURSTSIZE_HW_V1(__x) \
+	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_HW_V1, __x)
 #define MCDE_CRA1 0x00000804
 #define MCDE_CRA1_GROUPOFFSET 0x200
 #define MCDE_CRA1_PCD_SHIFT 0
@@ -2784,10 +3027,10 @@
 	MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, MCDE_CRA1_CLKTYPE_##__x)
 #define MCDE_CRA1_CLKTYPE(__x) \
 	MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, __x)
-#define MCDE_CRA1_TEFFECTEN_SHIFT 31
-#define MCDE_CRA1_TEFFECTEN_MASK 0x80000000
-#define MCDE_CRA1_TEFFECTEN(__x) \
-	MCDE_VAL2REG(MCDE_CRA1, TEFFECTEN, __x)
+#define MCDE_CRA1_TEFFECTEN_V1_SHIFT 31
+#define MCDE_CRA1_TEFFECTEN_V1_MASK 0x80000000
+#define MCDE_CRA1_TEFFECTEN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CRA1, TEFFECTEN_V1, __x)
 #define MCDE_CRB1 0x00000A04
 #define MCDE_CRB1_PCD_SHIFT 0
 #define MCDE_CRB1_PCD_MASK 0x000003FF
@@ -2847,10 +3090,10 @@
 	MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, MCDE_CRB1_CLKTYPE_##__x)
 #define MCDE_CRB1_CLKTYPE(__x) \
 	MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, __x)
-#define MCDE_CRB1_TEFFECTEN_SHIFT 31
-#define MCDE_CRB1_TEFFECTEN_MASK 0x80000000
-#define MCDE_CRB1_TEFFECTEN(__x) \
-	MCDE_VAL2REG(MCDE_CRB1, TEFFECTEN, __x)
+#define MCDE_CRB1_TEFFECTEN_V1_SHIFT 31
+#define MCDE_CRB1_TEFFECTEN_V1_MASK 0x80000000
+#define MCDE_CRB1_TEFFECTEN_V1(__x) \
+	MCDE_VAL2REG(MCDE_CRB1, TEFFECTEN_V1, __x)
 #define MCDE_COLKEYA 0x00000808
 #define MCDE_COLKEYA_GROUPOFFSET 0x200
 #define MCDE_COLKEYA_KEYB_SHIFT 0
@@ -3035,111 +3278,76 @@
 #define MCDE_RGBCONV6B_OFF_GREEN_MASK 0x07FF0000
 #define MCDE_RGBCONV6B_OFF_GREEN(__x) \
 	MCDE_VAL2REG(MCDE_RGBCONV6B, OFF_GREEN, __x)
-#define MCDE_FFCOEFA0 0x00000828
-#define MCDE_FFCOEFA0_GROUPOFFSET 0x200
-#define MCDE_FFCOEFA0_COEFF0_N1_SHIFT 0
-#define MCDE_FFCOEFA0_COEFF0_N1_MASK 0x000000FF
-#define MCDE_FFCOEFA0_COEFF0_N1(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N1, __x)
-#define MCDE_FFCOEFA0_COEFF0_N2_SHIFT 8
-#define MCDE_FFCOEFA0_COEFF0_N2_MASK 0x0000FF00
-#define MCDE_FFCOEFA0_COEFF0_N2(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N2, __x)
-#define MCDE_FFCOEFA0_COEFF0_N3_SHIFT 16
-#define MCDE_FFCOEFA0_COEFF0_N3_MASK 0x00FF0000
-#define MCDE_FFCOEFA0_COEFF0_N3(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N3, __x)
-#define MCDE_FFCOEFA0_T0_SHIFT 24
-#define MCDE_FFCOEFA0_T0_MASK 0x0F000000
-#define MCDE_FFCOEFA0_T0(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA0, T0, __x)
-#define MCDE_FFCOEFB0 0x00000A28
-#define MCDE_FFCOEFB0_COEFF0_N1_SHIFT 0
-#define MCDE_FFCOEFB0_COEFF0_N1_MASK 0x000000FF
-#define MCDE_FFCOEFB0_COEFF0_N1(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N1, __x)
-#define MCDE_FFCOEFB0_COEFF0_N2_SHIFT 8
-#define MCDE_FFCOEFB0_COEFF0_N2_MASK 0x0000FF00
-#define MCDE_FFCOEFB0_COEFF0_N2(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N2, __x)
-#define MCDE_FFCOEFB0_COEFF0_N3_SHIFT 16
-#define MCDE_FFCOEFB0_COEFF0_N3_MASK 0x00FF0000
-#define MCDE_FFCOEFB0_COEFF0_N3(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N3, __x)
-#define MCDE_FFCOEFB0_T0_SHIFT 24
-#define MCDE_FFCOEFB0_T0_MASK 0x0F000000
-#define MCDE_FFCOEFB0_T0(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB0, T0, __x)
-#define MCDE_FFCOEFA1 0x0000082C
-#define MCDE_FFCOEFA1_GROUPOFFSET 0x200
-#define MCDE_FFCOEFA1_COEFF1_N1_SHIFT 0
-#define MCDE_FFCOEFA1_COEFF1_N1_MASK 0x000000FF
-#define MCDE_FFCOEFA1_COEFF1_N1(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N1, __x)
-#define MCDE_FFCOEFA1_COEFF1_N2_SHIFT 8
-#define MCDE_FFCOEFA1_COEFF1_N2_MASK 0x0000FF00
-#define MCDE_FFCOEFA1_COEFF1_N2(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N2, __x)
-#define MCDE_FFCOEFA1_COEFF1_N3_SHIFT 16
-#define MCDE_FFCOEFA1_COEFF1_N3_MASK 0x00FF0000
-#define MCDE_FFCOEFA1_COEFF1_N3(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N3, __x)
-#define MCDE_FFCOEFA1_T1_SHIFT 24
-#define MCDE_FFCOEFA1_T1_MASK 0x0F000000
-#define MCDE_FFCOEFA1_T1(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA1, T1, __x)
-#define MCDE_FFCOEFB1 0x00000A2C
-#define MCDE_FFCOEFB1_COEFF1_N1_SHIFT 0
-#define MCDE_FFCOEFB1_COEFF1_N1_MASK 0x000000FF
-#define MCDE_FFCOEFB1_COEFF1_N1(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N1, __x)
-#define MCDE_FFCOEFB1_COEFF1_N2_SHIFT 8
-#define MCDE_FFCOEFB1_COEFF1_N2_MASK 0x0000FF00
-#define MCDE_FFCOEFB1_COEFF1_N2(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N2, __x)
-#define MCDE_FFCOEFB1_COEFF1_N3_SHIFT 16
-#define MCDE_FFCOEFB1_COEFF1_N3_MASK 0x00FF0000
-#define MCDE_FFCOEFB1_COEFF1_N3(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N3, __x)
-#define MCDE_FFCOEFB1_T1_SHIFT 24
-#define MCDE_FFCOEFB1_T1_MASK 0x0F000000
-#define MCDE_FFCOEFB1_T1(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB1, T1, __x)
-#define MCDE_FFCOEFA2 0x00000830
-#define MCDE_FFCOEFA2_GROUPOFFSET 0x200
-#define MCDE_FFCOEFA2_COEFF2_N1_SHIFT 0
-#define MCDE_FFCOEFA2_COEFF2_N1_MASK 0x000000FF
-#define MCDE_FFCOEFA2_COEFF2_N1(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N1, __x)
-#define MCDE_FFCOEFA2_COEFF2_N2_SHIFT 8
-#define MCDE_FFCOEFA2_COEFF2_N2_MASK 0x0000FF00
-#define MCDE_FFCOEFA2_COEFF2_N2(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N2, __x)
-#define MCDE_FFCOEFA2_COEFF2_N3_SHIFT 16
-#define MCDE_FFCOEFA2_COEFF2_N3_MASK 0x00FF0000
-#define MCDE_FFCOEFA2_COEFF2_N3(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N3, __x)
-#define MCDE_FFCOEFA2_T2_SHIFT 24
-#define MCDE_FFCOEFA2_T2_MASK 0x0F000000
-#define MCDE_FFCOEFA2_T2(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFA2, T2, __x)
-#define MCDE_FFCOEFB2 0x00000A30
-#define MCDE_FFCOEFB2_COEFF2_N1_SHIFT 0
-#define MCDE_FFCOEFB2_COEFF2_N1_MASK 0x000000FF
-#define MCDE_FFCOEFB2_COEFF2_N1(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N1, __x)
-#define MCDE_FFCOEFB2_COEFF2_N2_SHIFT 8
-#define MCDE_FFCOEFB2_COEFF2_N2_MASK 0x0000FF00
-#define MCDE_FFCOEFB2_COEFF2_N2(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N2, __x)
-#define MCDE_FFCOEFB2_COEFF2_N3_SHIFT 16
-#define MCDE_FFCOEFB2_COEFF2_N3_MASK 0x00FF0000
-#define MCDE_FFCOEFB2_COEFF2_N3(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N3, __x)
-#define MCDE_FFCOEFB2_T2_SHIFT 24
-#define MCDE_FFCOEFB2_T2_MASK 0x0F000000
-#define MCDE_FFCOEFB2_T2(__x) \
-	MCDE_VAL2REG(MCDE_FFCOEFB2, T2, __x)
+#define MCDE_FFCOEF0 0x00000828
+#define MCDE_FFCOEF0_COEFF0_N1_SHIFT 0
+#define MCDE_FFCOEF0_COEFF0_N1_MASK 0x000000FF
+#define MCDE_FFCOEF0_COEFF0_N1(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF0, COEFF0_N1, __x)
+#define MCDE_FFCOEF0_COEFF0_N2_SHIFT 8
+#define MCDE_FFCOEF0_COEFF0_N2_MASK 0x0000FF00
+#define MCDE_FFCOEF0_COEFF0_N2(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF0, COEFF0_N2, __x)
+#define MCDE_FFCOEF0_COEFF0_N3_SHIFT 16
+#define MCDE_FFCOEF0_COEFF0_N3_MASK 0x00FF0000
+#define MCDE_FFCOEF0_COEFF0_N3(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF0, COEFF0_N3, __x)
+#define MCDE_FFCOEF0_T0_SHIFT 24
+#define MCDE_FFCOEF0_T0_MASK 0x0F000000
+#define MCDE_FFCOEF0_T0(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF0, T0, __x)
+#define MCDE_FFCOEF1 0x0000082C
+#define MCDE_FFCOEF1_COEFF1_N1_SHIFT 0
+#define MCDE_FFCOEF1_COEFF1_N1_MASK 0x000000FF
+#define MCDE_FFCOEF1_COEFF1_N1(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF1, COEFF1_N1, __x)
+#define MCDE_FFCOEF1_COEFF1_N2_SHIFT 8
+#define MCDE_FFCOEF1_COEFF1_N2_MASK 0x0000FF00
+#define MCDE_FFCOEF1_COEFF1_N2(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF1, COEFF1_N2, __x)
+#define MCDE_FFCOEF1_COEFF1_N3_SHIFT 16
+#define MCDE_FFCOEF1_COEFF1_N3_MASK 0x00FF0000
+#define MCDE_FFCOEF1_COEFF1_N3(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF1, COEFF1_N3, __x)
+#define MCDE_FFCOEF1_T1_SHIFT 24
+#define MCDE_FFCOEF1_T1_MASK 0x0F000000
+#define MCDE_FFCOEF1_T1(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF1, T1, __x)
+#define MCDE_FFCOEF2 0x00000830
+#define MCDE_FFCOEF2_COEFF2_N1_SHIFT 0
+#define MCDE_FFCOEF2_COEFF2_N1_MASK 0x000000FF
+#define MCDE_FFCOEF2_COEFF2_N1(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF2, COEFF2_N1, __x)
+#define MCDE_FFCOEF2_COEFF2_N2_SHIFT 8
+#define MCDE_FFCOEF2_COEFF2_N2_MASK 0x0000FF00
+#define MCDE_FFCOEF2_COEFF2_N2(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF2, COEFF2_N2, __x)
+#define MCDE_FFCOEF2_COEFF2_N3_SHIFT 16
+#define MCDE_FFCOEF2_COEFF2_N3_MASK 0x00FF0000
+#define MCDE_FFCOEF2_COEFF2_N3(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF2, COEFF2_N3, __x)
+#define MCDE_FFCOEF2_T2_SHIFT 24
+#define MCDE_FFCOEF2_T2_MASK 0x0F000000
+#define MCDE_FFCOEF2_T2(__x) \
+	MCDE_VAL2REG(MCDE_FFCOEF2, T2, __x)
+#define MCDE_MCDE_WDATAA_V2 0x00000834
+#define MCDE_MCDE_WDATAA_V2_GROUPOFFSET 0x200
+#define MCDE_MCDE_WDATAA_V2_DC_SHIFT 24
+#define MCDE_MCDE_WDATAA_V2_DC_MASK 0x01000000
+#define MCDE_MCDE_WDATAA_V2_DC(__x) \
+	MCDE_VAL2REG(MCDE_MCDE_WDATAA_V2, DC, __x)
+#define MCDE_MCDE_WDATAA_V2_DATAVALUE_SHIFT 0
+#define MCDE_MCDE_WDATAA_V2_DATAVALUE_MASK 0x00FFFFFF
+#define MCDE_MCDE_WDATAA_V2_DATAVALUE(__x) \
+	MCDE_VAL2REG(MCDE_MCDE_WDATAA_V2, DATAVALUE, __x)
+#define MCDE_MCDE_WDATAB_V2 0x00000A34
+#define MCDE_MCDE_WDATAB_V2_DC_SHIFT 24
+#define MCDE_MCDE_WDATAB_V2_DC_MASK 0x01000000
+#define MCDE_MCDE_WDATAB_V2_DC(__x) \
+	MCDE_VAL2REG(MCDE_MCDE_WDATAB_V2, DC, __x)
+#define MCDE_MCDE_WDATAB_V2_DATAVALUE_SHIFT 0
+#define MCDE_MCDE_WDATAB_V2_DATAVALUE_MASK 0x00FFFFFF
+#define MCDE_MCDE_WDATAB_V2_DATAVALUE(__x) \
+	MCDE_VAL2REG(MCDE_MCDE_WDATAB_V2, DATAVALUE, __x)
 #define MCDE_TVCRA 0x00000838
 #define MCDE_TVCRA_GROUPOFFSET 0x200
 #define MCDE_TVCRA_SEL_MOD_SHIFT 0
@@ -3181,6 +3389,10 @@
 #define MCDE_TVCRA_AVRGEN_MASK 0x00000100
 #define MCDE_TVCRA_AVRGEN(__x) \
 	MCDE_VAL2REG(MCDE_TVCRA, AVRGEN, __x)
+#define MCDE_TVCRA_CKINV_SHIFT 9
+#define MCDE_TVCRA_CKINV_MASK 0x00000200
+#define MCDE_TVCRA_CKINV(__x) \
+	MCDE_VAL2REG(MCDE_TVCRA, CKINV, __x)
 #define MCDE_TVCRB 0x00000A38
 #define MCDE_TVCRB_SEL_MOD_SHIFT 0
 #define MCDE_TVCRB_SEL_MOD_MASK 0x00000001
@@ -3221,6 +3433,10 @@
 #define MCDE_TVCRB_AVRGEN_MASK 0x00000100
 #define MCDE_TVCRB_AVRGEN(__x) \
 	MCDE_VAL2REG(MCDE_TVCRB, AVRGEN, __x)
+#define MCDE_TVCRB_CKINV_SHIFT 9
+#define MCDE_TVCRB_CKINV_MASK 0x00000200
+#define MCDE_TVCRB_CKINV(__x) \
+	MCDE_VAL2REG(MCDE_TVCRB, CKINV, __x)
 #define MCDE_TVBL1A 0x0000083C
 #define MCDE_TVBL1A_GROUPOFFSET 0x200
 #define MCDE_TVBL1A_BEL1_SHIFT 0
@@ -3354,153 +3570,8 @@
 #define MCDE_TVBLUB_TVBCR_MASK 0x00FF0000
 #define MCDE_TVBLUB_TVBCR(__x) \
 	MCDE_VAL2REG(MCDE_TVBLUB, TVBCR, __x)
-#define MCDE_LCDTIM0A 0x0000085C
-#define MCDE_LCDTIM0A_GROUPOFFSET 0x200
-#define MCDE_LCDTIM0A_PSDEL0_SHIFT 0
-#define MCDE_LCDTIM0A_PSDEL0_MASK 0x000000FF
-#define MCDE_LCDTIM0A_PSDEL0(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, PSDEL0, __x)
-#define MCDE_LCDTIM0A_PSDEL1_SHIFT 1
-#define MCDE_LCDTIM0A_PSDEL1_MASK 0x0000001E
-#define MCDE_LCDTIM0A_PSDEL1(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, PSDEL1, __x)
-#define MCDE_LCDTIM0A_PSLOADSEL_SHIFT 12
-#define MCDE_LCDTIM0A_PSLOADSEL_MASK 0x00003000
-#define MCDE_LCDTIM0A_PSLOADSEL_HBP 0
-#define MCDE_LCDTIM0A_PSLOADSEL_CLP 1
-#define MCDE_LCDTIM0A_PSLOADSEL_HFP 2
-#define MCDE_LCDTIM0A_PSLOADSEL_HSW 3
-#define MCDE_LCDTIM0A_PSLOADSEL_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, PSLOADSEL, MCDE_LCDTIM0A_PSLOADSEL_##__x)
-#define MCDE_LCDTIM0A_PSLOADSEL(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, PSLOADSEL, __x)
-#define MCDE_LCDTIM0A_PSTGEN_SHIFT 14
-#define MCDE_LCDTIM0A_PSTGEN_MASK 0x00004000
-#define MCDE_LCDTIM0A_PSTGEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, PSTGEN, __x)
-#define MCDE_LCDTIM0A_PSVAEN_SHIFT 15
-#define MCDE_LCDTIM0A_PSVAEN_MASK 0x00008000
-#define MCDE_LCDTIM0A_PSVAEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, PSVAEN, __x)
-#define MCDE_LCDTIM0A_REVDEL0_SHIFT 16
-#define MCDE_LCDTIM0A_REVDEL0_MASK 0x00FF0000
-#define MCDE_LCDTIM0A_REVDEL0(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, REVDEL0, __x)
-#define MCDE_LCDTIM0A_REVDEL1_SHIFT 24
-#define MCDE_LCDTIM0A_REVDEL1_MASK 0x0F000000
-#define MCDE_LCDTIM0A_REVDEL1(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, REVDEL1, __x)
-#define MCDE_LCDTIM0A_REVLOADSEL_SHIFT 28
-#define MCDE_LCDTIM0A_REVLOADSEL_MASK 0x30000000
-#define MCDE_LCDTIM0A_REVLOADSEL_HBP 0
-#define MCDE_LCDTIM0A_REVLOADSEL_CLP 1
-#define MCDE_LCDTIM0A_REVLOADSEL_HFP 2
-#define MCDE_LCDTIM0A_REVLOADSEL_HSW 3
-#define MCDE_LCDTIM0A_REVLOADSEL_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, REVLOADSEL, MCDE_LCDTIM0A_REVLOADSEL_##__x)
-#define MCDE_LCDTIM0A_REVLOADSEL(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, REVLOADSEL, __x)
-#define MCDE_LCDTIM0A_REVTGEN_SHIFT 30
-#define MCDE_LCDTIM0A_REVTGEN_MASK 0x40000000
-#define MCDE_LCDTIM0A_REVTGEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, REVTGEN, __x)
-#define MCDE_LCDTIM0A_REVVAEN_SHIFT 31
-#define MCDE_LCDTIM0A_REVVAEN_MASK 0x80000000
-#define MCDE_LCDTIM0A_REVVAEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0A, REVVAEN, __x)
-#define MCDE_LCDTIM0B 0x00000A5C
-#define MCDE_LCDTIM0B_PSDEL0_SHIFT 0
-#define MCDE_LCDTIM0B_PSDEL0_MASK 0x000000FF
-#define MCDE_LCDTIM0B_PSDEL0(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, PSDEL0, __x)
-#define MCDE_LCDTIM0B_PSDEL1_SHIFT 1
-#define MCDE_LCDTIM0B_PSDEL1_MASK 0x0000001E
-#define MCDE_LCDTIM0B_PSDEL1(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, PSDEL1, __x)
-#define MCDE_LCDTIM0B_PSLOADSEL_SHIFT 12
-#define MCDE_LCDTIM0B_PSLOADSEL_MASK 0x00003000
-#define MCDE_LCDTIM0B_PSLOADSEL_HBP 0
-#define MCDE_LCDTIM0B_PSLOADSEL_CLP 1
-#define MCDE_LCDTIM0B_PSLOADSEL_HFP 2
-#define MCDE_LCDTIM0B_PSLOADSEL_HSW 3
-#define MCDE_LCDTIM0B_PSLOADSEL_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, PSLOADSEL, MCDE_LCDTIM0B_PSLOADSEL_##__x)
-#define MCDE_LCDTIM0B_PSLOADSEL(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, PSLOADSEL, __x)
-#define MCDE_LCDTIM0B_PSTGEN_SHIFT 14
-#define MCDE_LCDTIM0B_PSTGEN_MASK 0x00004000
-#define MCDE_LCDTIM0B_PSTGEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, PSTGEN, __x)
-#define MCDE_LCDTIM0B_PSVAEN_SHIFT 15
-#define MCDE_LCDTIM0B_PSVAEN_MASK 0x00008000
-#define MCDE_LCDTIM0B_PSVAEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, PSVAEN, __x)
-#define MCDE_LCDTIM0B_REVDEL0_SHIFT 16
-#define MCDE_LCDTIM0B_REVDEL0_MASK 0x00FF0000
-#define MCDE_LCDTIM0B_REVDEL0(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, REVDEL0, __x)
-#define MCDE_LCDTIM0B_REVDEL1_SHIFT 24
-#define MCDE_LCDTIM0B_REVDEL1_MASK 0x0F000000
-#define MCDE_LCDTIM0B_REVDEL1(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, REVDEL1, __x)
-#define MCDE_LCDTIM0B_REVLOADSEL_SHIFT 28
-#define MCDE_LCDTIM0B_REVLOADSEL_MASK 0x30000000
-#define MCDE_LCDTIM0B_REVLOADSEL_HBP 0
-#define MCDE_LCDTIM0B_REVLOADSEL_CLP 1
-#define MCDE_LCDTIM0B_REVLOADSEL_HFP 2
-#define MCDE_LCDTIM0B_REVLOADSEL_HSW 3
-#define MCDE_LCDTIM0B_REVLOADSEL_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, REVLOADSEL, MCDE_LCDTIM0B_REVLOADSEL_##__x)
-#define MCDE_LCDTIM0B_REVLOADSEL(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, REVLOADSEL, __x)
-#define MCDE_LCDTIM0B_REVTGEN_SHIFT 30
-#define MCDE_LCDTIM0B_REVTGEN_MASK 0x40000000
-#define MCDE_LCDTIM0B_REVTGEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, REVTGEN, __x)
-#define MCDE_LCDTIM0B_REVVAEN_SHIFT 31
-#define MCDE_LCDTIM0B_REVVAEN_MASK 0x80000000
-#define MCDE_LCDTIM0B_REVVAEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM0B, REVVAEN, __x)
 #define MCDE_LCDTIM1A 0x00000860
 #define MCDE_LCDTIM1A_GROUPOFFSET 0x200
-#define MCDE_LCDTIM1A_SPLDEL0_SHIFT 0
-#define MCDE_LCDTIM1A_SPLDEL0_MASK 0x000000FF
-#define MCDE_LCDTIM1A_SPLDEL0(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, SPLDEL0, __x)
-#define MCDE_LCDTIM1A_SPLDEL1_SHIFT 8
-#define MCDE_LCDTIM1A_SPLDEL1_MASK 0x00000F00
-#define MCDE_LCDTIM1A_SPLDEL1(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, SPLDEL1, __x)
-#define MCDE_LCDTIM1A_SPLLOADSEL_SHIFT 12
-#define MCDE_LCDTIM1A_SPLLOADSEL_MASK 0x00003000
-#define MCDE_LCDTIM1A_SPLLOADSEL_HBP 0
-#define MCDE_LCDTIM1A_SPLLOADSEL_CLP 1
-#define MCDE_LCDTIM1A_SPLLOADSEL_HFP 2
-#define MCDE_LCDTIM1A_SPLLOADSEL_HSW 3
-#define MCDE_LCDTIM1A_SPLLOADSEL_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, SPLLOADSEL, MCDE_LCDTIM1A_SPLLOADSEL_##__x)
-#define MCDE_LCDTIM1A_SPLLOADSEL(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, SPLLOADSEL, __x)
-#define MCDE_LCDTIM1A_SPLTGEN_SHIFT 14
-#define MCDE_LCDTIM1A_SPLTGEN_MASK 0x00004000
-#define MCDE_LCDTIM1A_SPLTGEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, SPLTGEN, __x)
-#define MCDE_LCDTIM1A_SPLVAEN_SHIFT 15
-#define MCDE_LCDTIM1A_SPLVAEN_MASK 0x00008000
-#define MCDE_LCDTIM1A_SPLVAEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, SPLVAEN, __x)
-#define MCDE_LCDTIM1A_ICLSP_SHIFT 16
-#define MCDE_LCDTIM1A_ICLSP_MASK 0x00010000
-#define MCDE_LCDTIM1A_ICLSP(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, ICLSP, __x)
-#define MCDE_LCDTIM1A_ICLREV_SHIFT 17
-#define MCDE_LCDTIM1A_ICLREV_MASK 0x00020000
-#define MCDE_LCDTIM1A_ICLREV(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, ICLREV, __x)
-#define MCDE_LCDTIM1A_LCLSPL_SHIFT 18
-#define MCDE_LCDTIM1A_LCLSPL_MASK 0x00040000
-#define MCDE_LCDTIM1A_LCLSPL(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1A, LCLSPL, __x)
 #define MCDE_LCDTIM1A_IVP_SHIFT 19
 #define MCDE_LCDTIM1A_IVP_MASK 0x00080000
 #define MCDE_LCDTIM1A_IVP(__x) \
@@ -3522,44 +3593,6 @@
 #define MCDE_LCDTIM1A_IOE(__x) \
 	MCDE_VAL2REG(MCDE_LCDTIM1A, IOE, __x)
 #define MCDE_LCDTIM1B 0x00000A60
-#define MCDE_LCDTIM1B_SPLDEL0_SHIFT 0
-#define MCDE_LCDTIM1B_SPLDEL0_MASK 0x000000FF
-#define MCDE_LCDTIM1B_SPLDEL0(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, SPLDEL0, __x)
-#define MCDE_LCDTIM1B_SPLDEL1_SHIFT 8
-#define MCDE_LCDTIM1B_SPLDEL1_MASK 0x00000F00
-#define MCDE_LCDTIM1B_SPLDEL1(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, SPLDEL1, __x)
-#define MCDE_LCDTIM1B_SPLLOADSEL_SHIFT 12
-#define MCDE_LCDTIM1B_SPLLOADSEL_MASK 0x00003000
-#define MCDE_LCDTIM1B_SPLLOADSEL_HBP 0
-#define MCDE_LCDTIM1B_SPLLOADSEL_CLP 1
-#define MCDE_LCDTIM1B_SPLLOADSEL_HFP 2
-#define MCDE_LCDTIM1B_SPLLOADSEL_HSW 3
-#define MCDE_LCDTIM1B_SPLLOADSEL_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, SPLLOADSEL, MCDE_LCDTIM1B_SPLLOADSEL_##__x)
-#define MCDE_LCDTIM1B_SPLLOADSEL(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, SPLLOADSEL, __x)
-#define MCDE_LCDTIM1B_SPLTGEN_SHIFT 14
-#define MCDE_LCDTIM1B_SPLTGEN_MASK 0x00004000
-#define MCDE_LCDTIM1B_SPLTGEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, SPLTGEN, __x)
-#define MCDE_LCDTIM1B_SPLVAEN_SHIFT 15
-#define MCDE_LCDTIM1B_SPLVAEN_MASK 0x00008000
-#define MCDE_LCDTIM1B_SPLVAEN(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, SPLVAEN, __x)
-#define MCDE_LCDTIM1B_ICLSP_SHIFT 16
-#define MCDE_LCDTIM1B_ICLSP_MASK 0x00010000
-#define MCDE_LCDTIM1B_ICLSP(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, ICLSP, __x)
-#define MCDE_LCDTIM1B_ICLREV_SHIFT 17
-#define MCDE_LCDTIM1B_ICLREV_MASK 0x00020000
-#define MCDE_LCDTIM1B_ICLREV(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, ICLREV, __x)
-#define MCDE_LCDTIM1B_LCLSPL_SHIFT 18
-#define MCDE_LCDTIM1B_LCLSPL_MASK 0x00040000
-#define MCDE_LCDTIM1B_LCLSPL(__x) \
-	MCDE_VAL2REG(MCDE_LCDTIM1B, LCLSPL, __x)
 #define MCDE_LCDTIM1B_IVP_SHIFT 19
 #define MCDE_LCDTIM1B_IVP_MASK 0x00080000
 #define MCDE_LCDTIM1B_IVP(__x) \
@@ -3690,24 +3723,24 @@
 	MCDE_VAL2REG(MCDE_PAL1B, RED, __x)
 #define MCDE_ROTADD0A 0x00000874
 #define MCDE_ROTADD0A_GROUPOFFSET 0x200
-#define MCDE_ROTADD0A_ROTADD0_SHIFT 0
-#define MCDE_ROTADD0A_ROTADD0_MASK 0xFFFFFFFF
+#define MCDE_ROTADD0A_ROTADD0_SHIFT 3
+#define MCDE_ROTADD0A_ROTADD0_MASK 0xFFFFFFF8
 #define MCDE_ROTADD0A_ROTADD0(__x) \
 	MCDE_VAL2REG(MCDE_ROTADD0A, ROTADD0, __x)
 #define MCDE_ROTADD0B 0x00000A74
-#define MCDE_ROTADD0B_ROTADD0_SHIFT 0
-#define MCDE_ROTADD0B_ROTADD0_MASK 0xFFFFFFFF
+#define MCDE_ROTADD0B_ROTADD0_SHIFT 3
+#define MCDE_ROTADD0B_ROTADD0_MASK 0xFFFFFFF8
 #define MCDE_ROTADD0B_ROTADD0(__x) \
 	MCDE_VAL2REG(MCDE_ROTADD0B, ROTADD0, __x)
 #define MCDE_ROTADD1A 0x00000878
 #define MCDE_ROTADD1A_GROUPOFFSET 0x200
-#define MCDE_ROTADD1A_ROTADD1_SHIFT 0
-#define MCDE_ROTADD1A_ROTADD1_MASK 0xFFFFFFFF
+#define MCDE_ROTADD1A_ROTADD1_SHIFT 3
+#define MCDE_ROTADD1A_ROTADD1_MASK 0xFFFFFFF8
 #define MCDE_ROTADD1A_ROTADD1(__x) \
 	MCDE_VAL2REG(MCDE_ROTADD1A, ROTADD1, __x)
 #define MCDE_ROTADD1B 0x00000A78
-#define MCDE_ROTADD1B_ROTADD1_SHIFT 0
-#define MCDE_ROTADD1B_ROTADD1_MASK 0xFFFFFFFF
+#define MCDE_ROTADD1B_ROTADD1_SHIFT 3
+#define MCDE_ROTADD1B_ROTADD1_MASK 0xFFFFFFF8
 #define MCDE_ROTADD1B_ROTADD1(__x) \
 	MCDE_VAL2REG(MCDE_ROTADD1B, ROTADD1, __x)
 #define MCDE_ROTACONF 0x0000087C
@@ -3737,14 +3770,26 @@
 	MCDE_VAL2REG(MCDE_ROTACONF, ROTDIR, __x)
 #define MCDE_ROTACONF_WR_MAXOUT_SHIFT 4
 #define MCDE_ROTACONF_WR_MAXOUT_MASK 0x00000030
+#define MCDE_ROTACONF_WR_MAXOUT_1_REQ 0
+#define MCDE_ROTACONF_WR_MAXOUT_2_REQ 1
+#define MCDE_ROTACONF_WR_MAXOUT_4_REQ 2
+#define MCDE_ROTACONF_WR_MAXOUT_8_REQ 3
+#define MCDE_ROTACONF_WR_MAXOUT_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_ROTACONF, WR_MAXOUT, MCDE_ROTACONF_WR_MAXOUT_##__x)
 #define MCDE_ROTACONF_WR_MAXOUT(__x) \
 	MCDE_VAL2REG(MCDE_ROTACONF, WR_MAXOUT, __x)
 #define MCDE_ROTACONF_RD_MAXOUT_SHIFT 6
 #define MCDE_ROTACONF_RD_MAXOUT_MASK 0x000000C0
+#define MCDE_ROTACONF_RD_MAXOUT_1_REQ 0
+#define MCDE_ROTACONF_RD_MAXOUT_2_REQ 1
+#define MCDE_ROTACONF_RD_MAXOUT_4_REQ 2
+#define MCDE_ROTACONF_RD_MAXOUT_8_REQ 3
+#define MCDE_ROTACONF_RD_MAXOUT_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_ROTACONF, RD_MAXOUT, MCDE_ROTACONF_RD_MAXOUT_##__x)
 #define MCDE_ROTACONF_RD_MAXOUT(__x) \
 	MCDE_VAL2REG(MCDE_ROTACONF, RD_MAXOUT, __x)
 #define MCDE_ROTACONF_STRIP_WIDTH_SHIFT 8
-#define MCDE_ROTACONF_STRIP_WIDTH_MASK 0x0000FF00
+#define MCDE_ROTACONF_STRIP_WIDTH_MASK 0x00007F00
 #define MCDE_ROTACONF_STRIP_WIDTH_2PIX 0
 #define MCDE_ROTACONF_STRIP_WIDTH_4PIX 1
 #define MCDE_ROTACONF_STRIP_WIDTH_8PIX 2
@@ -3755,6 +3800,10 @@
 	MCDE_ROTACONF_STRIP_WIDTH_##__x)
 #define MCDE_ROTACONF_STRIP_WIDTH(__x) \
 	MCDE_VAL2REG(MCDE_ROTACONF, STRIP_WIDTH, __x)
+#define MCDE_ROTACONF_SINGLE_BUF_SHIFT 15
+#define MCDE_ROTACONF_SINGLE_BUF_MASK 0x00008000
+#define MCDE_ROTACONF_SINGLE_BUF(__x) \
+	MCDE_VAL2REG(MCDE_ROTACONF, SINGLE_BUF, __x)
 #define MCDE_ROTACONF_WR_ROPC_SHIFT 16
 #define MCDE_ROTACONF_WR_ROPC_MASK 0x00FF0000
 #define MCDE_ROTACONF_WR_ROPC(__x) \
@@ -3789,14 +3838,26 @@
 	MCDE_VAL2REG(MCDE_ROTBCONF, ROTDIR, __x)
 #define MCDE_ROTBCONF_WR_MAXOUT_SHIFT 4
 #define MCDE_ROTBCONF_WR_MAXOUT_MASK 0x00000030
+#define MCDE_ROTBCONF_WR_MAXOUT_1_REQ 0
+#define MCDE_ROTBCONF_WR_MAXOUT_2_REQ 1
+#define MCDE_ROTBCONF_WR_MAXOUT_4_REQ 2
+#define MCDE_ROTBCONF_WR_MAXOUT_8_REQ 3
+#define MCDE_ROTBCONF_WR_MAXOUT_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_ROTBCONF, WR_MAXOUT, MCDE_ROTBCONF_WR_MAXOUT_##__x)
 #define MCDE_ROTBCONF_WR_MAXOUT(__x) \
 	MCDE_VAL2REG(MCDE_ROTBCONF, WR_MAXOUT, __x)
 #define MCDE_ROTBCONF_RD_MAXOUT_SHIFT 6
 #define MCDE_ROTBCONF_RD_MAXOUT_MASK 0x000000C0
+#define MCDE_ROTBCONF_RD_MAXOUT_1_REQ 0
+#define MCDE_ROTBCONF_RD_MAXOUT_2_REQ 1
+#define MCDE_ROTBCONF_RD_MAXOUT_4_REQ 2
+#define MCDE_ROTBCONF_RD_MAXOUT_8_REQ 3
+#define MCDE_ROTBCONF_RD_MAXOUT_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_ROTBCONF, RD_MAXOUT, MCDE_ROTBCONF_RD_MAXOUT_##__x)
 #define MCDE_ROTBCONF_RD_MAXOUT(__x) \
 	MCDE_VAL2REG(MCDE_ROTBCONF, RD_MAXOUT, __x)
 #define MCDE_ROTBCONF_STRIP_WIDTH_SHIFT 8
-#define MCDE_ROTBCONF_STRIP_WIDTH_MASK 0x0000FF00
+#define MCDE_ROTBCONF_STRIP_WIDTH_MASK 0x00007F00
 #define MCDE_ROTBCONF_STRIP_WIDTH_2PIX 0
 #define MCDE_ROTBCONF_STRIP_WIDTH_4PIX 1
 #define MCDE_ROTBCONF_STRIP_WIDTH_8PIX 2
@@ -3807,6 +3868,10 @@
 	MCDE_ROTBCONF_STRIP_WIDTH_##__x)
 #define MCDE_ROTBCONF_STRIP_WIDTH(__x) \
 	MCDE_VAL2REG(MCDE_ROTBCONF, STRIP_WIDTH, __x)
+#define MCDE_ROTBCONF_SINGLE_BUF_SHIFT 15
+#define MCDE_ROTBCONF_SINGLE_BUF_MASK 0x00008000
+#define MCDE_ROTBCONF_SINGLE_BUF(__x) \
+	MCDE_VAL2REG(MCDE_ROTBCONF, SINGLE_BUF, __x)
 #define MCDE_ROTBCONF_WR_ROPC_SHIFT 16
 #define MCDE_ROTBCONF_WR_ROPC_MASK 0x00FF0000
 #define MCDE_ROTBCONF_WR_ROPC(__x) \
@@ -3878,6 +3943,79 @@
 #define MCDE_SYNCHCONFB_SWINTVCNT_MASK 0xFFFC0000
 #define MCDE_SYNCHCONFB_SWINTVCNT(__x) \
 	MCDE_VAL2REG(MCDE_SYNCHCONFB, SWINTVCNT, __x)
+#define MCDE_CTRLA 0x00000884
+#define MCDE_CTRLA_GROUPOFFSET 0x200
+#define MCDE_CTRLA_FIFOWTRMRK_SHIFT 0
+#define MCDE_CTRLA_FIFOWTRMRK_MASK 0x000003FF
+#define MCDE_CTRLA_FIFOWTRMRK(__x) \
+	MCDE_VAL2REG(MCDE_CTRLA, FIFOWTRMRK, __x)
+#define MCDE_CTRLA_FIFOEMPTY_SHIFT 12
+#define MCDE_CTRLA_FIFOEMPTY_MASK 0x00001000
+#define MCDE_CTRLA_FIFOEMPTY(__x) \
+	MCDE_VAL2REG(MCDE_CTRLA, FIFOEMPTY, __x)
+#define MCDE_CTRLA_FIFOFULL_SHIFT 13
+#define MCDE_CTRLA_FIFOFULL_MASK 0x00002000
+#define MCDE_CTRLA_FIFOFULL(__x) \
+	MCDE_VAL2REG(MCDE_CTRLA, FIFOFULL, __x)
+#define MCDE_CTRLA_FORMID_SHIFT 16
+#define MCDE_CTRLA_FORMID_MASK 0x00070000
+#define MCDE_CTRLA_FORMID_DSI0VID 0
+#define MCDE_CTRLA_FORMID_DSI0CMD 1
+#define MCDE_CTRLA_FORMID_DSI1VID 2
+#define MCDE_CTRLA_FORMID_DSI1CMD 0
+#define MCDE_CTRLA_FORMID_DSI2VID 1
+#define MCDE_CTRLA_FORMID_DSI2CMD 2
+#define MCDE_CTRLA_FORMID_DPIA 0
+#define MCDE_CTRLA_FORMID_DPIB 1
+#define MCDE_CTRLA_FORMID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CTRLA, FORMID, MCDE_CTRLA_FORMID_##__x)
+#define MCDE_CTRLA_FORMID(__x) \
+	MCDE_VAL2REG(MCDE_CTRLA, FORMID, __x)
+#define MCDE_CTRLA_FORMTYPE_SHIFT 20
+#define MCDE_CTRLA_FORMTYPE_MASK 0x00700000
+#define MCDE_CTRLA_FORMTYPE_DPITV 0
+#define MCDE_CTRLA_FORMTYPE_DBI 1
+#define MCDE_CTRLA_FORMTYPE_DSI 2
+#define MCDE_CTRLA_FORMTYPE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CTRLA, FORMTYPE, MCDE_CTRLA_FORMTYPE_##__x)
+#define MCDE_CTRLA_FORMTYPE(__x) \
+	MCDE_VAL2REG(MCDE_CTRLA, FORMTYPE, __x)
+#define MCDE_CTRLB 0x00000A84
+#define MCDE_CTRLB_FIFOWTRMRK_SHIFT 0
+#define MCDE_CTRLB_FIFOWTRMRK_MASK 0x000003FF
+#define MCDE_CTRLB_FIFOWTRMRK(__x) \
+	MCDE_VAL2REG(MCDE_CTRLB, FIFOWTRMRK, __x)
+#define MCDE_CTRLB_FIFOEMPTY_SHIFT 12
+#define MCDE_CTRLB_FIFOEMPTY_MASK 0x00001000
+#define MCDE_CTRLB_FIFOEMPTY(__x) \
+	MCDE_VAL2REG(MCDE_CTRLB, FIFOEMPTY, __x)
+#define MCDE_CTRLB_FIFOFULL_SHIFT 13
+#define MCDE_CTRLB_FIFOFULL_MASK 0x00002000
+#define MCDE_CTRLB_FIFOFULL(__x) \
+	MCDE_VAL2REG(MCDE_CTRLB, FIFOFULL, __x)
+#define MCDE_CTRLB_FORMID_SHIFT 16
+#define MCDE_CTRLB_FORMID_MASK 0x00070000
+#define MCDE_CTRLB_FORMID_DSI0VID 0
+#define MCDE_CTRLB_FORMID_DSI0CMD 1
+#define MCDE_CTRLB_FORMID_DSI1VID 2
+#define MCDE_CTRLB_FORMID_DSI1CMD 0
+#define MCDE_CTRLB_FORMID_DSI2VID 1
+#define MCDE_CTRLB_FORMID_DSI2CMD 2
+#define MCDE_CTRLB_FORMID_DPIA 0
+#define MCDE_CTRLB_FORMID_DPIB 1
+#define MCDE_CTRLB_FORMID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CTRLB, FORMID, MCDE_CTRLB_FORMID_##__x)
+#define MCDE_CTRLB_FORMID(__x) \
+	MCDE_VAL2REG(MCDE_CTRLB, FORMID, __x)
+#define MCDE_CTRLB_FORMTYPE_SHIFT 20
+#define MCDE_CTRLB_FORMTYPE_MASK 0x00700000
+#define MCDE_CTRLB_FORMTYPE_DPITV 0
+#define MCDE_CTRLB_FORMTYPE_DBI 1
+#define MCDE_CTRLB_FORMTYPE_DSI 2
+#define MCDE_CTRLB_FORMTYPE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CTRLB, FORMTYPE, MCDE_CTRLB_FORMTYPE_##__x)
+#define MCDE_CTRLB_FORMTYPE(__x) \
+	MCDE_VAL2REG(MCDE_CTRLB, FORMTYPE, __x)
 #define MCDE_GAM0A 0x00000888
 #define MCDE_GAM0A_GROUPOFFSET 0x200
 #define MCDE_GAM0A_BLUE_SHIFT 0
@@ -4427,23 +4565,39 @@
 	MCDE_VAL2REG(MCDE_BCNR1, BCN, __x)
 #define MCDE_CSCDTR0 0x00000C74
 #define MCDE_CSCDTR0_GROUPOFFSET 0x4
-#define MCDE_CSCDTR0_CSCDACT_SHIFT 0
-#define MCDE_CSCDTR0_CSCDACT_MASK 0x000000FF
-#define MCDE_CSCDTR0_CSCDACT(__x) \
-	MCDE_VAL2REG(MCDE_CSCDTR0, CSCDACT, __x)
-#define MCDE_CSCDTR0_CSCDDEACT_SHIFT 8
-#define MCDE_CSCDTR0_CSCDDEACT_MASK 0x0000FF00
-#define MCDE_CSCDTR0_CSCDDEACT(__x) \
-	MCDE_VAL2REG(MCDE_CSCDTR0, CSCDDEACT, __x)
+#define MCDE_CSCDTR0_CSACT_SHIFT 0
+#define MCDE_CSCDTR0_CSACT_MASK 0x000000FF
+#define MCDE_CSCDTR0_CSACT(__x) \
+	MCDE_VAL2REG(MCDE_CSCDTR0, CSACT, __x)
+#define MCDE_CSCDTR0_CSDEACT_SHIFT 8
+#define MCDE_CSCDTR0_CSDEACT_MASK 0x0000FF00
+#define MCDE_CSCDTR0_CSDEACT(__x) \
+	MCDE_VAL2REG(MCDE_CSCDTR0, CSDEACT, __x)
+#define MCDE_CSCDTR0_CDACT_SHIFT 16
+#define MCDE_CSCDTR0_CDACT_MASK 0x00FF0000
+#define MCDE_CSCDTR0_CDACT(__x) \
+	MCDE_VAL2REG(MCDE_CSCDTR0, CDACT, __x)
+#define MCDE_CSCDTR0_CDDEACT_SHIFT 24
+#define MCDE_CSCDTR0_CDDEACT_MASK 0xFF000000
+#define MCDE_CSCDTR0_CDDEACT(__x) \
+	MCDE_VAL2REG(MCDE_CSCDTR0, CDDEACT, __x)
 #define MCDE_CSCDTR1 0x00000C78
-#define MCDE_CSCDTR1_CSCDACT_SHIFT 0
-#define MCDE_CSCDTR1_CSCDACT_MASK 0x000000FF
-#define MCDE_CSCDTR1_CSCDACT(__x) \
-	MCDE_VAL2REG(MCDE_CSCDTR1, CSCDACT, __x)
-#define MCDE_CSCDTR1_CSCDDEACT_SHIFT 8
-#define MCDE_CSCDTR1_CSCDDEACT_MASK 0x0000FF00
-#define MCDE_CSCDTR1_CSCDDEACT(__x) \
-	MCDE_VAL2REG(MCDE_CSCDTR1, CSCDDEACT, __x)
+#define MCDE_CSCDTR1_CSACT_SHIFT 0
+#define MCDE_CSCDTR1_CSACT_MASK 0x000000FF
+#define MCDE_CSCDTR1_CSACT(__x) \
+	MCDE_VAL2REG(MCDE_CSCDTR1, CSACT, __x)
+#define MCDE_CSCDTR1_CSDEACT_SHIFT 8
+#define MCDE_CSCDTR1_CSDEACT_MASK 0x0000FF00
+#define MCDE_CSCDTR1_CSDEACT(__x) \
+	MCDE_VAL2REG(MCDE_CSCDTR1, CSDEACT, __x)
+#define MCDE_CSCDTR1_CDACT_SHIFT 16
+#define MCDE_CSCDTR1_CDACT_MASK 0x00FF0000
+#define MCDE_CSCDTR1_CDACT(__x) \
+	MCDE_VAL2REG(MCDE_CSCDTR1, CDACT, __x)
+#define MCDE_CSCDTR1_CDDEACT_SHIFT 24
+#define MCDE_CSCDTR1_CDDEACT_MASK 0xFF000000
+#define MCDE_CSCDTR1_CDDEACT(__x) \
+	MCDE_VAL2REG(MCDE_CSCDTR1, CDDEACT, __x)
 #define MCDE_RDWRTR0 0x00000C7C
 #define MCDE_RDWRTR0_GROUPOFFSET 0x4
 #define MCDE_RDWRTR0_RWACT_SHIFT 0
@@ -4490,17 +4644,17 @@
 #define MCDE_DOTR1_DODEACT_MASK 0x0000FF00
 #define MCDE_DOTR1_DODEACT(__x) \
 	MCDE_VAL2REG(MCDE_DOTR1, DODEACT, __x)
-#define MCDE_WCMDC0 0x00000C8C
-#define MCDE_WCMDC0_GROUPOFFSET 0x4
-#define MCDE_WCMDC0_COMMANDVALUE_SHIFT 0
-#define MCDE_WCMDC0_COMMANDVALUE_MASK 0x00FFFFFF
-#define MCDE_WCMDC0_COMMANDVALUE(__x) \
-	MCDE_VAL2REG(MCDE_WCMDC0, COMMANDVALUE, __x)
-#define MCDE_WCMDC1 0x00000C90
-#define MCDE_WCMDC1_COMMANDVALUE_SHIFT 0
-#define MCDE_WCMDC1_COMMANDVALUE_MASK 0x00FFFFFF
-#define MCDE_WCMDC1_COMMANDVALUE(__x) \
-	MCDE_VAL2REG(MCDE_WCMDC1, COMMANDVALUE, __x)
+#define MCDE_WCMDC0_V1 0x00000C8C
+#define MCDE_WCMDC0_V1_GROUPOFFSET 0x4
+#define MCDE_WCMDC0_V1_COMMANDVALUE_SHIFT 0
+#define MCDE_WCMDC0_V1_COMMANDVALUE_MASK 0x00FFFFFF
+#define MCDE_WCMDC0_V1_COMMANDVALUE(__x) \
+	MCDE_VAL2REG(MCDE_WCMDC0_V1, COMMANDVALUE, __x)
+#define MCDE_WCMDC1_V1 0x00000C90
+#define MCDE_WCMDC1_V1_COMMANDVALUE_SHIFT 0
+#define MCDE_WCMDC1_V1_COMMANDVALUE_MASK 0x00FFFFFF
+#define MCDE_WCMDC1_V1_COMMANDVALUE(__x) \
+	MCDE_VAL2REG(MCDE_WCMDC1_V1, COMMANDVALUE, __x)
 #define MCDE_WDATADC0 0x00000C94
 #define MCDE_WDATADC0_GROUPOFFSET 0x4
 #define MCDE_WDATADC0_DATAVALUE_SHIFT 0
@@ -4531,58 +4685,116 @@
 #define MCDE_RDATADC1_STARTREAD_MASK 0x00010000
 #define MCDE_RDATADC1_STARTREAD(__x) \
 	MCDE_VAL2REG(MCDE_RDATADC1, STARTREAD, __x)
-#define MCDE_STATC 0x00000CA4
-#define MCDE_STATC_STATBUSY0_SHIFT 0
-#define MCDE_STATC_STATBUSY0_MASK 0x00000001
-#define MCDE_STATC_STATBUSY0(__x) \
-	MCDE_VAL2REG(MCDE_STATC, STATBUSY0, __x)
-#define MCDE_STATC_FIFOEMPTY0_SHIFT 1
-#define MCDE_STATC_FIFOEMPTY0_MASK 0x00000002
-#define MCDE_STATC_FIFOEMPTY0(__x) \
-	MCDE_VAL2REG(MCDE_STATC, FIFOEMPTY0, __x)
-#define MCDE_STATC_FIFOFULL0_SHIFT 2
-#define MCDE_STATC_FIFOFULL0_MASK 0x00000004
-#define MCDE_STATC_FIFOFULL0(__x) \
-	MCDE_VAL2REG(MCDE_STATC, FIFOFULL0, __x)
-#define MCDE_STATC_FIFOCMDEMPTY0_SHIFT 3
-#define MCDE_STATC_FIFOCMDEMPTY0_MASK 0x00000008
-#define MCDE_STATC_FIFOCMDEMPTY0(__x) \
-	MCDE_VAL2REG(MCDE_STATC, FIFOCMDEMPTY0, __x)
-#define MCDE_STATC_FIFOCMDFULL0_SHIFT 4
-#define MCDE_STATC_FIFOCMDFULL0_MASK 0x00000010
-#define MCDE_STATC_FIFOCMDFULL0(__x) \
-	MCDE_VAL2REG(MCDE_STATC, FIFOCMDFULL0, __x)
-#define MCDE_STATC_STATBUSY1_SHIFT 5
-#define MCDE_STATC_STATBUSY1_MASK 0x00000020
-#define MCDE_STATC_STATBUSY1(__x) \
-	MCDE_VAL2REG(MCDE_STATC, STATBUSY1, __x)
-#define MCDE_STATC_FIFOEMPTY1_SHIFT 6
-#define MCDE_STATC_FIFOEMPTY1_MASK 0x00000040
-#define MCDE_STATC_FIFOEMPTY1(__x) \
-	MCDE_VAL2REG(MCDE_STATC, FIFOEMPTY1, __x)
-#define MCDE_STATC_FIFOFULL1_SHIFT 7
-#define MCDE_STATC_FIFOFULL1_MASK 0x00000080
-#define MCDE_STATC_FIFOFULL1(__x) \
-	MCDE_VAL2REG(MCDE_STATC, FIFOFULL1, __x)
-#define MCDE_STATC_FIFOCMDEMPTY1_SHIFT 8
-#define MCDE_STATC_FIFOCMDEMPTY1_MASK 0x00000100
-#define MCDE_STATC_FIFOCMDEMPTY1(__x) \
-	MCDE_VAL2REG(MCDE_STATC, FIFOCMDEMPTY1, __x)
-#define MCDE_STATC_FIFOCMDFULL1_SHIFT 9
-#define MCDE_STATC_FIFOCMDFULL1_MASK 0x00000200
-#define MCDE_STATC_FIFOCMDFULL1(__x) \
-	MCDE_VAL2REG(MCDE_STATC, FIFOCMDFULL1, __x)
+#define MCDE_STATC_V1 0x00000CA4
+#define MCDE_STATC_V1_STATBUSY0_SHIFT 0
+#define MCDE_STATC_V1_STATBUSY0_MASK 0x00000001
+#define MCDE_STATC_V1_STATBUSY0(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, STATBUSY0, __x)
+#define MCDE_STATC_V1_FIFOEMPTY0_SHIFT 1
+#define MCDE_STATC_V1_FIFOEMPTY0_MASK 0x00000002
+#define MCDE_STATC_V1_FIFOEMPTY0(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, FIFOEMPTY0, __x)
+#define MCDE_STATC_V1_FIFOFULL0_SHIFT 2
+#define MCDE_STATC_V1_FIFOFULL0_MASK 0x00000004
+#define MCDE_STATC_V1_FIFOFULL0(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, FIFOFULL0, __x)
+#define MCDE_STATC_V1_FIFOCMDEMPTY0_SHIFT 3
+#define MCDE_STATC_V1_FIFOCMDEMPTY0_MASK 0x00000008
+#define MCDE_STATC_V1_FIFOCMDEMPTY0(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDEMPTY0, __x)
+#define MCDE_STATC_V1_FIFOCMDFULL0_SHIFT 4
+#define MCDE_STATC_V1_FIFOCMDFULL0_MASK 0x00000010
+#define MCDE_STATC_V1_FIFOCMDFULL0(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDFULL0, __x)
+#define MCDE_STATC_V1_STATBUSY1_SHIFT 5
+#define MCDE_STATC_V1_STATBUSY1_MASK 0x00000020
+#define MCDE_STATC_V1_STATBUSY1(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, STATBUSY1, __x)
+#define MCDE_STATC_V1_FIFOEMPTY1_SHIFT 6
+#define MCDE_STATC_V1_FIFOEMPTY1_MASK 0x00000040
+#define MCDE_STATC_V1_FIFOEMPTY1(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, FIFOEMPTY1, __x)
+#define MCDE_STATC_V1_FIFOFULL1_SHIFT 7
+#define MCDE_STATC_V1_FIFOFULL1_MASK 0x00000080
+#define MCDE_STATC_V1_FIFOFULL1(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, FIFOFULL1, __x)
+#define MCDE_STATC_V1_FIFOCMDEMPTY1_SHIFT 8
+#define MCDE_STATC_V1_FIFOCMDEMPTY1_MASK 0x00000100
+#define MCDE_STATC_V1_FIFOCMDEMPTY1(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDEMPTY1, __x)
+#define MCDE_STATC_V1_FIFOCMDFULL1_SHIFT 9
+#define MCDE_STATC_V1_FIFOCMDFULL1_MASK 0x00000200
+#define MCDE_STATC_V1_FIFOCMDFULL1(__x) \
+	MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDFULL1, __x)
 #define MCDE_CTRLC0 0x00000CA8
 #define MCDE_CTRLC0_GROUPOFFSET 0x4
 #define MCDE_CTRLC0_FIFOWTRMRK_SHIFT 0
 #define MCDE_CTRLC0_FIFOWTRMRK_MASK 0x000000FF
 #define MCDE_CTRLC0_FIFOWTRMRK(__x) \
 	MCDE_VAL2REG(MCDE_CTRLC0, FIFOWTRMRK, __x)
+#define MCDE_CTRLC0_FIFOEMPTY_SHIFT 12
+#define MCDE_CTRLC0_FIFOEMPTY_MASK 0x00001000
+#define MCDE_CTRLC0_FIFOEMPTY(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC0, FIFOEMPTY, __x)
+#define MCDE_CTRLC0_FIFOFULL_SHIFT 13
+#define MCDE_CTRLC0_FIFOFULL_MASK 0x00002000
+#define MCDE_CTRLC0_FIFOFULL(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC0, FIFOFULL, __x)
+#define MCDE_CTRLC0_FORMID_SHIFT 16
+#define MCDE_CTRLC0_FORMID_MASK 0x00070000
+#define MCDE_CTRLC0_FORMID_DSI0VID 0
+#define MCDE_CTRLC0_FORMID_DSI0CMD 1
+#define MCDE_CTRLC0_FORMID_DSI1VID 2
+#define MCDE_CTRLC0_FORMID_DSI1CMD 0
+#define MCDE_CTRLC0_FORMID_DSI2VID 1
+#define MCDE_CTRLC0_FORMID_DSI2CMD 2
+#define MCDE_CTRLC0_FORMID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC0, FORMID, MCDE_CTRLC0_FORMID_##__x)
+#define MCDE_CTRLC0_FORMID(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC0, FORMID, __x)
+#define MCDE_CTRLC0_FORMTYPE_SHIFT 20
+#define MCDE_CTRLC0_FORMTYPE_MASK 0x00700000
+#define MCDE_CTRLC0_FORMTYPE_DPITV 0
+#define MCDE_CTRLC0_FORMTYPE_DBI 1
+#define MCDE_CTRLC0_FORMTYPE_DSI 2
+#define MCDE_CTRLC0_FORMTYPE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC0, FORMTYPE, MCDE_CTRLC0_FORMTYPE_##__x)
+#define MCDE_CTRLC0_FORMTYPE(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC0, FORMTYPE, __x)
 #define MCDE_CTRLC1 0x00000CAC
 #define MCDE_CTRLC1_FIFOWTRMRK_SHIFT 0
 #define MCDE_CTRLC1_FIFOWTRMRK_MASK 0x000000FF
 #define MCDE_CTRLC1_FIFOWTRMRK(__x) \
 	MCDE_VAL2REG(MCDE_CTRLC1, FIFOWTRMRK, __x)
+#define MCDE_CTRLC1_FIFOEMPTY_SHIFT 12
+#define MCDE_CTRLC1_FIFOEMPTY_MASK 0x00001000
+#define MCDE_CTRLC1_FIFOEMPTY(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC1, FIFOEMPTY, __x)
+#define MCDE_CTRLC1_FIFOFULL_SHIFT 13
+#define MCDE_CTRLC1_FIFOFULL_MASK 0x00002000
+#define MCDE_CTRLC1_FIFOFULL(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC1, FIFOFULL, __x)
+#define MCDE_CTRLC1_FORMID_SHIFT 16
+#define MCDE_CTRLC1_FORMID_MASK 0x00070000
+#define MCDE_CTRLC1_FORMID_DSI0VID 0
+#define MCDE_CTRLC1_FORMID_DSI0CMD 1
+#define MCDE_CTRLC1_FORMID_DSI1VID 2
+#define MCDE_CTRLC1_FORMID_DSI1CMD 0
+#define MCDE_CTRLC1_FORMID_DSI2VID 1
+#define MCDE_CTRLC1_FORMID_DSI2CMD 2
+#define MCDE_CTRLC1_FORMID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC1, FORMID, MCDE_CTRLC1_FORMID_##__x)
+#define MCDE_CTRLC1_FORMID(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC1, FORMID, __x)
+#define MCDE_CTRLC1_FORMTYPE_SHIFT 20
+#define MCDE_CTRLC1_FORMTYPE_MASK 0x00700000
+#define MCDE_CTRLC1_FORMTYPE_DPITV 0
+#define MCDE_CTRLC1_FORMTYPE_DBI 1
+#define MCDE_CTRLC1_FORMTYPE_DSI 2
+#define MCDE_CTRLC1_FORMTYPE_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC1, FORMTYPE, MCDE_CTRLC1_FORMTYPE_##__x)
+#define MCDE_CTRLC1_FORMTYPE(__x) \
+	MCDE_VAL2REG(MCDE_CTRLC1, FORMTYPE, __x)
 #define MCDE_DSIVID0CONF0 0x00000E00
 #define MCDE_DSIVID0CONF0_GROUPOFFSET 0x20
 #define MCDE_DSIVID0CONF0_BLANKING_SHIFT 0
@@ -5094,5 +5306,4 @@
 #define MCDE_DSICMD2DELAY1_FRAMESTARTDEL_MASK 0x00FF0000
 #define MCDE_DSICMD2DELAY1_FRAMESTARTDEL(__x) \
 	MCDE_VAL2REG(MCDE_DSICMD2DELAY1, FRAMESTARTDEL, __x)
-
 #endif /*__MCDE_REGS_H_ */
diff --git a/board/st/u8500/u8500.c b/board/st/u8500/u8500.c
index ea6873e61..10b79f08b 100644
--- a/board/st/u8500/u8500.c
+++ b/board/st/u8500/u8500.c
@@ -271,45 +271,31 @@ int dram_init(void)
 #ifdef CONFIG_VIDEO_LOGO
 int dss_init(void)
 {
-	int ret = 0;
 	uchar byte;
 	puts("MCDE:  ");
-	if (!cpu_is_u8500v11()) {
-		printf("Only HREF+ is supported \n");
+	if (!cpu_is_u8500v11() && !cpu_is_u8500v2()) {
+		printf("Only HREF+ or V2 is supported\n");
+		goto mcde_error;
+	}
+	if (mcde_startup()) {
+		printf("startup failed\n");
+		goto mcde_error;
+	}
+	if (mcde_display_image()) {
+		printf("display_image failed\n");
 		goto mcde_error;
 	}
-	(void) i2c_set_bus_num(0);
-	(void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1);
-	if (byte == 0x01)
-		board_id = 0;
-	else
-		board_id = 1;
 
-	if (board_id != 0) {
-		ret = mcde_startup();
-		if (ret) {
-			printf("startup failed\n");
-			goto mcde_error;
-		}
-		ret = mcde_display_image();
-		if (ret) {
-			printf("display_image failed\n");
-			goto mcde_error;
-		}
+	printf("ready\n");
+	setenv("startup_graphics", "1");
+	setenv("logo", "nologo");
+	return 0;
 
-		printf("ready \n");
-		setenv("startup_graphics", "1");
-		setenv("logo", "nologo");
-		goto mcde_ok;
-	} else {
-		ret = 1;
-		printf("MOP500 is not supported \n");
-	}
 mcde_error:
 	setenv("startup_graphics", "0");
 	setenv("logo", "0");
-mcde_ok:
-	return ret;
+
+	return -EINVAL;
 
 }
 #endif