diff options
| author | Jimmy Rubin <ejimrub@steludxu031.lud.stericsson.com> | 2010-06-08 16:28:18 +0200 |
|---|---|---|
| committer | Jonas ABERG <jonas.aberg@stericsson.com> | 2010-06-10 16:58:53 +0200 |
| commit | e5e6dd7fe444b873d9113e2f4d716f63faf9ca70 (patch) | |
| tree | 9e55121cdd05d2b48ef8d505d5cd3f530f97be1f /board | |
| parent | d46a7e3528b5f86610ee388a18a9698a3d26e6fb (diff) | |
Adding support for startup graphics
This patch does the following:
* Startup graphics only support for HREF+.
* Displays a logo last in the u-boot sequence before the kernel is booted.
* Informs the kernel not to display penguins.
* Added pmem values to bootargs.
ST Ericsson Change-ID: WP236570
Change-Id: Ib176c17a795ddd002e94344eb9c67739b1e2269e
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/1048
Reviewed-by: Par-Olof HAKANSSON <par-olof.hakansson@stericsson.com>
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
Tested-by: Jonas ABERG <jonas.aberg@stericsson.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/st/u8500/Makefile | 2 | ||||
| -rw-r--r-- | board/st/u8500/dsilink_regs.h | 2036 | ||||
| -rw-r--r-- | board/st/u8500/mcde.h | 114 | ||||
| -rw-r--r-- | board/st/u8500/mcde_display.c | 297 | ||||
| -rw-r--r-- | board/st/u8500/mcde_display.h | 38 | ||||
| -rw-r--r-- | board/st/u8500/mcde_hw.c | 779 | ||||
| -rw-r--r-- | board/st/u8500/mcde_regs.h | 5098 | ||||
| -rw-r--r-- | board/st/u8500/u8500.c | 53 |
8 files changed, 8416 insertions, 1 deletions
diff --git a/board/st/u8500/Makefile b/board/st/u8500/Makefile index 28f7ac9a7..254da4eae 100644 --- a/board/st/u8500/Makefile +++ b/board/st/u8500/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk CFLAGS += -D__RELEASE -D__STN_8500 LIB = $(obj)lib$(BOARD).a -COBJS := u8500.o flash.o gpio.o u8500_i2c.o mmc.o mmc_utils.o init_mmc.o emmc.o clock.o prcmu.o +COBJS := u8500.o flash.o gpio.o u8500_i2c.o mmc.o mmc_utils.o init_mmc.o emmc.o clock.o prcmu.o mcde_display.o mcde_hw.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/st/u8500/dsilink_regs.h b/board/st/u8500/dsilink_regs.h new file mode 100644 index 000000000..69b08718b --- /dev/null +++ b/board/st/u8500/dsilink_regs.h @@ -0,0 +1,2036 @@ +/* +* Copyright (C) ST-Ericsson SA 2010 +* +* Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> +* for ST-Ericsson. +* +* License terms: GNU General Public License (GPL), version 2. +*/ +#ifndef __DSILINK_REGS_H__ +#define __DSILINK_REGS_H__ + +#define DSI_VAL2REG(__reg, __fld, __val) \ + (((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK) +#define DSI_REG2VAL(__reg, __fld, __val) \ + (((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT) + +#define DSI_MCTL_INTEGRATION_MODE 0x00000000 +#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN_SHIFT 0 +#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN_MASK 0x00000001 +#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_INTEGRATION_MODE, INT_MODE_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL 0x00000004 +#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN_SHIFT 0 +#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN_MASK 0x00000001 +#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, LINK_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_SHIFT 1 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_MASK 0x00000002 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_CMD 0 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_VID 1 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_MODE, \ + DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_##__x) +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_MODE, __x) +#define DSI_MCTL_MAIN_DATA_CTL_VID_EN_SHIFT 2 +#define DSI_MCTL_MAIN_DATA_CTL_VID_EN_MASK 0x00000004 +#define DSI_MCTL_MAIN_DATA_CTL_VID_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, VID_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL_SHIFT 3 +#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL_MASK 0x00000008 +#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, TVG_SEL, __x) +#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL_SHIFT 4 +#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL_MASK 0x00000010 +#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, TBG_SEL, __x) +#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN_SHIFT 5 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN_MASK 0x00000020 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_TE_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN_SHIFT 6 +#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN_MASK 0x00000040 +#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF2_TE_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN_SHIFT 7 +#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN_MASK 0x00000080 +#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, REG_TE_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_READ_EN_SHIFT 8 +#define DSI_MCTL_MAIN_DATA_CTL_READ_EN_MASK 0x00000100 +#define DSI_MCTL_MAIN_DATA_CTL_READ_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, READ_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN_SHIFT 9 +#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN_MASK 0x00000200 +#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, BTA_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC_SHIFT 10 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC_MASK 0x00000400 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_GEN_ECC, __x) +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM_SHIFT 11 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM_MASK 0x00000800 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_GEN_CHECKSUM, __x) +#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN_SHIFT 12 +#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN_MASK 0x00001000 +#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, HOST_EOT_GEN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN_SHIFT 13 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN_MASK 0x00002000 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_EOT_GEN, __x) +#define DSI_MCTL_MAIN_PHY_CTL 0x00000008 +#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN_SHIFT 0 +#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN_MASK 0x00000001 +#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, LANE2_EN, __x) +#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE_SHIFT 1 +#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE_MASK 0x00000002 +#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, FORCE_STOP_MODE, __x) +#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS_SHIFT 2 +#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS_MASK 0x00000004 +#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, CLK_CONTINUOUS, __x) +#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN_SHIFT 3 +#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN_MASK 0x00000008 +#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, CLK_ULPM_EN, __x) +#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN_SHIFT 4 +#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN_MASK 0x00000010 +#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, DAT1_ULPM_EN, __x) +#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN_SHIFT 5 +#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN_MASK 0x00000020 +#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, DAT2_ULPM_EN, __x) +#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT 6 +#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0 +#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, WAIT_BURST_TIME, __x) +#define DSI_MCTL_PLL_CTL 0x0000000C +#define DSI_MCTL_PLL_CTL_PLL_MULT_SHIFT 0 +#define DSI_MCTL_PLL_CTL_PLL_MULT_MASK 0x000000FF +#define DSI_MCTL_PLL_CTL_PLL_MULT(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_MULT, __x) +#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV_SHIFT 8 +#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV_MASK 0x00003F00 +#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_DIV, __x) +#define DSI_MCTL_PLL_CTL_PLL_IN_DIV_SHIFT 14 +#define DSI_MCTL_PLL_CTL_PLL_IN_DIV_MASK 0x0001C000 +#define DSI_MCTL_PLL_CTL_PLL_IN_DIV(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_IN_DIV, __x) +#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2_SHIFT 17 +#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2_MASK 0x00020000 +#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_SEL_DIV2, __x) +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_SHIFT 18 +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_MASK 0x00040000 +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_INT_PLL 0 +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_SYS_PLL 1 +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_SEL, \ + DSI_MCTL_PLL_CTL_PLL_OUT_SEL_##__x) +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_SEL, __x) +#define DSI_MCTL_PLL_CTL_PLL_MASTER_SHIFT 31 +#define DSI_MCTL_PLL_CTL_PLL_MASTER_MASK 0x80000000 +#define DSI_MCTL_PLL_CTL_PLL_MASTER(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_MASTER, __x) +#define DSI_MCTL_LANE_STS 0x00000010 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_SHIFT 0 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_MASK 0x00000003 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_START 0 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_IDLE 1 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_HS 2 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_ULPM 3 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, CLKLANE_STATE, \ + DSI_MCTL_LANE_STS_CLKLANE_STATE_##__x) +#define DSI_MCTL_LANE_STS_CLKLANE_STATE(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, CLKLANE_STATE, __x) +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_SHIFT 2 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_MASK 0x0000001C +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_START 0 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_IDLE 1 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_WRITE 2 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_ULPM 3 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_READ 4 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE1_STATE, \ + DSI_MCTL_LANE_STS_DATLANE1_STATE_##__x) +#define DSI_MCTL_LANE_STS_DATLANE1_STATE(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE1_STATE, __x) +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_SHIFT 5 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_MASK 0x00000060 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_START 0 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_IDLE 1 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_WRITE 2 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_ULPM 3 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE2_STATE, \ + DSI_MCTL_LANE_STS_DATLANE2_STATE_##__x) +#define DSI_MCTL_LANE_STS_DATLANE2_STATE(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE2_STATE, __x) +#define DSI_MCTL_DPHY_TIMEOUT 0x00000014 +#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0 +#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_MASK 0x0000000F +#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, CLK_DIV, __x) +#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT 4 +#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_MASK 0x0003FFF0 +#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, HSTX_TO_VAL, __x) +#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT 18 +#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_MASK 0xFFFC0000 +#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, LPRX_TO_VAL, __x) +#define DSI_MCTL_ULPOUT_TIME 0x00000018 +#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT 0 +#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_MASK 0x000001FF +#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME(__x) \ + DSI_VAL2REG(DSI_MCTL_ULPOUT_TIME, CKLANE_ULPOUT_TIME, __x) +#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT 9 +#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_MASK 0x0003FE00 +#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME(__x) \ + DSI_VAL2REG(DSI_MCTL_ULPOUT_TIME, DATA_ULPOUT_TIME, __x) +#define DSI_MCTL_DPHY_STATIC 0x0000001C +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT 0 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK_MASK 0x00000001 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_CLK, __x) +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT 1 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK_MASK 0x00000002 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_CLK, __x) +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT 2 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1_MASK 0x00000004 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_DAT1, __x) +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT 3 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1_MASK 0x00000008 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_DAT1, __x) +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT 4 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2_MASK 0x00000010 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_DAT2, __x) +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT 5 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2_MASK 0x00000020 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_DAT2, __x) +#define DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT 6 +#define DSI_MCTL_DPHY_STATIC_UI_X4_MASK 0x00000FC0 +#define DSI_MCTL_DPHY_STATIC_UI_X4(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, UI_X4, __x) +#define DSI_MCTL_MAIN_EN 0x00000020 +#define DSI_MCTL_MAIN_EN_PLL_START_SHIFT 0 +#define DSI_MCTL_MAIN_EN_PLL_START_MASK 0x00000001 +#define DSI_MCTL_MAIN_EN_PLL_START(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, PLL_START, __x) +#define DSI_MCTL_MAIN_EN_CKLANE_EN_SHIFT 3 +#define DSI_MCTL_MAIN_EN_CKLANE_EN_MASK 0x00000008 +#define DSI_MCTL_MAIN_EN_CKLANE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, CKLANE_EN, __x) +#define DSI_MCTL_MAIN_EN_DAT1_EN_SHIFT 4 +#define DSI_MCTL_MAIN_EN_DAT1_EN_MASK 0x00000010 +#define DSI_MCTL_MAIN_EN_DAT1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT1_EN, __x) +#define DSI_MCTL_MAIN_EN_DAT2_EN_SHIFT 5 +#define DSI_MCTL_MAIN_EN_DAT2_EN_MASK 0x00000020 +#define DSI_MCTL_MAIN_EN_DAT2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT2_EN, __x) +#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ_SHIFT 6 +#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ_MASK 0x00000040 +#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, CLKLANE_ULPM_REQ, __x) +#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ_SHIFT 7 +#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ_MASK 0x00000080 +#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT1_ULPM_REQ, __x) +#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ_SHIFT 8 +#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ_MASK 0x00000100 +#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT2_ULPM_REQ, __x) +#define DSI_MCTL_MAIN_EN_IF1_EN_SHIFT 9 +#define DSI_MCTL_MAIN_EN_IF1_EN_MASK 0x00000200 +#define DSI_MCTL_MAIN_EN_IF1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, IF1_EN, __x) +#define DSI_MCTL_MAIN_EN_IF2_EN_SHIFT 10 +#define DSI_MCTL_MAIN_EN_IF2_EN_MASK 0x00000400 +#define DSI_MCTL_MAIN_EN_IF2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, IF2_EN, __x) +#define DSI_MCTL_MAIN_STS 0x00000024 +#define DSI_MCTL_MAIN_STS_PLL_LOCK_SHIFT 0 +#define DSI_MCTL_MAIN_STS_PLL_LOCK_MASK 0x00000001 +#define DSI_MCTL_MAIN_STS_PLL_LOCK(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, PLL_LOCK, __x) +#define DSI_MCTL_MAIN_STS_CLKLANE_READY_SHIFT 1 +#define DSI_MCTL_MAIN_STS_CLKLANE_READY_MASK 0x00000002 +#define DSI_MCTL_MAIN_STS_CLKLANE_READY(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, CLKLANE_READY, __x) +#define DSI_MCTL_MAIN_STS_DAT1_READY_SHIFT 2 +#define DSI_MCTL_MAIN_STS_DAT1_READY_MASK 0x00000004 +#define DSI_MCTL_MAIN_STS_DAT1_READY(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, DAT1_READY, __x) +#define DSI_MCTL_MAIN_STS_DAT2_READY_SHIFT 3 +#define DSI_MCTL_MAIN_STS_DAT2_READY_MASK 0x00000008 +#define DSI_MCTL_MAIN_STS_DAT2_READY(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, DAT2_READY, __x) +#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_SHIFT 4 +#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_MASK 0x00000010 +#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, HSTX_TO_ERR, __x) +#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_SHIFT 5 +#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_MASK 0x00000020 +#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, LPRX_TO_ERR, __x) +#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_SHIFT 6 +#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_MASK 0x00000040 +#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, CRS_UNTERM_PCK, __x) +#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_SHIFT 7 +#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_MASK 0x00000080 +#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, VRS_UNTERM_PCK, __x) +#define DSI_MCTL_DPHY_ERR 0x00000028 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_1_SHIFT 6 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_1_MASK 0x00000040 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_ESC_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_ESC_2_SHIFT 7 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_2_MASK 0x00000080 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_ESC_2, __x) +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1_SHIFT 8 +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1_MASK 0x00000100 +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_SYNCESC_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2_SHIFT 9 +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2_MASK 0x00000200 +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_SYNCESC_2, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1_SHIFT 10 +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1_MASK 0x00000400 +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONTROL_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2_SHIFT 11 +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2_MASK 0x00000800 +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONTROL_2, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1_SHIFT 12 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1_MASK 0x00001000 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP0_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2_SHIFT 13 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2_MASK 0x00002000 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP0_2, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1_SHIFT 14 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1_MASK 0x00004000 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP1_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2_SHIFT 15 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2_MASK 0x00008000 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP1_2, __x) +#define DSI_INT_VID_RDDATA 0x00000030 +#define DSI_INT_VID_RDDATA_IF_DATA_SHIFT 0 +#define DSI_INT_VID_RDDATA_IF_DATA_MASK 0x0000FFFF +#define DSI_INT_VID_RDDATA_IF_DATA(__x) \ + DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_DATA, __x) +#define DSI_INT_VID_RDDATA_IF_VALID_SHIFT 16 +#define DSI_INT_VID_RDDATA_IF_VALID_MASK 0x00010000 +#define DSI_INT_VID_RDDATA_IF_VALID(__x) \ + DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_VALID, __x) +#define DSI_INT_VID_RDDATA_IF_START_SHIFT 17 +#define DSI_INT_VID_RDDATA_IF_START_MASK 0x00020000 +#define DSI_INT_VID_RDDATA_IF_START(__x) \ + DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_START, __x) +#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC_SHIFT 18 +#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC_MASK 0x00040000 +#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC(__x) \ + DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_FRAME_SYNC, __x) +#define DSI_INT_VID_GNT 0x00000034 +#define DSI_INT_VID_GNT_IF_STALL_SHIFT 0 +#define DSI_INT_VID_GNT_IF_STALL_MASK 0x00000001 +#define DSI_INT_VID_GNT_IF_STALL(__x) \ + DSI_VAL2REG(DSI_INT_VID_GNT, IF_STALL, __x) +#define DSI_INT_CMD_RDDATA 0x00000038 +#define DSI_INT_CMD_RDDATA_IF_DATA_SHIFT 0 +#define DSI_INT_CMD_RDDATA_IF_DATA_MASK 0x0000FFFF +#define DSI_INT_CMD_RDDATA_IF_DATA(__x) \ + DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_DATA, __x) +#define DSI_INT_CMD_RDDATA_IF_VALID_SHIFT 16 +#define DSI_INT_CMD_RDDATA_IF_VALID_MASK 0x00010000 +#define DSI_INT_CMD_RDDATA_IF_VALID(__x) \ + DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_VALID, __x) +#define DSI_INT_CMD_RDDATA_IF_START_SHIFT 17 +#define DSI_INT_CMD_RDDATA_IF_START_MASK 0x00020000 +#define DSI_INT_CMD_RDDATA_IF_START(__x) \ + DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_START, __x) +#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC_SHIFT 18 +#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC_MASK 0x00040000 +#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC(__x) \ + DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_FRAME_SYNC, __x) +#define DSI_INT_CMD_GNT 0x0000003C +#define DSI_INT_CMD_GNT_IF_STALL_SHIFT 0 +#define DSI_INT_CMD_GNT_IF_STALL_MASK 0x00000001 +#define DSI_INT_CMD_GNT_IF_STALL(__x) \ + DSI_VAL2REG(DSI_INT_CMD_GNT, IF_STALL, __x) +#define DSI_INT_INTERRUPT_CTL 0x00000040 +#define DSI_INT_INTERRUPT_CTL_INT_VAL_SHIFT 0 +#define DSI_INT_INTERRUPT_CTL_INT_VAL_MASK 0x00000001 +#define DSI_INT_INTERRUPT_CTL_INT_VAL(__x) \ + DSI_VAL2REG(DSI_INT_INTERRUPT_CTL, INT_VAL, __x) +#define DSI_CMD_MODE_CTL 0x00000050 +#define DSI_CMD_MODE_CTL_IF1_ID_SHIFT 0 +#define DSI_CMD_MODE_CTL_IF1_ID_MASK 0x00000003 +#define DSI_CMD_MODE_CTL_IF1_ID(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, IF1_ID, __x) +#define DSI_CMD_MODE_CTL_IF2_ID_SHIFT 2 +#define DSI_CMD_MODE_CTL_IF2_ID_MASK 0x0000000C +#define DSI_CMD_MODE_CTL_IF2_ID(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, IF2_ID, __x) +#define DSI_CMD_MODE_CTL_IF1_LP_EN_SHIFT 4 +#define DSI_CMD_MODE_CTL_IF1_LP_EN_MASK 0x00000010 +#define DSI_CMD_MODE_CTL_IF1_LP_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, IF1_LP_EN, __x) +#define DSI_CMD_MODE_CTL_IF2_LP_EN_SHIFT 5 +#define DSI_CMD_MODE_CTL_IF2_LP_EN_MASK 0x00000020 +#define DSI_CMD_MODE_CTL_IF2_LP_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, IF2_LP_EN, __x) +#define DSI_CMD_MODE_CTL_ARB_MODE_SHIFT 6 +#define DSI_CMD_MODE_CTL_ARB_MODE_MASK 0x00000040 +#define DSI_CMD_MODE_CTL_ARB_MODE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, ARB_MODE, __x) +#define DSI_CMD_MODE_CTL_ARB_PRI_SHIFT 7 +#define DSI_CMD_MODE_CTL_ARB_PRI_MASK 0x00000080 +#define DSI_CMD_MODE_CTL_ARB_PRI(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, ARB_PRI, __x) +#define DSI_CMD_MODE_CTL_FIL_VALUE_SHIFT 8 +#define DSI_CMD_MODE_CTL_FIL_VALUE_MASK 0x0000FF00 +#define DSI_CMD_MODE_CTL_FIL_VALUE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, FIL_VALUE, __x) +#define DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT 16 +#define DSI_CMD_MODE_CTL_TE_TIMEOUT_MASK 0x03FF0000 +#define DSI_CMD_MODE_CTL_TE_TIMEOUT(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, TE_TIMEOUT, __x) +#define DSI_CMD_MODE_STS 0x00000054 +#define DSI_CMD_MODE_STS_ERR_NO_TE_SHIFT 0 +#define DSI_CMD_MODE_STS_ERR_NO_TE_MASK 0x00000001 +#define DSI_CMD_MODE_STS_ERR_NO_TE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_NO_TE, __x) +#define DSI_CMD_MODE_STS_ERR_TE_MISS_SHIFT 1 +#define DSI_CMD_MODE_STS_ERR_TE_MISS_MASK 0x00000002 +#define DSI_CMD_MODE_STS_ERR_TE_MISS(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_TE_MISS, __x) +#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN_SHIFT 2 +#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN_MASK 0x00000004 +#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_SDI1_UNDERRUN, __x) +#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN_SHIFT 3 +#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN_MASK 0x00000008 +#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_SDI2_UNDERRUN, __x) +#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD_SHIFT 4 +#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD_MASK 0x00000010 +#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_UNWANTED_RD, __x) +#define DSI_CMD_MODE_STS_CSM_RUNNING_SHIFT 5 +#define DSI_CMD_MODE_STS_CSM_RUNNING_MASK 0x00000020 +#define DSI_CMD_MODE_STS_CSM_RUNNING(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, CSM_RUNNING, __x) +#define DSI_DIRECT_CMD_SEND 0x00000060 +#define DSI_DIRECT_CMD_SEND_START_SHIFT 0 +#define DSI_DIRECT_CMD_SEND_START_MASK 0xFFFFFFFF +#define DSI_DIRECT_CMD_SEND_START(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_SEND, START, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS 0x00000064 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_SHIFT 0 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_MASK 0x00000007 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE 0 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ 1 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ 4 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TRIG_REQ 5 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_BTA_REQ 6 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_ENUM(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_NAT, \ + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_##__x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_NAT, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT_SHIFT 3 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT_MASK 0x00000008 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_LONGNOTSHORT, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT 8 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_MASK 0x00003F00 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_0 5 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_1 21 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_LONG_WRITE 57 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_READ 6 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_HEAD, \ + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_##__x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_HEAD, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT 14 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_MASK 0x0000C000 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_ID, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT 16 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_MASK 0x001F0000 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_SIZE, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN_SHIFT 21 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN_MASK 0x00200000 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_LP_EN, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_SHIFT 24 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_MASK 0x0F000000 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, TRIGGER_VAL, __x) +#define DSI_DIRECT_CMD_STS 0x00000068 +#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION_SHIFT 0 +#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION_MASK 0x00000001 +#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, CMD_TRANSMISSION, __x) +#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED_SHIFT 1 +#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED_MASK 0x00000002 +#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, WRITE_COMPLETED, __x) +#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED_SHIFT 2 +#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED_MASK 0x00000004 +#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_COMPLETED, __x) +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_SHIFT 3 +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_MASK 0x00000008 +#define DSI_DIRECT_CMD_STS_READ_COMPLETED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, READ_COMPLETED, __x) +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_SHIFT 4 +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_MASK 0x00000010 +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACKNOWLEDGE_RECEIVED, __x) +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED_SHIFT 5 +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED_MASK 0x00000020 +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACKNOWLEDGE_WITH_ERR_RECEIVED, __x) +#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED_SHIFT 6 +#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED_MASK 0x00000040 +#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_RECEIVED, __x) +#define DSI_DIRECT_CMD_STS_TE_RECEIVED_SHIFT 7 +#define DSI_DIRECT_CMD_STS_TE_RECEIVED_MASK 0x00000080 +#define DSI_DIRECT_CMD_STS_TE_RECEIVED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, TE_RECEIVED, __x) +#define DSI_DIRECT_CMD_STS_BTA_COMPLETED_SHIFT 8 +#define DSI_DIRECT_CMD_STS_BTA_COMPLETED_MASK 0x00000100 +#define DSI_DIRECT_CMD_STS_BTA_COMPLETED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, BTA_COMPLETED, __x) +#define DSI_DIRECT_CMD_STS_BTA_FINISHED_SHIFT 9 +#define DSI_DIRECT_CMD_STS_BTA_FINISHED_MASK 0x00000200 +#define DSI_DIRECT_CMD_STS_BTA_FINISHED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, BTA_FINISHED, __x) +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR_SHIFT 10 +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR_MASK 0x00000400 +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, READ_COMPLETED_WITH_ERR, __x) +#define DSI_DIRECT_CMD_STS_TRIGGER_VAL_SHIFT 11 +#define DSI_DIRECT_CMD_STS_TRIGGER_VAL_MASK 0x00007800 +#define DSI_DIRECT_CMD_STS_TRIGGER_VAL(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_VAL, __x) +#define DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT 16 +#define DSI_DIRECT_CMD_STS_ACK_VAL_MASK 0xFFFF0000 +#define DSI_DIRECT_CMD_STS_ACK_VAL(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACK_VAL, __x) +#define DSI_DIRECT_CMD_RD_INIT 0x0000006C +#define DSI_DIRECT_CMD_RD_INIT_RESET_SHIFT 0 +#define DSI_DIRECT_CMD_RD_INIT_RESET_MASK 0xFFFFFFFF +#define DSI_DIRECT_CMD_RD_INIT_RESET(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_INIT, RESET, __x) +#define DSI_DIRECT_CMD_WRDAT0 0x00000070 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT0_SHIFT 0 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT0_MASK 0x000000FF +#define DSI_DIRECT_CMD_WRDAT0_WRDAT0(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT0, __x) +#define DSI_DIRECT_CMD_WRDAT0_WRDAT1_SHIFT 8 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT1_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT1(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT1, __x) +#define DSI_DIRECT_CMD_WRDAT0_WRDAT2_SHIFT 16 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT2_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT2(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT2, __x) +#define DSI_DIRECT_CMD_WRDAT0_WRDAT3_SHIFT 24 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT3_MASK 0xFF000000 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT3(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT3, __x) +#define DSI_DIRECT_CMD_WRDAT1 0x00000074 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT4_SHIFT 0 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT4_MASK 0x000000FF +#define DSI_DIRECT_CMD_WRDAT1_WRDAT4(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT4, __x) +#define DSI_DIRECT_CMD_WRDAT1_WRDAT5_SHIFT 8 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT5_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT5(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT5, __x) +#define DSI_DIRECT_CMD_WRDAT1_WRDAT6_SHIFT 16 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT6_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT6(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT6, __x) +#define DSI_DIRECT_CMD_WRDAT1_WRDAT7_SHIFT 24 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT7_MASK 0xFF000000 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT7(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT7, __x) +#define DSI_DIRECT_CMD_WRDAT2 0x00000078 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT8_SHIFT 0 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT8_MASK 0x000000FF +#define DSI_DIRECT_CMD_WRDAT2_WRDAT8(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT8, __x) +#define DSI_DIRECT_CMD_WRDAT2_WRDAT9_SHIFT 8 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT9_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT9(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT9, __x) +#define DSI_DIRECT_CMD_WRDAT2_WRDAT10_SHIFT 16 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT10_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT10(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT10, __x) +#define DSI_DIRECT_CMD_WRDAT2_WRDAT11_SHIFT 24 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT11_MASK 0xFF000000 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT11(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT11, __x) +#define DSI_DIRECT_CMD_WRDAT3 0x0000007C +#define DSI_DIRECT_CMD_WRDAT3_WRDAT12_SHIFT 0 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT12_MASK 0x000000FF +#define DSI_DIRECT_CMD_WRDAT3_WRDAT12(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT12, __x) +#define DSI_DIRECT_CMD_WRDAT3_WRDAT13_SHIFT 8 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT13_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT13(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT13, __x) +#define DSI_DIRECT_CMD_WRDAT3_WRDAT14_SHIFT 16 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT14_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT14(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT14, __x) +#define DSI_DIRECT_CMD_WRDAT3_WRDAT15_SHIFT 24 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT15_MASK 0xFF000000 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT15(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT15, __x) +#define DSI_DIRECT_CMD_RDDAT 0x00000080 +#define DSI_DIRECT_CMD_RDDAT_RDDAT0_SHIFT 0 +#define DSI_DIRECT_CMD_RDDAT_RDDAT0_MASK 0x000000FF +#define DSI_DIRECT_CMD_RDDAT_RDDAT0(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT0, __x) +#define DSI_DIRECT_CMD_RDDAT_RDDAT1_SHIFT 8 +#define DSI_DIRECT_CMD_RDDAT_RDDAT1_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_RDDAT_RDDAT1(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT1, __x) +#define DSI_DIRECT_CMD_RDDAT_RDDAT2_SHIFT 16 +#define DSI_DIRECT_CMD_RDDAT_RDDAT2_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_RDDAT_RDDAT2(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT2, __x) +#define DSI_DIRECT_CMD_RDDAT_RDDAT3_SHIFT 24 +#define DSI_DIRECT_CMD_RDDAT_RDDAT3_MASK 0xFF000000 +#define DSI_DIRECT_CMD_RDDAT_RDDAT3(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT3, __x) +#define DSI_DIRECT_CMD_RD_PROPERTY 0x00000084 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_SHIFT 0 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK 0x0000FFFF +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_SIZE, __x) +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_SHIFT 16 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_MASK 0x00030000 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_ID, __x) +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_SHIFT 18 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_MASK 0x00040000 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_DCSNOTGENERIC, __x) +#define DSI_DIRECT_CMD_RD_STS 0x00000088 +#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED_SHIFT 0 +#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED_MASK 0x00000001 +#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_FIXED, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE_SHIFT 1 +#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE_MASK 0x00000002 +#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_UNCORRECTABLE, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM_SHIFT 2 +#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM_MASK 0x00000004 +#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_CHECKSUM, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE_SHIFT 3 +#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE_MASK 0x00000008 +#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_UNDECODABLE, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE_SHIFT 4 +#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE_MASK 0x00000010 +#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_RECEIVE, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE_SHIFT 5 +#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE_MASK 0x00000020 +#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_OVERSIZE, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH_SHIFT 6 +#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH_MASK 0x00000040 +#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_WRONG_LENGTH, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT_SHIFT 7 +#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT_MASK 0x00000080 +#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_MISSING_EOT, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR_SHIFT 8 +#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR_MASK 0x00000100 +#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_EOT_WITH_ERR, __x) +#define DSI_VID_MAIN_CTL 0x00000090 +#define DSI_VID_MAIN_CTL_START_MODE_SHIFT 0 +#define DSI_VID_MAIN_CTL_START_MODE_MASK 0x00000003 +#define DSI_VID_MAIN_CTL_START_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, START_MODE, __x) +#define DSI_VID_MAIN_CTL_STOP_MODE_SHIFT 2 +#define DSI_VID_MAIN_CTL_STOP_MODE_MASK 0x0000000C +#define DSI_VID_MAIN_CTL_STOP_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, STOP_MODE, __x) +#define DSI_VID_MAIN_CTL_VID_ID_SHIFT 4 +#define DSI_VID_MAIN_CTL_VID_ID_MASK 0x00000030 +#define DSI_VID_MAIN_CTL_VID_ID(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_ID, __x) +#define DSI_VID_MAIN_CTL_HEADER_SHIFT 6 +#define DSI_VID_MAIN_CTL_HEADER_MASK 0x00000FC0 +#define DSI_VID_MAIN_CTL_HEADER(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, HEADER, __x) +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_SHIFT 12 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_MASK 0x00003000 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS 0 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS 1 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE 2 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS 3 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_PIXEL_MODE, \ + DSI_VID_MAIN_CTL_VID_PIXEL_MODE_##__x) +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_PIXEL_MODE, __x) +#define DSI_VID_MAIN_CTL_BURST_MODE_SHIFT 14 +#define DSI_VID_MAIN_CTL_BURST_MODE_MASK 0x00004000 +#define DSI_VID_MAIN_CTL_BURST_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, BURST_MODE, __x) +#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE_SHIFT 15 +#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE_MASK 0x00008000 +#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, SYNC_PULSE_ACTIVE, __x) +#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL_SHIFT 16 +#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL_MASK 0x00010000 +#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, SYNC_PULSE_HORIZONTAL, __x) +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_SHIFT 17 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_MASK 0x00060000 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_NULL 0 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING 1 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0 2 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 3 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKLINE_MODE, \ + DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_##__x) +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKLINE_MODE, __x) +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_SHIFT 19 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_MASK 0x00180000 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_NULL 0 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_BLANKING 1 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 2 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_1 3 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKEOL_MODE, \ + DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_##__x) +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKEOL_MODE, __x) +#define DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT 21 +#define DSI_VID_MAIN_CTL_RECOVERY_MODE_MASK 0x00600000 +#define DSI_VID_MAIN_CTL_RECOVERY_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, RECOVERY_MODE, __x) +#define DSI_VID_VSIZE 0x00000094 +#define DSI_VID_VSIZE_VSA_LENGTH_SHIFT 0 +#define DSI_VID_VSIZE_VSA_LENGTH_MASK 0x0000003F +#define DSI_VID_VSIZE_VSA_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_VSIZE, VSA_LENGTH, __x) +#define DSI_VID_VSIZE_VBP_LENGTH_SHIFT 6 +#define DSI_VID_VSIZE_VBP_LENGTH_MASK 0x00000FC0 +#define DSI_VID_VSIZE_VBP_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_VSIZE, VBP_LENGTH, __x) +#define DSI_VID_VSIZE_VFP_LENGTH_SHIFT 12 +#define DSI_VID_VSIZE_VFP_LENGTH_MASK 0x000FF000 +#define DSI_VID_VSIZE_VFP_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_VSIZE, VFP_LENGTH, __x) +#define DSI_VID_VSIZE_VACT_LENGTH_SHIFT 20 +#define DSI_VID_VSIZE_VACT_LENGTH_MASK 0x7FF00000 +#define DSI_VID_VSIZE_VACT_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_VSIZE, VACT_LENGTH, __x) +#define DSI_VID_HSIZE1 0x00000098 +#define DSI_VID_HSIZE1_HSA_LENGTH_SHIFT 0 +#define DSI_VID_HSIZE1_HSA_LENGTH_MASK 0x000003FF +#define DSI_VID_HSIZE1_HSA_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_HSIZE1, HSA_LENGTH, __x) +#define DSI_VID_HSIZE1_HBP_LENGTH_SHIFT 10 +#define DSI_VID_HSIZE1_HBP_LENGTH_MASK 0x000FFC00 +#define DSI_VID_HSIZE1_HBP_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_HSIZE1, HBP_LENGTH, __x) +#define DSI_VID_HSIZE1_HFP_LENGTH_SHIFT 20 +#define DSI_VID_HSIZE1_HFP_LENGTH_MASK 0x7FF00000 +#define DSI_VID_HSIZE1_HFP_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_HSIZE1, HFP_LENGTH, __x) +#define DSI_VID_HSIZE2 0x0000009C +#define DSI_VID_HSIZE2_RGB_SIZE_SHIFT 0 +#define DSI_VID_HSIZE2_RGB_SIZE_MASK 0x00001FFF +#define DSI_VID_HSIZE2_RGB_SIZE(__x) \ + DSI_VAL2REG(DSI_VID_HSIZE2, RGB_SIZE, __x) +#define DSI_VID_BLKSIZE1 0x000000A0 +#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT 0 +#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK 0x00001FFF +#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK(__x) \ + DSI_VAL2REG(DSI_VID_BLKSIZE1, BLKLINE_EVENT_PCK, __x) +#define DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT 13 +#define DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK 0x03FFE000 +#define DSI_VID_BLKSIZE1_BLKEOL_PCK(__x) \ + DSI_VAL2REG(DSI_VID_BLKSIZE1, BLKEOL_PCK, __x) +#define DSI_VID_BLKSIZE2 0x000000A4 +#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT 0 +#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_MASK 0x00001FFF +#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK(__x) \ + DSI_VAL2REG(DSI_VID_BLKSIZE2, BLKLINE_PULSE_PCK, __x) +#define DSI_VID_PCK_TIME 0x000000A8 +#define DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT 0 +#define DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK 0x00001FFF +#define DSI_VID_PCK_TIME_BLKEOL_DURATION(__x) \ + DSI_VAL2REG(DSI_VID_PCK_TIME, BLKEOL_DURATION, __x) +#define DSI_VID_DPHY_TIME 0x000000AC +#define DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT 0 +#define DSI_VID_DPHY_TIME_REG_LINE_DURATION_MASK 0x00001FFF +#define DSI_VID_DPHY_TIME_REG_LINE_DURATION(__x) \ + DSI_VAL2REG(DSI_VID_DPHY_TIME, REG_LINE_DURATION, __x) +#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT 13 +#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_MASK 0x00FFE000 +#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME(__x) \ + DSI_VAL2REG(DSI_VID_DPHY_TIME, REG_WAKEUP_TIME, __x) +#define DSI_VID_ERR_COLOR 0x000000B0 +#define DSI_VID_ERR_COLOR_COL_RED_SHIFT 0 +#define DSI_VID_ERR_COLOR_COL_RED_MASK 0x000000FF +#define DSI_VID_ERR_COLOR_COL_RED(__x) \ + DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_RED, __x) +#define DSI_VID_ERR_COLOR_COL_GREEN_SHIFT 8 +#define DSI_VID_ERR_COLOR_COL_GREEN_MASK 0x0000FF00 +#define DSI_VID_ERR_COLOR_COL_GREEN(__x) \ + DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_GREEN, __x) +#define DSI_VID_ERR_COLOR_COL_BLUE_SHIFT 16 +#define DSI_VID_ERR_COLOR_COL_BLUE_MASK 0x00FF0000 +#define DSI_VID_ERR_COLOR_COL_BLUE(__x) \ + DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_BLUE, __x) +#define DSI_VID_ERR_COLOR_PAD_VAL_SHIFT 24 +#define DSI_VID_ERR_COLOR_PAD_VAL_MASK 0xFF000000 +#define DSI_VID_ERR_COLOR_PAD_VAL(__x) \ + DSI_VAL2REG(DSI_VID_ERR_COLOR, PAD_VAL, __x) +#define DSI_VID_VPOS 0x000000B4 +#define DSI_VID_VPOS_LINE_POS_SHIFT 0 +#define DSI_VID_VPOS_LINE_POS_MASK 0x00000003 +#define DSI_VID_VPOS_LINE_POS(__x) \ + DSI_VAL2REG(DSI_VID_VPOS, LINE_POS, __x) +#define DSI_VID_VPOS_LINE_VAL_SHIFT 2 +#define DSI_VID_VPOS_LINE_VAL_MASK 0x00001FFC +#define DSI_VID_VPOS_LINE_VAL(__x) \ + DSI_VAL2REG(DSI_VID_VPOS, LINE_VAL, __x) +#define DSI_VID_HPOS 0x000000B8 +#define DSI_VID_HPOS_HORIZONTAL_POS_SHIFT 0 +#define DSI_VID_HPOS_HORIZONTAL_POS_MASK 0x00000007 +#define DSI_VID_HPOS_HORIZONTAL_POS(__x) \ + DSI_VAL2REG(DSI_VID_HPOS, HORIZONTAL_POS, __x) +#define DSI_VID_HPOS_HORIZONTAL_VAL_SHIFT 3 +#define DSI_VID_HPOS_HORIZONTAL_VAL_MASK 0x0000FFF8 +#define DSI_VID_HPOS_HORIZONTAL_VAL(__x) \ + DSI_VAL2REG(DSI_VID_HPOS, HORIZONTAL_VAL, __x) +#define DSI_VID_MODE_STS 0x000000BC +#define DSI_VID_MODE_STS_VSG_RUNNING_SHIFT 0 +#define DSI_VID_MODE_STS_VSG_RUNNING_MASK 0x00000001 +#define DSI_VID_MODE_STS_VSG_RUNNING(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, VSG_RUNNING, __x) +#define DSI_VID_MODE_STS_ERR_MISSING_DATA_SHIFT 1 +#define DSI_VID_MODE_STS_ERR_MISSING_DATA_MASK 0x00000002 +#define DSI_VID_MODE_STS_ERR_MISSING_DATA(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_DATA, __x) +#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC_SHIFT 2 +#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC_MASK 0x00000004 +#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_HSYNC, __x) +#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC_SHIFT 3 +#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC_MASK 0x00000008 +#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_VSYNC, __x) +#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH_SHIFT 4 +#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH_MASK 0x00000010 +#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, REG_ERR_SMALL_LENGTH, __x) +#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT_SHIFT 5 +#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT_MASK 0x00000020 +#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, REG_ERR_SMALL_HEIGHT, __x) +#define DSI_VID_MODE_STS_ERR_BURSTWRITE_SHIFT 6 +#define DSI_VID_MODE_STS_ERR_BURSTWRITE_MASK 0x00000040 +#define DSI_VID_MODE_STS_ERR_BURSTWRITE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_BURSTWRITE, __x) +#define DSI_VID_MODE_STS_ERR_LONGWRITE_SHIFT 7 +#define DSI_VID_MODE_STS_ERR_LONGWRITE_MASK 0x00000080 +#define DSI_VID_MODE_STS_ERR_LONGWRITE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_LONGWRITE, __x) +#define DSI_VID_MODE_STS_ERR_LONGREAD_SHIFT 8 +#define DSI_VID_MODE_STS_ERR_LONGREAD_MASK 0x00000100 +#define DSI_VID_MODE_STS_ERR_LONGREAD(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_LONGREAD, __x) +#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH_SHIFT 9 +#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH_MASK 0x00000200 +#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_VRS_WRONG_LENGTH, __x) +#define DSI_VID_MODE_STS_VSG_RECOVERY_SHIFT 10 +#define DSI_VID_MODE_STS_VSG_RECOVERY_MASK 0x00000400 +#define DSI_VID_MODE_STS_VSG_RECOVERY(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, VSG_RECOVERY, __x) +#define DSI_VID_VCA_SETTING1 0x000000C0 +#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT 0 +#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK 0x0000FFFF +#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT(__x) \ + DSI_VAL2REG(DSI_VID_VCA_SETTING1, MAX_BURST_LIMIT, __x) +#define DSI_VID_VCA_SETTING1_BURST_LP_SHIFT 16 +#define DSI_VID_VCA_SETTING1_BURST_LP_MASK 0x00010000 +#define DSI_VID_VCA_SETTING1_BURST_LP(__x) \ + DSI_VAL2REG(DSI_VID_VCA_SETTING1, BURST_LP, __x) +#define DSI_VID_VCA_SETTING2 0x000000C4 +#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT 0 +#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK 0x0000FFFF +#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT(__x) \ + DSI_VAL2REG(DSI_VID_VCA_SETTING2, EXACT_BURST_LIMIT, __x) +#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT 16 +#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK 0xFFFF0000 +#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT(__x) \ + DSI_VAL2REG(DSI_VID_VCA_SETTING2, MAX_LINE_LIMIT, __x) +#define DSI_TVG_CTL 0x000000C8 +#define DSI_TVG_CTL_TVG_RUN_SHIFT 0 +#define DSI_TVG_CTL_TVG_RUN_MASK 0x00000001 +#define DSI_TVG_CTL_TVG_RUN(__x) \ + DSI_VAL2REG(DSI_TVG_CTL, TVG_RUN, __x) +#define DSI_TVG_CTL_TVG_STOPMODE_SHIFT 1 +#define DSI_TVG_CTL_TVG_STOPMODE_MASK 0x00000006 +#define DSI_TVG_CTL_TVG_STOPMODE(__x) \ + DSI_VAL2REG(DSI_TVG_CTL, TVG_STOPMODE, __x) +#define DSI_TVG_CTL_TVG_MODE_SHIFT 3 +#define DSI_TVG_CTL_TVG_MODE_MASK 0x00000018 +#define DSI_TVG_CTL_TVG_MODE(__x) \ + DSI_VAL2REG(DSI_TVG_CTL, TVG_MODE, __x) +#define DSI_TVG_CTL_TVG_STRIPE_SIZE_SHIFT 5 +#define DSI_TVG_CTL_TVG_STRIPE_SIZE_MASK 0x000000E0 +#define DSI_TVG_CTL_TVG_STRIPE_SIZE(__x) \ + DSI_VAL2REG(DSI_TVG_CTL, TVG_STRIPE_SIZE, __x) +#define DSI_TVG_IMG_SIZE 0x000000CC +#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE_SHIFT 0 +#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE_MASK 0x00001FFF +#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE(__x) \ + DSI_VAL2REG(DSI_TVG_IMG_SIZE, TVG_LINE_SIZE, __x) +#define DSI_TVG_IMG_SIZE_TVG_NBLINE_SHIFT 16 +#define DSI_TVG_IMG_SIZE_TVG_NBLINE_MASK 0x07FF0000 +#define DSI_TVG_IMG_SIZE_TVG_NBLINE(__x) \ + DSI_VAL2REG(DSI_TVG_IMG_SIZE, TVG_NBLINE, __x) +#define DSI_TVG_COLOR1 0x000000D0 +#define DSI_TVG_COLOR1_COL1_RED_SHIFT 0 +#define DSI_TVG_COLOR1_COL1_RED_MASK 0x000000FF +#define DSI_TVG_COLOR1_COL1_RED(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR1, COL1_RED, __x) +#define DSI_TVG_COLOR1_COL1_GREEN_SHIFT 8 +#define DSI_TVG_COLOR1_COL1_GREEN_MASK 0x0000FF00 +#define DSI_TVG_COLOR1_COL1_GREEN(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR1, COL1_GREEN, __x) +#define DSI_TVG_COLOR1_COL1_BLUE_SHIFT 16 +#define DSI_TVG_COLOR1_COL1_BLUE_MASK 0x00FF0000 +#define DSI_TVG_COLOR1_COL1_BLUE(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR1, COL1_BLUE, __x) +#define DSI_TVG_COLOR2 0x000000D4 +#define DSI_TVG_COLOR2_COL2_RED_SHIFT 0 +#define DSI_TVG_COLOR2_COL2_RED_MASK 0x000000FF +#define DSI_TVG_COLOR2_COL2_RED(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR2, COL2_RED, __x) +#define DSI_TVG_COLOR2_COL2_GREEN_SHIFT 8 +#define DSI_TVG_COLOR2_COL2_GREEN_MASK 0x0000FF00 +#define DSI_TVG_COLOR2_COL2_GREEN(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR2, COL2_GREEN, __x) +#define DSI_TVG_COLOR2_COL2_BLUE_SHIFT 16 +#define DSI_TVG_COLOR2_COL2_BLUE_MASK 0x00FF0000 +#define DSI_TVG_COLOR2_COL2_BLUE(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR2, COL2_BLUE, __x) +#define DSI_TVG_STS 0x000000D8 +#define DSI_TVG_STS_TVG_RUNNING_SHIFT 0 +#define DSI_TVG_STS_TVG_RUNNING_MASK 0x00000001 +#define DSI_TVG_STS_TVG_RUNNING(__x) \ + DSI_VAL2REG(DSI_TVG_STS, TVG_RUNNING, __x) +#define DSI_TBG_CTL 0x000000E0 +#define DSI_TBG_CTL_TBG_START_SHIFT 0 +#define DSI_TBG_CTL_TBG_START_MASK 0x00000001 +#define DSI_TBG_CTL_TBG_START(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_START, __x) +#define DSI_TBG_CTL_TBG_HS_REQ_SHIFT 1 +#define DSI_TBG_CTL_TBG_HS_REQ_MASK 0x00000002 +#define DSI_TBG_CTL_TBG_HS_REQ(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_HS_REQ, __x) +#define DSI_TBG_CTL_TBG_DATA_SEL_SHIFT 2 +#define DSI_TBG_CTL_TBG_DATA_SEL_MASK 0x00000004 +#define DSI_TBG_CTL_TBG_DATA_SEL(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_DATA_SEL, __x) +#define DSI_TBG_CTL_TBG_MODE_SHIFT 3 +#define DSI_TBG_CTL_TBG_MODE_MASK 0x00000018 +#define DSI_TBG_CTL_TBG_MODE_1BYTE 0 +#define DSI_TBG_CTL_TBG_MODE_2BYTE 1 +#define DSI_TBG_CTL_TBG_MODE_BURST_COUNTER 2 +#define DSI_TBG_CTL_TBG_MODE_BURST 3 +#define DSI_TBG_CTL_TBG_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_MODE, DSI_TBG_CTL_TBG_MODE_##__x) +#define DSI_TBG_CTL_TBG_MODE(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_MODE, __x) +#define DSI_TBG_SETTING 0x000000E4 +#define DSI_TBG_SETTING_TBG_DATA_SHIFT 0 +#define DSI_TBG_SETTING_TBG_DATA_MASK 0x0000FFFF +#define DSI_TBG_SETTING_TBG_DATA(__x) \ + DSI_VAL2REG(DSI_TBG_SETTING, TBG_DATA, __x) +#define DSI_TBG_SETTING_TBG_CPT_SHIFT 16 +#define DSI_TBG_SETTING_TBG_CPT_MASK 0x0FFF0000 +#define DSI_TBG_SETTING_TBG_CPT(__x) \ + DSI_VAL2REG(DSI_TBG_SETTING, TBG_CPT, __x) +#define DSI_TBG_STS 0x000000E8 +#define DSI_TBG_STS_TBG_STATUS_SHIFT 0 +#define DSI_TBG_STS_TBG_STATUS_MASK 0x00000001 +#define DSI_TBG_STS_TBG_STATUS(__x) \ + DSI_VAL2REG(DSI_TBG_STS, TBG_STATUS, __x) +#define DSI_MCTL_MAIN_STS_CTL 0x000000F0 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN_SHIFT 0 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN_MASK 0x00000001 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, PLL_LOCK_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN_SHIFT 1 +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN_MASK 0x00000002 +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CLKLANE_READY_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN_SHIFT 2 +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN_MASK 0x00000004 +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT1_READY_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN_SHIFT 3 +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN_MASK 0x00000008 +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT2_READY_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN_SHIFT 4 +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN_MASK 0x00000010 +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, HSTX_TO_ERR_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN_SHIFT 5 +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN_MASK 0x00000020 +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, LPRX_TO_ERR_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN_SHIFT 6 +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN_MASK 0x00000040 +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CRS_UNTERM_PCK_ERR_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN_SHIFT 7 +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN_MASK 0x00000080 +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, VRS_UNTERM_PCK_ERR_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE_SHIFT 16 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE_MASK 0x00010000 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, PLL_LOCK_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE_SHIFT 17 +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE_MASK 0x00020000 +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CLKLANE_READY_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE_SHIFT 18 +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE_MASK 0x00040000 +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT1_READY_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE_SHIFT 19 +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE_MASK 0x00080000 +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT2_READY_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE_SHIFT 20 +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE_MASK 0x00100000 +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, HSTX_TO_ERR_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE_SHIFT 21 +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE_MASK 0x00200000 +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, LPRX_TO_ERR_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE_SHIFT 22 +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE_MASK 0x00400000 +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CRS_UNTERM_PCK_ERR_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE_SHIFT 23 +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE_MASK 0x00800000 +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, VRS_UNTERM_PCK_ERR_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL 0x000000F4 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN_SHIFT 0 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN_MASK 0x00000001 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_NO_TE_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN_SHIFT 1 +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN_MASK 0x00000002 +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_TE_MISS_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN_SHIFT 2 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN_MASK 0x00000004 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI1_UNDERRUN_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN_SHIFT 3 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN_MASK 0x00000008 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI2_UNDERRUN_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN_SHIFT 4 +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN_MASK 0x00000010 +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_UNWANTED_RD_EN, __x) +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN_SHIFT 5 +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN_MASK 0x00000020 +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, CSM_RUNNING_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE_SHIFT 16 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE_MASK 0x00010000 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_NO_TE_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE_SHIFT 17 +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE_MASK 0x00020000 +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_TE_MISS_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE_SHIFT 18 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE_MASK 0x00040000 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI1_UNDERRUN_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE_SHIFT 19 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE_MASK 0x00080000 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI2_UNDERRUN_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE_SHIFT 20 +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE_MASK 0x00100000 +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_UNWANTED_RD_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE_SHIFT 21 +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE_MASK 0x00200000 +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, CSM_RUNNING_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL 0x000000F8 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN_SHIFT 0 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN_MASK 0x00000001 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, CMD_TRANSMISSION_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN_SHIFT 1 +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN_MASK 0x00000002 +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, WRITE_COMPLETED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN_SHIFT 2 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN_MASK 0x00000004 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_COMPLETED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN_SHIFT 3 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN_MASK 0x00000008 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN_SHIFT 4 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN_MASK 0x00000010 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_RECEIVED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN_SHIFT 5 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN_MASK 0x00000020 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_WITH_ERR_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN_SHIFT 6 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN_MASK 0x00000040 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_RECEIVED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN_SHIFT 7 +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN_MASK 0x00000080 +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TE_RECEIVED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN_SHIFT 8 +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN_MASK 0x00000100 +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_COMPLETED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN_SHIFT 9 +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN_MASK 0x00000200 +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_FINISHED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN_SHIFT 10 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN_MASK 0x00000400 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_WITH_ERR_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE_SHIFT 16 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE_MASK 0x00010000 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, CMD_TRANSMISSION_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE_SHIFT 17 +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE_MASK 0x00020000 +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, WRITE_COMPLETED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE_SHIFT 18 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE_MASK 0x00040000 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_COMPLETED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE_SHIFT 19 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE_MASK 0x00080000 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE_SHIFT 20 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE_MASK 0x00100000 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_RECEIVED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE_SHIFT 21 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE_MASK 0x00200000 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_WITH_ERR_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE_SHIFT 22 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE_MASK 0x00400000 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_RECEIVED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE_SHIFT 23 +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE_MASK 0x00800000 +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TE_RECEIVED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE_SHIFT 24 +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE_MASK 0x01000000 +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_COMPLETED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE_SHIFT 25 +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE_MASK 0x02000000 +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_FINISHED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE_SHIFT 26 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE_MASK 0x04000000 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_WITH_ERR_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL 0x000000FC +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN_SHIFT 0 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN_MASK 0x00000001 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_FIXED_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN_SHIFT 1 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN_MASK 0x00000002 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNCORRECTABLE_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN_SHIFT 2 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN_MASK 0x00000004 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_CHECKSUM_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN_SHIFT 3 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN_MASK 0x00000008 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNDECODABLE_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN_SHIFT 4 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN_MASK 0x00000010 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_RECEIVE_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN_SHIFT 5 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN_MASK 0x00000020 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_OVERSIZE_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN_SHIFT 6 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN_MASK 0x00000040 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_WRONG_LENGTH_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN_SHIFT 7 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN_MASK 0x00000080 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_MISSING_EOT_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN_SHIFT 8 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN_MASK 0x00000100 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_EOT_WITH_ERR_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE_SHIFT 16 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE_MASK 0x00010000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_FIXED_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE_SHIFT 17 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE_MASK 0x00020000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNCORRECTABLE_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE_SHIFT 18 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE_MASK 0x00040000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_CHECKSUM_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE_SHIFT 19 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE_MASK 0x00080000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNDECODABLE_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE_SHIFT 20 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE_MASK 0x00100000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_RECEIVE_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE_SHIFT 21 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE_MASK 0x00200000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_OVERSIZE_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE_SHIFT 22 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE_MASK 0x00400000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_WRONG_LENGTH_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE_SHIFT 23 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE_MASK 0x00800000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_MISSING_EOT_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE_SHIFT 24 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE_MASK 0x01000000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_EOT_WITH_ERR_EDGE, __x) +#define DSI_VID_MODE_STS_CTL 0x00000100 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN_SHIFT 0 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN_MASK 0x00000001 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RUNNING_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN_SHIFT 1 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN_MASK 0x00000002 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_DATA_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN_SHIFT 2 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN_MASK 0x00000004 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_HSYNC_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN_SHIFT 3 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN_MASK 0x00000008 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_VSYNC_EN, __x) +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN_SHIFT 4 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN_MASK 0x00000010 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_LENGTH_EN, __x) +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN_SHIFT 5 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN_MASK 0x00000020 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_HEIGHT_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN_SHIFT 6 +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN_MASK 0x00000040 +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_BURSTWRITE_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN_SHIFT 7 +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN_MASK 0x00000080 +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGWRITE_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN_SHIFT 8 +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN_MASK 0x00000100 +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGREAD_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN_SHIFT 9 +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN_MASK 0x00000200 +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_VRS_WRONG_LENGTH_EN, __x) +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE_SHIFT 16 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE_MASK 0x00010000 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RUNNING_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE_SHIFT 17 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE_MASK 0x00020000 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_DATA_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE_SHIFT 18 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE_MASK 0x00040000 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_HSYNC_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE_SHIFT 19 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE_MASK 0x00080000 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_VSYNC_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE_SHIFT 20 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE_MASK 0x00100000 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_LENGTH_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE_SHIFT 21 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE_MASK 0x00200000 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_HEIGHT_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE_SHIFT 22 +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE_MASK 0x00400000 +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_BURSTWRITE_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE_SHIFT 23 +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE_MASK 0x00800000 +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGWRITE_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE_SHIFT 24 +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE_MASK 0x01000000 +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGREAD_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE_SHIFT 25 +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE_MASK 0x02000000 +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_VRS_WRONG_LENGTH_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE_SHIFT 26 +#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE_MASK 0x04000000 +#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RECOVERY_EDGE, __x) +#define DSI_TG_STS_CTL 0x00000104 +#define DSI_TG_STS_CTL_TVG_STS_EN_SHIFT 0 +#define DSI_TG_STS_CTL_TVG_STS_EN_MASK 0x00000001 +#define DSI_TG_STS_CTL_TVG_STS_EN(__x) \ + DSI_VAL2REG(DSI_TG_STS_CTL, TVG_STS_EN, __x) +#define DSI_TG_STS_CTL_TBG_STS_EN_SHIFT 1 +#define DSI_TG_STS_CTL_TBG_STS_EN_MASK 0x00000002 +#define DSI_TG_STS_CTL_TBG_STS_EN(__x) \ + DSI_VAL2REG(DSI_TG_STS_CTL, TBG_STS_EN, __x) +#define DSI_TG_STS_CTL_TVG_STS_EDGE_SHIFT 16 +#define DSI_TG_STS_CTL_TVG_STS_EDGE_MASK 0x00010000 +#define DSI_TG_STS_CTL_TVG_STS_EDGE(__x) \ + DSI_VAL2REG(DSI_TG_STS_CTL, TVG_STS_EDGE, __x) +#define DSI_TG_STS_CTL_TBG_STS_EDGE_SHIFT 17 +#define DSI_TG_STS_CTL_TBG_STS_EDGE_MASK 0x00020000 +#define DSI_TG_STS_CTL_TBG_STS_EDGE(__x) \ + DSI_VAL2REG(DSI_TG_STS_CTL, TBG_STS_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL 0x00000108 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN_SHIFT 6 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN_MASK 0x00000040 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN_SHIFT 7 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN_MASK 0x00000080 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN_SHIFT 8 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN_MASK 0x00000100 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN_SHIFT 9 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN_MASK 0x00000200 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN_SHIFT 10 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN_MASK 0x00000400 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN_SHIFT 11 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN_MASK 0x00000800 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN_SHIFT 12 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN_MASK 0x00001000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN_SHIFT 13 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN_MASK 0x00002000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN_SHIFT 14 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN_MASK 0x00004000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN_SHIFT 15 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN_MASK 0x00008000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE_SHIFT 22 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE_MASK 0x00400000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE_SHIFT 23 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE_MASK 0x00800000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_2_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE_SHIFT 24 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE_MASK 0x01000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE_SHIFT 25 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE_MASK 0x02000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_2_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE_SHIFT 26 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE_MASK 0x04000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE_SHIFT 27 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE_MASK 0x08000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_2_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE_SHIFT 28 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE_MASK 0x10000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE_SHIFT 29 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE_MASK 0x20000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_2_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE_SHIFT 30 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE_MASK 0x40000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE_SHIFT 31 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE_MASK 0x80000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_2_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CLR 0x00000110 +#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR_SHIFT 0 +#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR_MASK 0x00000001 +#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, PLL_LOCK_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR_SHIFT 1 +#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR_MASK 0x00000002 +#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, CLKLANE_READY_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR_SHIFT 2 +#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR_MASK 0x00000004 +#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, DAT1_READY_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR_SHIFT 3 +#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR_MASK 0x00000008 +#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, DAT2_READY_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR_SHIFT 4 +#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR_MASK 0x00000010 +#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, HSTX_TO_ERR_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR_SHIFT 5 +#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR_MASK 0x00000020 +#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, LPRX_TO_ERR_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR_SHIFT 6 +#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR_MASK 0x00000040 +#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, CRS_UNTERM_PCK_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR_SHIFT 7 +#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR_MASK 0x00000080 +#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, VRS_UNTERM_PCK_CLR, __x) +#define DSI_CMD_MODE_STS_CLR 0x00000114 +#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR_SHIFT 0 +#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR_MASK 0x00000001 +#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_NO_TE_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR_SHIFT 1 +#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR_MASK 0x00000002 +#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_TE_MISS_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR_SHIFT 2 +#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR_MASK 0x00000004 +#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_SDI1_UNDERRUN_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR_SHIFT 3 +#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR_MASK 0x00000008 +#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_SDI2_UNDERRUN_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR_SHIFT 4 +#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR_MASK 0x00000010 +#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_UNWANTED_RD_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR_SHIFT 5 +#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR_MASK 0x00000020 +#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, CSM_RUNNING_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR 0x00000118 +#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR_SHIFT 0 +#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR_MASK 0x00000001 +#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, CMD_TRANSMISSION_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR_SHIFT 1 +#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR_MASK 0x00000002 +#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, WRITE_COMPLETED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR_SHIFT 2 +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR_MASK 0x00000004 +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TRIGGER_COMPLETED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR_SHIFT 3 +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR_MASK 0x00000008 +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, READ_COMPLETED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR_SHIFT 4 +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR_MASK 0x00000010 +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, ACKNOWLEDGE_RECEIVED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR_SHIFT 5 +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR_MASK 0x00000020 +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR_SHIFT 6 +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR_MASK 0x00000040 +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TRIGGER_RECEIVED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR_SHIFT 7 +#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR_MASK 0x00000080 +#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TE_RECEIVED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR_SHIFT 8 +#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR_MASK 0x00000100 +#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, BTA_COMPLETED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR_SHIFT 9 +#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR_MASK 0x00000200 +#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, BTA_FINISHED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR_SHIFT 10 +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR_MASK 0x00000400 +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, READ_COMPLETED_WITH_ERR_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR 0x0000011C +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR_SHIFT 0 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR_MASK 0x00000001 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_FIXED_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR_SHIFT 1 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR_MASK 0x00000002 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_UNCORRECTABLE_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR_SHIFT 2 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR_MASK 0x00000004 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_CHECKSUM_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR_SHIFT 3 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR_MASK 0x00000008 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_UNDECODABLE_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR_SHIFT 4 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR_MASK 0x00000010 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_RECEIVE_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR_SHIFT 5 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR_MASK 0x00000020 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_OVERSIZE_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR_SHIFT 6 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR_MASK 0x00000040 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_WRONG_LENGTH_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR_SHIFT 7 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR_MASK 0x00000080 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_MISSING_EOT_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR_SHIFT 8 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR_MASK 0x00000100 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_EOT_WITH_ERR_CLR, __x) +#define DSI_VID_MODE_STS_CLR 0x00000120 +#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR_SHIFT 0 +#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR_MASK 0x00000001 +#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, VSG_STS_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR_SHIFT 1 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR_MASK 0x00000002 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_DATA_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR_SHIFT 2 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR_MASK 0x00000004 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_HSYNC_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR_SHIFT 3 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR_MASK 0x00000008 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_VSYNC_CLR, __x) +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR_SHIFT 4 +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR_MASK 0x00000010 +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, REG_ERR_SMALL_LENGTH_CLR, __x) +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR_SHIFT 5 +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR_MASK 0x00000020 +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, REG_ERR_SMALL_HEIGHT_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR_SHIFT 6 +#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR_MASK 0x00000040 +#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_BURSTWRITE_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR_SHIFT 7 +#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR_MASK 0x00000080 +#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_LONGWRITE_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR_SHIFT 8 +#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR_MASK 0x00000100 +#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_LONGREAD_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR_SHIFT 9 +#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR_MASK 0x00000200 +#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_VRS_WRONG_LENGTH_CLR, __x) +#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR_SHIFT 10 +#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR_MASK 0x00000400 +#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, VSG_RECOVERY_CLR, __x) +#define DSI_TG_STS_CLR 0x00000124 +#define DSI_TG_STS_CLR_TVG_STS_CLR_SHIFT 0 +#define DSI_TG_STS_CLR_TVG_STS_CLR_MASK 0x00000001 +#define DSI_TG_STS_CLR_TVG_STS_CLR(__x) \ + DSI_VAL2REG(DSI_TG_STS_CLR, TVG_STS_CLR, __x) +#define DSI_TG_STS_CLR_TBG_STS_CLR_SHIFT 1 +#define DSI_TG_STS_CLR_TBG_STS_CLR_MASK 0x00000002 +#define DSI_TG_STS_CLR_TBG_STS_CLR(__x) \ + DSI_VAL2REG(DSI_TG_STS_CLR, TBG_STS_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR 0x00000128 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR_SHIFT 6 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR_MASK 0x00000040 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_ESC_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR_SHIFT 7 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR_MASK 0x00000080 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_ESC_2_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR_SHIFT 8 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR_MASK 0x00000100 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_SYNCESC_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR_SHIFT 9 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR_MASK 0x00000200 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_SYNCESC_2_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR_SHIFT 10 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR_MASK 0x00000400 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONTROL_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR_SHIFT 11 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR_MASK 0x00000800 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONTROL_2_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR_SHIFT 12 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR_MASK 0x00001000 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP0_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR_SHIFT 13 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR_MASK 0x00002000 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP0_2_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR_SHIFT 14 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR_MASK 0x00004000 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP1_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR_SHIFT 15 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR_MASK 0x00008000 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP1_2_CLR, __x) +#define DSI_MCTL_MAIN_STS_FLAG 0x00000130 +#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG_SHIFT 0 +#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG_MASK 0x00000001 +#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, PLL_LOCK_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG_SHIFT 1 +#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG_MASK 0x00000002 +#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, CLKLANE_READY_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG_SHIFT 2 +#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG_MASK 0x00000004 +#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, DAT1_READY_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG_SHIFT 3 +#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG_MASK 0x00000008 +#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, DAT2_READY_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG_SHIFT 4 +#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG_MASK 0x00000010 +#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, HSTX_TO_ERR_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG_SHIFT 5 +#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG_MASK 0x00000020 +#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, LPRX_TO_ERR_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG_SHIFT 6 +#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG_MASK 0x00000040 +#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, CRS_UNTERM_PCK_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG_SHIFT 7 +#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG_MASK 0x00000080 +#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, VRS_UNTERM_PCK_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG 0x00000134 +#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG_SHIFT 0 +#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG_MASK 0x00000001 +#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_NO_TE_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG_SHIFT 1 +#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG_MASK 0x00000002 +#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_TE_MISS_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG_SHIFT 2 +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG_MASK 0x00000004 +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_SDI1_UNDERRUN_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG_SHIFT 3 +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG_MASK 0x00000008 +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_SDI2_UNDERRUN_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG_SHIFT 4 +#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG_MASK 0x00000010 +#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_UNWANTED_RD_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG_SHIFT 5 +#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG_MASK 0x00000020 +#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, CSM_RUNNING_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG 0x00000138 +#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG_SHIFT 0 +#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG_MASK 0x00000001 +#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, CMD_TRANSMISSION_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG_SHIFT 1 +#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG_MASK 0x00000002 +#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, WRITE_COMPLETED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG_SHIFT 2 +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG_MASK 0x00000004 +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TRIGGER_COMPLETED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG_SHIFT 3 +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG_MASK 0x00000008 +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, READ_COMPLETED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG_SHIFT 4 +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG_MASK 0x00000010 +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, ACKNOWLEDGE_RECEIVED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG_SHIFT 5 +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG_MASK 0x00000020 +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG_SHIFT 6 +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG_MASK 0x00000040 +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TRIGGER_RECEIVED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG_SHIFT 7 +#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG_MASK 0x00000080 +#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TE_RECEIVED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG_SHIFT 8 +#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG_MASK 0x00000100 +#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, BTA_COMPLETED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG_SHIFT 9 +#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG_MASK 0x00000200 +#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, BTA_FINISHED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG_SHIFT 10 +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG_MASK 0x00000400 +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, READ_COMPLETED_WITH_ERR_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG 0x0000013C +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG_SHIFT 0 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG_MASK 0x00000001 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_FIXED_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG_SHIFT 1 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG_MASK 0x00000002 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_UNCORRECTABLE_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG_SHIFT 2 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG_MASK 0x00000004 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_CHECKSUM_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG_SHIFT 3 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG_MASK 0x00000008 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_UNDECODABLE_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG_SHIFT 4 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG_MASK 0x00000010 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_RECEIVE_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG_SHIFT 5 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG_MASK 0x00000020 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_OVERSIZE_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG_SHIFT 6 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG_MASK 0x00000040 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_WRONG_LENGTH_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG_SHIFT 7 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG_MASK 0x00000080 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_MISSING_EOT_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG_SHIFT 8 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG_MASK 0x00000100 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_EOT_WITH_ERR_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG 0x00000140 +#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG_SHIFT 0 +#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG_MASK 0x00000001 +#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, VSG_STS_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG_SHIFT 1 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG_MASK 0x00000002 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_DATA_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG_SHIFT 2 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG_MASK 0x00000004 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_HSYNC_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG_SHIFT 3 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG_MASK 0x00000008 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_VSYNC_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG_SHIFT 4 +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG_MASK 0x00000010 +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, REG_ERR_SMALL_LENGTH_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG_SHIFT 5 +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG_MASK 0x00000020 +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, REG_ERR_SMALL_HEIGHT_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG_SHIFT 6 +#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG_MASK 0x00000040 +#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_BURSTWRITE_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG_SHIFT 7 +#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG_MASK 0x00000080 +#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_LONGWRITE_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG_SHIFT 8 +#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG_MASK 0x00000100 +#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_LONGREAD_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG_SHIFT 9 +#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG_MASK 0x00000200 +#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_VRS_WRONG_LENGTH_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG_SHIFT 10 +#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG_MASK 0x00000400 +#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, VSG_RECOVERY_FLAG, __x) +#define DSI_TG_STS_FLAG 0x00000144 +#define DSI_TG_STS_FLAG_TVG_STS_FLAG_SHIFT 0 +#define DSI_TG_STS_FLAG_TVG_STS_FLAG_MASK 0x00000001 +#define DSI_TG_STS_FLAG_TVG_STS_FLAG(__x) \ + DSI_VAL2REG(DSI_TG_STS_FLAG, TVG_STS_FLAG, __x) +#define DSI_TG_STS_FLAG_TBG_STS_FLAG_SHIFT 1 +#define DSI_TG_STS_FLAG_TBG_STS_FLAG_MASK 0x00000002 +#define DSI_TG_STS_FLAG_TBG_STS_FLAG(__x) \ + DSI_VAL2REG(DSI_TG_STS_FLAG, TBG_STS_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG 0x00000148 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG_SHIFT 6 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG_MASK 0x00000040 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_ESC_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG_SHIFT 7 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG_MASK 0x00000080 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_ESC_2_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG_SHIFT 8 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG_MASK 0x00000100 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_SYNCESC_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG_SHIFT 9 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG_MASK 0x00000200 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_SYNCESC_2_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG_SHIFT 10 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG_MASK 0x00000400 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONTROL_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG_SHIFT 11 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG_MASK 0x00000800 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONTROL_2_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG_SHIFT 12 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG_MASK 0x00001000 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP0_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG_SHIFT 13 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG_MASK 0x00002000 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP0_2_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG_SHIFT 14 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG_MASK 0x00004000 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP1_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG_SHIFT 15 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG_MASK 0x00008000 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP1_2_FLAG, __x) +#define DSI_DPHY_LANES_TRIM 0x00000150 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_SHIFT 0 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_MASK 0x00000003 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1_SHIFT 2 +#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1_MASK 0x00000004 +#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_CD_OFF_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1_SHIFT 3 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1_MASK 0x00000008 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1_SHIFT 4 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1_MASK 0x00000010 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1_SHIFT 5 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1_MASK 0x00000020 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_SHIFT 6 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_MASK 0x000000C0 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_SHIFT 8 +#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_MASK 0x00000300 +#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_LP_RX_VIL_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_SHIFT 10 +#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_MASK 0x00000C00 +#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_LP_TX_SLEWRATE_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_SHIFT 12 +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_MASK 0x00001000 +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_81 0 +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90 1 +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_ENUM(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SPECS_90_81B, \ + DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_##__x) +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SPECS_90_81B, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK_SHIFT 13 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK_MASK 0x00002000 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK_SHIFT 14 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK_MASK 0x00004000 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK_SHIFT 15 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK_MASK 0x00008000 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2_SHIFT 16 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2_MASK 0x00030000 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_DAT2, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2_SHIFT 18 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2_MASK 0x00040000 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_DAT2, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2_SHIFT 19 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2_MASK 0x00080000 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_DAT2, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2_SHIFT 20 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2_MASK 0x00100000 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_DAT2, __x) +#define DSI_ID_REG 0x00000FF0 +#define DSI_ID_REG_Y_SHIFT 0 +#define DSI_ID_REG_Y_MASK 0x0000000F +#define DSI_ID_REG_Y(__x) \ + DSI_VAL2REG(DSI_ID_REG, Y, __x) +#define DSI_ID_REG_X_SHIFT 4 +#define DSI_ID_REG_X_MASK 0x000000F0 +#define DSI_ID_REG_X(__x) \ + DSI_VAL2REG(DSI_ID_REG, X, __x) +#define DSI_ID_REG_H_SHIFT 8 +#define DSI_ID_REG_H_MASK 0x00000300 +#define DSI_ID_REG_H(__x) \ + DSI_VAL2REG(DSI_ID_REG, H, __x) +#define DSI_ID_REG_PRODUCT_ID_SHIFT 10 +#define DSI_ID_REG_PRODUCT_ID_MASK 0x0003FC00 +#define DSI_ID_REG_PRODUCT_ID(__x) \ + DSI_VAL2REG(DSI_ID_REG, PRODUCT_ID, __x) +#define DSI_ID_REG_VENDOR_ID_SHIFT 18 +#define DSI_ID_REG_VENDOR_ID_MASK 0xFFFC0000 +#define DSI_ID_REG_VENDOR_ID(__x) \ + DSI_VAL2REG(DSI_ID_REG, VENDOR_ID, __x) +#define DSI_IP_CONF 0x00000FF4 +#define DSI_IP_CONF_FIFO_SIZE_SHIFT 0 +#define DSI_IP_CONF_FIFO_SIZE_MASK 0x0000003F +#define DSI_IP_CONF_FIFO_SIZE(__x) \ + DSI_VAL2REG(DSI_IP_CONF, FIFO_SIZE, __x) + +#endif /* __DSILINK_REGS_H */ diff --git a/board/st/u8500/mcde.h b/board/st/u8500/mcde.h new file mode 100644 index 000000000..58345e8d1 --- /dev/null +++ b/board/st/u8500/mcde.h @@ -0,0 +1,114 @@ +/* +* Copyright (C) ST-Ericsson SA 2010 +* +* Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> +* for ST-Ericsson. +* +* License terms: GNU General Public License (GPL), version 2. +*/ +#ifndef __MCDE__H__ +#define __MCDE__H__ + +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + +/* Physical interface types */ +enum mcde_port_type { + MCDE_PORTTYPE_DSI = 0, +}; + +/* Interface mode */ +enum mcde_port_mode { + MCDE_PORTMODE_CMD = 0, +}; + +/* MCDE fifos */ +enum mcde_fifo { + MCDE_FIFO_A = 0, +}; + +/* MCDE channels (pixel pipelines) */ +enum mcde_chnl { + MCDE_CHNL_C0 = 2, +}; + +/* Update sync mode */ +enum mcde_sync_src { + MCDE_SYNCSRC_BTA = 3, /* DSI BTA */ +}; + +struct mcde_port { + enum mcde_port_type type; + enum mcde_port_mode mode; + u8 ifc; + u8 link; + enum mcde_sync_src sync_src; + union { + struct { + u8 virt_id; + u8 num_data_lanes; + } dsi; + struct { + u8 num_data_lanes; + } dbi; + struct { + t_bool chip_select; + u8 num_data_lanes; + } dpi; + } phy; +}; + +/* Overlay pixel formats (input) */ +enum mcde_ovly_pix_fmt { + MCDE_OVLYPIXFMT_RGB565 = 1, + MCDE_OVLYPIXFMT_RGB888 = 4, +}; + +/* Interface pixel formats (output) */ +enum mcde_port_pix_fmt { + /* MIPI standard formats */ + MCDE_PORTPIXFMT_DSI_24BPP = 0x34, + +}; + +struct mcde_chnl_state; + +struct mcde_chnl_state *mcde_chnl_get(enum mcde_chnl chnl_id, + enum mcde_fifo fifo, const struct mcde_port *port); +void mcde_chnl_set_update_area(struct mcde_chnl_state *chnl, + u16 x, u16 y, u16 w, u16 h); +void mcde_chnl_set_pixel_format(struct mcde_chnl_state *chnl, + enum mcde_port_pix_fmt pix_fmt); +void mcde_chnl_apply(struct mcde_chnl_state *chnl); +void mcde_chnl_update(struct mcde_chnl_state *chnl); + +void mcde_enable_dss(void); + +/* MCDE overlay */ +struct mcde_ovly_state; + +struct mcde_ovly_state *mcde_ovly_get(struct mcde_chnl_state *chnl); +void mcde_ovly_set_source_buf(struct mcde_ovly_state *ovly, + u32 paddr); +void mcde_ovly_set_source_info(struct mcde_ovly_state *ovly, + u32 stride, enum mcde_ovly_pix_fmt pix_fmt); +void mcde_ovly_set_source_area(struct mcde_ovly_state *ovly, + u16 x, u16 y, u16 w, u16 h); +void mcde_ovly_set_dest_pos(struct mcde_ovly_state *ovly, + u16 x, u16 y, u8 z); +void mcde_ovly_apply(struct mcde_ovly_state *ovly); + +/* MCDE dsi */ + +#define MCDE_MAX_DCS_WRITE 15 +#define DCS_CMD_WRITE_START 0x2C +#define DCS_CMD_WRITE_CONTINUE 0x3C + +int mcde_dsi_dcs_write(struct mcde_port *port, u8 cmd, u8* data, int len); + +/* MCDE */ + +int mcde_init(u8 num_data_lanes); +void mcde_exit(void); + +#endif /* __MCDE__H__ */ + diff --git a/board/st/u8500/mcde_display.c b/board/st/u8500/mcde_display.c new file mode 100644 index 000000000..40f7570d6 --- /dev/null +++ b/board/st/u8500/mcde_display.c @@ -0,0 +1,297 @@ +/* +* Copyright (C) ST-Ericsson SA 2010 +* +* Author: Jimmy Rubin <jimmy.rubin@stericsson.com> +* for ST-Ericsson. +* +* License terms: GNU General Public License (GPL), version 2. +*/ + + +#include <common.h> +#include <command.h> +#include "gpio.h" +#include "mcde_display.h" +#include "dsilink_regs.h" +#include <tc35892.h> +#include "mcde_regs.h" +#include <malloc.h> +#include "mcde.h" +#include <linux/err.h> +#include <asm/arch/ab8500.h> +#include "common.h" + +#ifdef CONFIG_SYS_VIDEO_USE_GIMP_HEADER +#include <asm/arch/mcde_video_logo_gimp.h> +#else +#include <asm/arch/mcde_video_logo.h> +#endif + +#define DEBUG 0 +#define dbg_printk(format, arg...) \ + if (DEBUG) \ + printf("mcde: " format, ##arg) \ + +static struct mcde_chnl_state *chnl; + +static struct mcde_port port0 = { + .type = MCDE_PORTTYPE_DSI, + .mode = MCDE_PORTMODE_CMD, + .ifc = 0, + .link = 0, + .sync_src = MCDE_SYNCSRC_BTA, + .phy = { + .dsi = { + .virt_id = 0, + .num_data_lanes = 2, + }, + }, +}; + +struct mcde_display_generic_platform_data main_display_data = { + .reset_gpio = TC35892_PIN_KPY7, + .reset_delay = 1, +}; + +struct mcde_display_device main_display = { + .port = &port0, + .chnl_id = MCDE_CHNL_C0, + .fifo = MCDE_FIFO_A, + .default_pixel_format = MCDE_OVLYPIXFMT_RGB565, + .port_pixel_format = MCDE_PORTPIXFMT_DSI_24BPP, + .native_x_res = 864, + .native_y_res = 480, +}; + +static int mcde_enable_gpio(void) +{ + int ret; + dbg_printk("Enable GPIO pins!\n"); + + /* Only main display should be initialized */ + ret = tc35892_gpio_dir(CONFIG_SYS_I2C_GPIOE_ADDR, + main_display_data.reset_gpio, 1); + if (ret) { + printf("%s:Could not set direction for gpio \n", __func__); + return -EINVAL; + } + ret = tc35892_gpio_set(CONFIG_SYS_I2C_GPIOE_ADDR, + main_display_data.reset_gpio, 0); + if (ret) { + printf("%s:Could reset gpio \n", __func__); + return -EINVAL; + } + mdelay(main_display_data.reset_delay); + ret = tc35892_gpio_set(CONFIG_SYS_I2C_GPIOE_ADDR, + main_display_data.reset_gpio, 1); + if (ret) { + printf("%s:Could set gpior\n", __func__); + return -EINVAL; + } + mdelay(main_display_data.reset_delay); + + dbg_printk("All needed GPIOS enabled!\n"); + return 0; +} + +#define DCS_CMD_EXIT_SLEEP_MODE 0x11 +#define DCS_CMD_SET_DISPLAY_ON 0x29 + +static int mcde_turn_on_display(void) +{ + int ret = 0; + dbg_printk("Turn on display!\n"); + ret = mcde_dsi_dcs_write(main_display.port, + DCS_CMD_EXIT_SLEEP_MODE, NULL, 0); + if (!ret) { + dbg_printk("mcde_dsi_dcs_write " + "DCS_CMD_EXIT_SLEEP_MODE success!\n"); + ret = mcde_dsi_dcs_write(main_display.port, + DCS_CMD_SET_DISPLAY_ON, NULL, 0); + if (!ret) + dbg_printk("mcde_dsi_dcs_write " + "DCS_CMD_SET_DISPLAY_ON success!\n"); + } + + return ret; +} + +#define LDO_VAUX1_MASK 0x1 +#define LDO_VAUX1_ENABLE 0x1 +#define VAUX1_VOLTAGE_2_5V 0x08 + +#define VANA_ENABLE_IN_HP_MODE 0x05 + +#define ENABLE_PWM1 0x01 +#define PWM_DUTY_LOW_1024_1024 0xFF +#define PWM_DUTY_HI_1024_1024 0x03 + +static int mcde_display_power_init(void) +{ + int ret; + int val; + + if (!cpu_is_u8500v11()) + return 0; + + /* Vaux12Regu */ + ret = ab8500_read(AB8500_REGU_CTRL2, AB8500_REGU_VAUX12_REGU_REG); + if (ret < 0) + goto out; + + val = ret; + + /* Vaux1 & Vaux2 HP mode */ + ret = ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VAUX12_REGU_REG, + val | LDO_VAUX1_ENABLE); + if (ret < 0) + goto out; + + udelay(10 * 1000); + + /* Set the voltage to 2.5V */ + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VAUX1_SEL_REG, VAUX1_VOLTAGE_2_5V); + if (ret < 0) + goto out; + + /* DCI & CSI (DSI / PLL / Camera) */ /* Vana & Vpll HP mode */ + ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VPLLVANA_REGU_REG, + VANA_ENABLE_IN_HP_MODE); + + /* Enable the PWM control for the backlight Main display */ + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, ENABLE_PWM1); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL1_REG, + PWM_DUTY_LOW_1024_1024); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL2_REG, + PWM_DUTY_HI_1024_1024); +out: + return ret; +} + + +int mcde_startup(void) +{ + u8 num_dsilinks; + int ret; + u32 i; + + num_dsilinks = main_display.port->phy.dsi.num_data_lanes; + mcde_init(num_dsilinks); + ret = mcde_display_power_init(); + if (ret) + goto display_power_failed; + mcde_enable_dss(); + + ret = mcde_enable_gpio(); + if (ret) + goto enable_gpio_failed; + + chnl = mcde_chnl_get(main_display.chnl_id, main_display.fifo, + main_display.port); + if (IS_ERR(chnl)) { + ret = PTR_ERR(chnl); + printf("%s:Failed to acquire MCDE channel\n", __func__); + goto get_chnl_failed; + } + + ret = mcde_turn_on_display(); + if (ret) + goto display_power_mode_failed; + mcde_chnl_set_update_area(chnl, 0, 0, main_display.native_x_res, + main_display.native_y_res); + mcde_chnl_set_pixel_format(chnl, main_display.port_pixel_format); + mcde_chnl_apply(chnl); + +display_power_mode_failed: +get_chnl_failed: +display_power_failed: +enable_gpio_failed: + mcde_exit(); + return ret; +} + +int mcde_display_image(void) +{ + struct mcde_ovly_state *ovly; + u32 xpos = 0; + u32 ypos = 0; + int ret; +#ifdef CONFIG_SYS_VIDEO_USE_GIMP_HEADER + u32 i = 0; + u8 pixels[3]; + u16 pixel; + u16 *sp; +#endif + + ovly = mcde_ovly_get(chnl); + if (IS_ERR(ovly)) { + ret = PTR_ERR(ovly); + printf("Failed to get channel\n"); + return -ret; + } + +#ifdef CONFIG_SYS_VIDEO_USE_GIMP_HEADER + /* Add the image data */ + sp = (u16 *)CONFIG_SYS_VIDEO_FB_ADRS; + for (i = 0; i < ((MCDE_VIDEO_LOGO_WIDTH*MCDE_VIDEO_LOGO_HEIGHT)); i++) { + HEADER_PIXEL(header_data, pixels); + pixels[0] >>= 3; /* Keep 5 bits red */ + pixels[1] >>= 2; /* 6 bits green */ + pixels[2] >>= 3; /* and 5 bits blue */ + pixel = (pixels[0] << 11) | (pixels[1] << 5) | pixels[2]; + *sp++ = pixel; + } + mcde_ovly_set_source_buf(ovly, CONFIG_SYS_VIDEO_FB_ADRS); +#else + mcde_ovly_set_source_buf(ovly, (u32)&mcde_video_logo[0]); +#endif + mcde_ovly_set_source_info(ovly, (MCDE_VIDEO_LOGO_WIDTH*2), + main_display.default_pixel_format); + mcde_ovly_set_source_area(ovly, 0, 0, MCDE_VIDEO_LOGO_WIDTH, + MCDE_VIDEO_LOGO_HEIGHT); + if (MCDE_VIDEO_LOGO_WIDTH == main_display.native_x_res) + xpos = 0; + else + xpos = (main_display.native_x_res - MCDE_VIDEO_LOGO_WIDTH) / 2; + + if (MCDE_VIDEO_LOGO_HEIGHT == main_display.native_y_res) + ypos = 0; + else + ypos = (main_display.native_y_res - MCDE_VIDEO_LOGO_HEIGHT) / 2; + + mcde_ovly_set_dest_pos(ovly, xpos, ypos, 0); + mcde_ovly_apply(ovly); + mcde_chnl_update(chnl); + /* Wait for refresh to be finished */ + mdelay(CONFIG_SYS_MCDE_REFRESH_TIME); + mcde_exit(); + return 0; +} + +/* + * command line commands + */ + + +int mcde_power_up(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return mcde_startup(); +} + +int mcde_disply_bitmap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return mcde_display_image(); +} + +U_BOOT_CMD( + mcde_power_up, 1, 1, mcde_power_up, + "Power up display", + "" +); + +U_BOOT_CMD( + mcde_display, 1, 1, mcde_disply_bitmap, + "Display bitmap", + "" +); diff --git a/board/st/u8500/mcde_display.h b/board/st/u8500/mcde_display.h new file mode 100644 index 000000000..6941c044c --- /dev/null +++ b/board/st/u8500/mcde_display.h @@ -0,0 +1,38 @@ +/* +* Copyright (C) ST-Ericsson SA 2010 +* +* Author: Jimmy Rubin <jimmy.rubin@stericsson.com> +* for ST-Ericsson. +* +* License terms: GNU General Public License (GPL), version 2. +*/ +#ifndef __MCDE_DISPLAY_H +#define __MCDE_DISPLAY_H + +#include <common.h> +#include "mcde.h" + +extern int cpu_is_u8500v11(void); + +struct mcde_display_generic_platform_data { + /* Platform info */ + int reset_gpio; + int reset_delay; /* ms */ +}; + +struct mcde_display_device { + struct mcde_port *port; + enum mcde_chnl chnl_id; + enum mcde_fifo fifo; + enum mcde_ovly_pix_fmt default_pixel_format; + enum mcde_port_pix_fmt port_pixel_format; + u16 native_x_res; + u16 native_y_res; +}; + +int mcde_startup(void); +int mcde_display_image(void); + +#endif /* !defined(__MCDE_UTILS_H) */ + + diff --git a/board/st/u8500/mcde_hw.c b/board/st/u8500/mcde_hw.c new file mode 100644 index 000000000..8d08d1717 --- /dev/null +++ b/board/st/u8500/mcde_hw.c @@ -0,0 +1,779 @@ +/* +* Copyright (C) ST-Ericsson SA 2010 +* +* Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> +* for ST-Ericsson. +* +* License terms: GNU General Public License (GPL), version 2. +*/ + +#include <common.h> +#include <command.h> +#include "gpio.h" +#include <tc35892.h> +#include <malloc.h> + +#include <linux/err.h> +#include "dsilink_regs.h" +#include "mcde_regs.h" +#include "mcde.h" + +#define DEBUG 0 +#define dbg_printk(format, arg...) \ + if (DEBUG) \ + printf("mcde: " format, ##arg) + +u8 *mcdeio; +u8 **dsiio; + +static inline u32 dsi_rreg(int __i, u32 __reg) +{ + return readl(dsiio[__i] + __reg); +} +static inline void dsi_wreg(int __i, u32 __reg, u32 __val) +{ + writel(__val, dsiio[__i] + __reg); +} +#define dsi_rfld(__i, __reg, __fld) \ + ((dsi_rreg(__i, __reg) & __reg##_##__fld##_MASK) >> \ + __reg##_##__fld##_SHIFT) +#define dsi_wfld(__i, __reg, __fld, __val) \ + dsi_wreg(__i, __reg, (dsi_rreg(__i, __reg) & \ + ~__reg##_##__fld##_MASK) | (((__val) << __reg##_##__fld##_SHIFT) & \ + __reg##_##__fld##_MASK)) + +static inline u32 mcde_rreg(u32 __reg) +{ + return readl(mcdeio + __reg); +} +static inline void mcde_wreg(u32 __reg, u32 __val) +{ + writel(__val, mcdeio + __reg); +} +#define mcde_rfld(__reg, __fld) \ + ((mcde_rreg(__reg) & __reg##_##__fld##_MASK) >> \ + __reg##_##__fld##_SHIFT) +#define mcde_wfld(__reg, __fld, __val) \ + mcde_wreg(__reg, (mcde_rreg(__reg) & \ + ~__reg##_##__fld##_MASK) | (((__val) << __reg##_##__fld##_SHIFT) & \ + __reg##_##__fld##_MASK)) + +struct ovly_regs { + u8 ch_id; + t_bool enabled; + u32 baseaddress0; + u32 baseaddress1; + t_bool buf_id; + u8 bits_per_pixel; + u8 bpp; + t_bool bgr; + t_bool bebo; + t_bool opq; + u8 pixoff; + u16 ppl; + u16 lpf; + u32 ljinc; + u16 cropx; + u16 cropy; + u16 xpos; + u16 ypos; + u8 z; +}; + +struct mcde_ovly_state { + t_bool inuse; + u8 idx; /* MCDE overlay index */ + struct mcde_chnl_state *chnl; /* Owner channel */ + u32 transactionid; /* Apply time stamp */ + u32 transactionid_regs; /* Register update time stamp */ + + /* Staged settings */ + u32 paddr; + u16 stride; + enum mcde_ovly_pix_fmt pix_fmt; + + u16 src_x; + u16 src_y; + u16 dst_x; + u16 dst_y; + u16 dst_z; + u16 w; + u16 h; + + /* Applied settings */ + struct ovly_regs regs; +}; +static struct mcde_ovly_state overlays[] = { + { .idx = 0 }, + { .idx = 1 }, + { .idx = 2 }, + { .idx = 3 }, + { .idx = 4 }, + { .idx = 5 }, +}; + +struct chnl_regs { + t_bool floen; + u16 x; + u16 y; + u16 ppl; + u16 lpf; + u8 bpp; + /* DSI */ + u8 dsipacking; +}; + +struct mcde_chnl_state { + t_bool inuse; + enum mcde_chnl id; + struct mcde_port port; + struct mcde_ovly_state *ovly0; + struct mcde_ovly_state *ovly1; + const struct chnl_config *cfg; + u32 transactionid; + u32 transactionid_regs; + + /* Staged settings */ + t_bool synchronized_update; + enum mcde_port_pix_fmt pix_fmt; + u16 update_x; + u16 update_y; + u16 update_w; + u16 update_h; + + /* Applied settings */ + struct chnl_regs regs; +}; + +static struct mcde_chnl_state channels[] = { + { + .id = MCDE_CHNL_C0, + .ovly0 = &overlays[4], + .ovly1 = NULL, + }, +}; + + +/* MCDE internal helpers */ +static u8 portfmt2dsipacking(enum mcde_port_pix_fmt pix_fmt) +{ + switch (pix_fmt) { + case MCDE_PORTPIXFMT_DSI_24BPP: + default: + return MCDE_DSIVID0CONF0_PACKING_RGB888; + } +} + +static u8 portfmt2bpp(enum mcde_port_pix_fmt pix_fmt) +{ + switch (pix_fmt) { + case MCDE_PORTPIXFMT_DSI_24BPP: + return 24; + default: + return 0; + } +} + +void update_channel_static_registers(struct mcde_chnl_state *chnl) +{ + const struct mcde_port *port = &chnl->port; + int i = 0; + u8 idx = 2 * port->link + port->ifc; + u8 lnk = port->link; + /* Fifo & muxing */ + mcde_wfld(MCDE_CONF0, SWAP_A_C0, TRUE); + mcde_wfld(MCDE_CR, FABMUX, FALSE); + + /* Formatter */ + dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, LINK_EN, TRUE); + + dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, BTA_EN, TRUE); + dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, READ_EN, TRUE); + dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, REG_TE_EN, TRUE); + dsi_wreg(lnk, DSI_MCTL_DPHY_STATIC, + DSI_MCTL_DPHY_STATIC_UI_X4(0xf)); + dsi_wreg(lnk, DSI_DPHY_LANES_TRIM, + DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_ENUM(0_90)); + dsi_wreg(lnk, DSI_MCTL_DPHY_TIMEOUT, + DSI_MCTL_DPHY_TIMEOUT_CLK_DIV(0xf) | + DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL(0x3fff) | + DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL(0x3fff)); + dsi_wreg(lnk, DSI_MCTL_MAIN_PHY_CTL, + DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME(0xf) | + DSI_MCTL_MAIN_PHY_CTL_LANE2_EN(TRUE) | + DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS(FALSE)); + dsi_wreg(lnk, DSI_MCTL_ULPOUT_TIME, + DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME(1) | + DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME(1)); + dsi_wfld(lnk, DSI_CMD_MODE_CTL, ARB_MODE, TRUE); + dsi_wfld(lnk, DSI_CMD_MODE_CTL, TE_TIMEOUT, 0x3ff); + dsi_wreg(lnk, DSI_MCTL_MAIN_EN, + DSI_MCTL_MAIN_EN_PLL_START(TRUE) | + DSI_MCTL_MAIN_EN_CKLANE_EN(TRUE) | + DSI_MCTL_MAIN_EN_DAT1_EN(TRUE) | + DSI_MCTL_MAIN_EN_DAT2_EN(port->phy.dsi.num_data_lanes + == 2) | + DSI_MCTL_MAIN_EN_IF1_EN(TRUE)); + + while (dsi_rfld(lnk, DSI_MCTL_MAIN_STS, CLKLANE_READY) == 0 || + dsi_rfld(lnk, DSI_MCTL_MAIN_STS, DAT1_READY) == 0 || + dsi_rfld(lnk, DSI_MCTL_MAIN_STS, DAT2_READY) == 0) { + mdelay(1); + if (i++ == 10) + printf("DSI lane not ready (link=%d)!\n", lnk); + } + + if (port->ifc == 0 && port->link == 0) + mcde_wfld(MCDE_CR, DSIVID0_EN, TRUE); + else if (port->ifc == 0 && port->link == 1) + mcde_wfld(MCDE_CR, DSIVID1_EN, TRUE); + else if (port->ifc == 0 && port->link == 2) + mcde_wfld(MCDE_CR, DSIVID2_EN, TRUE); + else if (port->ifc == 1 && port->link == 0) + mcde_wfld(MCDE_CR, DSICMD0_EN, TRUE); + else if (port->ifc == 1 && port->link == 1) + mcde_wfld(MCDE_CR, DSICMD1_EN, TRUE); + else if (port->ifc == 1 && port->link == 2) + mcde_wfld(MCDE_CR, DSICMD2_EN, TRUE); + mcde_wreg(MCDE_DSIVID0CONF0 + + idx * MCDE_DSIVID0CONF0_GROUPOFFSET, + MCDE_DSIVID0CONF0_BLANKING(0) | + MCDE_DSIVID0CONF0_VID_MODE(0) | + MCDE_DSIVID0CONF0_CMD8(TRUE) | + MCDE_DSIVID0CONF0_BIT_SWAP(FALSE) | + MCDE_DSIVID0CONF0_BYTE_SWAP(FALSE) | + MCDE_DSIVID0CONF0_DCSVID_NOTGEN(TRUE)); + + if (port->ifc == 0) + dsi_wfld(port->link, DSI_CMD_MODE_CTL, IF1_ID, + port->phy.dsi.virt_id); + else if (port->ifc == 1) + dsi_wfld(port->link, DSI_CMD_MODE_CTL, IF2_ID, + port->phy.dsi.virt_id); + + mcde_wfld(MCDE_CRC, SYCEN0, TRUE); + mcde_wreg(MCDE_VSCRC0, + MCDE_VSCRC0_VSPMIN(1) | + MCDE_VSCRC0_VSPMAX(0xff)); + mcde_wreg(MCDE_CTRLC0, MCDE_CTRLC0_FIFOWTRMRK(0xa0)); + + mcde_wfld(MCDE_CR, MCDEEN, TRUE); + dbg_printk("Static registers setup, chnl=%d\n", chnl->id); +} + +static void update_overlay_registers(u8 idx, struct ovly_regs *regs, + u16 update_x, u16 update_y, u16 update_w, u16 update_h) +{ + u32 lmrgn = (regs->cropx + update_x) * regs->bits_per_pixel; + u32 tmrgn = (regs->cropy + update_y) * regs->ljinc; + u32 ppl = regs->ppl - update_x; + u32 lpf = regs->lpf - update_y; + + if (!regs->enabled) { + u32 temp; + temp = mcde_rreg(MCDE_OVL0CR + idx * MCDE_OVL0CR_GROUPOFFSET); + mcde_wreg(MCDE_OVL0CR + idx * MCDE_OVL0CR_GROUPOFFSET, + (temp & ~MCDE_OVL0CR_OVLEN_MASK) | + MCDE_OVL0CR_OVLEN(FALSE)); + return; + } + + mcde_wreg(MCDE_EXTSRC0A0 + idx * MCDE_EXTSRC0A0_GROUPOFFSET, + regs->baseaddress0); + mcde_wreg(MCDE_EXTSRC0A1 + idx * MCDE_EXTSRC0A1_GROUPOFFSET, + regs->baseaddress1); + mcde_wreg(MCDE_EXTSRC0CONF + idx * MCDE_EXTSRC0CONF_GROUPOFFSET, + MCDE_EXTSRC0CONF_BUF_ID(regs->buf_id) | + MCDE_EXTSRC0CONF_BUF_NB(2) | + MCDE_EXTSRC0CONF_PRI_OVLID(idx) | + MCDE_EXTSRC0CONF_BPP(regs->bpp) | + MCDE_EXTSRC0CONF_BGR(regs->bgr) | + MCDE_EXTSRC0CONF_BEBO(regs->bebo) | + MCDE_EXTSRC0CONF_BEPO(FALSE)); + mcde_wreg(MCDE_EXTSRC0CR + idx * MCDE_EXTSRC0CR_GROUPOFFSET, + MCDE_EXTSRC0CR_SEL_MOD_ENUM(SOFTWARE_SEL) | + MCDE_EXTSRC0CR_MULTIOVL_CTRL_ENUM(PRIMARY) | + MCDE_EXTSRC0CR_FS_DIV_DISABLE(FALSE) | + MCDE_EXTSRC0CR_FORCE_FS_DIV(FALSE)); + mcde_wreg(MCDE_OVL0CR + idx * MCDE_OVL0CR_GROUPOFFSET, + MCDE_OVL0CR_OVLEN(TRUE) | + MCDE_OVL0CR_COLCCTRL_ENUM(DISABLED) | + MCDE_OVL0CR_CKEYGEN(FALSE) | + MCDE_OVL0CR_ALPHAPMEN(TRUE) | + MCDE_OVL0CR_OVLF(FALSE) | + MCDE_OVL0CR_OVLR(FALSE) | + MCDE_OVL0CR_OVLB(FALSE) | + MCDE_OVL0CR_FETCH_ROPC(0) | + MCDE_OVL0CR_STBPRIO(0) | + MCDE_OVL0CR_BURSTSIZE(11) | /* TODO: _HW_8W */ + MCDE_OVL0CR_MAXOUTSTANDING(2) | /* TODO: get from ovly */ + MCDE_OVL0CR_ROTBURSTSIZE(2)); /* TODO: _4W, calculate? */ + mcde_wreg(MCDE_OVL0CONF + idx * MCDE_OVL0CONF_GROUPOFFSET, + MCDE_OVL0CONF_PPL(ppl) | + MCDE_OVL0CONF_EXTSRC_ID(idx) | + MCDE_OVL0CONF_LPF(lpf)); + mcde_wreg(MCDE_OVL0CONF2 + idx * MCDE_OVL0CONF2_GROUPOFFSET, + MCDE_OVL0CONF2_BP_ENUM(PER_PIXEL_ALPHA) | + MCDE_OVL0CONF2_ALPHAVALUE(128) | /* TODO: Allow setting? */ + MCDE_OVL0CONF2_OPQ(regs->opq) | + MCDE_OVL0CONF2_PIXOFF(lmrgn & 63) | + MCDE_OVL0CONF2_PIXELFETCHERWATERMARKLEVEL(32)); + mcde_wreg(MCDE_OVL0LJINC + idx * MCDE_OVL0LJINC_GROUPOFFSET, + regs->ljinc); + mcde_wreg(MCDE_OVL0CROP + idx * MCDE_OVL0CROP_GROUPOFFSET, + MCDE_OVL0CROP_TMRGN(tmrgn) | + MCDE_OVL0CROP_LMRGN(lmrgn >> 6)); + mcde_wreg(MCDE_OVL0COMP + idx * MCDE_OVL0COMP_GROUPOFFSET, + MCDE_OVL0COMP_XPOS(regs->xpos) | + MCDE_OVL0COMP_CH_ID(regs->ch_id) | + MCDE_OVL0COMP_YPOS(regs->ypos) | + MCDE_OVL0COMP_Z(regs->z)); + dbg_printk("Overlay registers setup, idx=%d\n", idx); +} + +void update_channel_registers(enum mcde_chnl chnl_id, struct chnl_regs *regs, + struct mcde_port *port) +{ + u8 idx = chnl_id; + if (!regs->floen) { + mcde_wfld(MCDE_CRC, C1EN, FALSE); + if (!mcde_rfld(MCDE_CRC, C2EN)) + mcde_wfld(MCDE_CRC, FLOEN, FALSE); + } + + /* Channel */ + mcde_wreg(MCDE_CHNL0CONF + idx * MCDE_CHNL0CONF_GROUPOFFSET, + MCDE_CHNL0CONF_PPL(regs->ppl-1) | + MCDE_CHNL0CONF_LPF(regs->lpf-1)); + mcde_wreg(MCDE_CHNL0STAT + idx * MCDE_CHNL0STAT_GROUPOFFSET, + MCDE_CHNL0STAT_CHNLBLBCKGND_EN(FALSE) | + MCDE_CHNL0STAT_CHNLRD(TRUE)); + mcde_wreg(MCDE_CHNL0SYNCHMOD + idx * MCDE_CHNL0SYNCHMOD_GROUPOFFSET, + MCDE_CHNL0SYNCHMOD_SRC_SYNCH_ENUM(SOFTWARE) | /* TODO: */ + MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_ENUM(FORMATTER)); + mcde_wreg(MCDE_CHNL0BCKGNDCOL + idx * MCDE_CHNL0BCKGNDCOL_GROUPOFFSET, + MCDE_CHNL0BCKGNDCOL_B(255) | /* TODO: Temp */ + MCDE_CHNL0BCKGNDCOL_G(255) | + MCDE_CHNL0BCKGNDCOL_R(255)); + mcde_wreg(MCDE_CHNL0PRIO + idx * MCDE_CHNL0PRIO_GROUPOFFSET, + MCDE_CHNL0PRIO_CHNLPRIO(0)); + + mcde_wfld(MCDE_CRC, POWEREN, TRUE); + mcde_wfld(MCDE_CRC, FLOEN, TRUE); + mcde_wfld(MCDE_CRC, C1EN, TRUE); + + /* Formatter */ + { + u8 fidx = 2 * port->link + port->ifc; + u32 temp, packet; + temp = mcde_rreg(MCDE_DSIVID0CONF0 + + fidx * MCDE_DSIVID0CONF0_GROUPOFFSET); + mcde_wreg(MCDE_DSIVID0CONF0 + + fidx * MCDE_DSIVID0CONF0_GROUPOFFSET, + (temp & ~MCDE_DSIVID0CONF0_PACKING_MASK) | + MCDE_DSIVID0CONF0_PACKING(regs->dsipacking)); + packet = ((regs->ppl * regs->bpp) >> 3) + 1; /* 1==CMD8 */ + mcde_wreg(MCDE_DSIVID0FRAME + + fidx * MCDE_DSIVID0FRAME_GROUPOFFSET, + MCDE_DSIVID0FRAME_FRAME(packet * regs->lpf)); + mcde_wreg(MCDE_DSIVID0PKT + fidx * MCDE_DSIVID0PKT_GROUPOFFSET, + MCDE_DSIVID0PKT_PACKET(packet)); + mcde_wreg(MCDE_DSIVID0SYNC + + fidx * MCDE_DSIVID0SYNC_GROUPOFFSET, + MCDE_DSIVID0SYNC_SW(0) | + MCDE_DSIVID0SYNC_DMA(0)); + mcde_wreg(MCDE_DSIVID0CMDW + + fidx * MCDE_DSIVID0CMDW_GROUPOFFSET, + MCDE_DSIVID0CMDW_CMDW_START(DCS_CMD_WRITE_START) | + MCDE_DSIVID0CMDW_CMDW_CONTINUE(DCS_CMD_WRITE_CONTINUE)); + mcde_wreg(MCDE_DSIVID0DELAY0 + + fidx * MCDE_DSIVID0DELAY0_GROUPOFFSET, + MCDE_DSIVID0DELAY0_INTPKTDEL(0)); + mcde_wreg(MCDE_DSIVID0DELAY1 + + fidx * MCDE_DSIVID0DELAY1_GROUPOFFSET, + MCDE_DSIVID0DELAY1_TEREQDEL(0) | + MCDE_DSIVID0DELAY1_FRAMESTARTDEL(0)); + } + dbg_printk("Channel registers setup, chnl=%d\n", chnl_id); +} + +/* MCDE channels */ +struct mcde_chnl_state *mcde_chnl_get(enum mcde_chnl chnl_id, + enum mcde_fifo fifo, const struct mcde_port *port) +{ + int i; + struct mcde_chnl_state *chnl = NULL; + + /* Allocate channel */ + for (i = 0; i < ARRAY_SIZE(channels); i++) { + if (chnl_id == channels[i].id) + chnl = &channels[i]; + } + if (!chnl) { + printf("Invalid channel, chnl=%d\n", chnl_id); + return ERR_PTR(-EINVAL); + } + if (chnl->inuse) { + printf("Channel in use, chnl=%d\n", chnl_id); + return ERR_PTR(-EBUSY); + } + + chnl->port = *port; + chnl->synchronized_update = FALSE; + chnl->update_x = 0; + chnl->update_y = 0; + chnl->update_w = 0; + chnl->update_h = 0; + mcde_chnl_apply(chnl); + + update_channel_static_registers(chnl); + + chnl->inuse = TRUE; + return chnl; +} + +void mcde_chnl_set_update_area(struct mcde_chnl_state *chnl, + u16 x, u16 y, u16 w, u16 h) +{ + if (!chnl->inuse) + return; + + chnl->update_x = x; + chnl->update_y = y; + chnl->update_w = w; + chnl->update_h = h; +} + +void mcde_chnl_set_pixel_format(struct mcde_chnl_state *chnl, + enum mcde_port_pix_fmt pix_fmt) +{ + if (!chnl->inuse) + return; + + chnl->pix_fmt = pix_fmt; +} + +void mcde_chnl_apply(struct mcde_chnl_state *chnl) +{ + t_bool enable; + if (!chnl->inuse) + return; + + enable = chnl->update_w > 0 && chnl->update_h > 0; + chnl->regs.floen = enable; + chnl->regs.ppl = chnl->update_w; + chnl->regs.lpf = chnl->update_h; + chnl->regs.bpp = portfmt2bpp(chnl->pix_fmt); + chnl->regs.dsipacking = portfmt2dsipacking(chnl->pix_fmt); + chnl->transactionid++; + dbg_printk("Channel applied, chnl=%d\n", chnl->id); +} + +void mcde_chnl_update(struct mcde_chnl_state *chnl) +{ + struct mcde_ovly_state *ovly; + + if (!chnl->inuse || !chnl->regs.floen) + return; + + /* Commit settings to registers */ + ovly = chnl->ovly0; + if (ovly->transactionid_regs < ovly->transactionid || + chnl->transactionid_regs < chnl->transactionid) { + update_overlay_registers(ovly->idx, &ovly->regs, + chnl->regs.x, chnl->regs.y, + chnl->regs.ppl, chnl->regs.lpf); + ovly->transactionid_regs = ovly->transactionid; + } + ovly = chnl->ovly1; + if (ovly && ( + ovly->transactionid_regs < ovly->transactionid || + chnl->transactionid_regs < chnl->transactionid)) { + update_overlay_registers(ovly->idx, &ovly->regs, + chnl->regs.x, chnl->regs.y, + chnl->regs.ppl, chnl->regs.lpf); + ovly->transactionid_regs = ovly->transactionid; + } + if (chnl->transactionid_regs < chnl->transactionid) { + update_channel_registers(chnl->id, &chnl->regs, &chnl->port); + chnl->transactionid_regs = chnl->transactionid; + } + + if (chnl->regs.floen) + mcde_wreg(MCDE_CHNL0SYNCHSW + + chnl->id * MCDE_CHNL0SYNCHSW_GROUPOFFSET, + MCDE_CHNL0SYNCHSW_SW_TRIG(TRUE)); + dbg_printk("Channel updated, chnl=%d\n", chnl->id); +} + +/* MCDE overlays */ +struct mcde_ovly_state *mcde_ovly_get(struct mcde_chnl_state *chnl) +{ + struct mcde_ovly_state *ovly; + + if (!chnl->inuse) + return ERR_PTR(-EINVAL); + + if (!chnl->ovly0->inuse) + ovly = chnl->ovly0; + else if (chnl->ovly1 && !chnl->ovly1->inuse) + ovly = chnl->ovly1; + else + ovly = ERR_PTR(-EBUSY); + + if (!IS_ERR(ovly)) { + ovly->inuse = TRUE; + ovly->paddr = 0; + ovly->stride = 0; + ovly->pix_fmt = MCDE_OVLYPIXFMT_RGB565; + ovly->src_x = 0; + ovly->src_y = 0; + ovly->dst_x = 0; + ovly->dst_y = 0; + ovly->dst_z = 0; + ovly->w = 0; + ovly->h = 0; + mcde_ovly_apply(ovly); + } + + return ovly; +} + +void mcde_ovly_set_source_buf(struct mcde_ovly_state *ovly, u32 paddr) +{ + if (!ovly->inuse) + return; + + ovly->paddr = paddr; +} + +void mcde_ovly_set_source_info(struct mcde_ovly_state *ovly, + u32 stride, enum mcde_ovly_pix_fmt pix_fmt) +{ + if (!ovly->inuse) + return; + + ovly->stride = stride; + ovly->pix_fmt = pix_fmt; +} + +void mcde_ovly_set_source_area(struct mcde_ovly_state *ovly, + u16 x, u16 y, u16 w, u16 h) +{ + if (!ovly->inuse) + return; + + ovly->src_x = x; + ovly->src_y = y; + ovly->w = w; + ovly->h = h; +} + +void mcde_ovly_set_dest_pos(struct mcde_ovly_state *ovly, u16 x, u16 y, u8 z) +{ + if (!ovly->inuse) + return; + + ovly->dst_x = x; + ovly->dst_y = y; + ovly->dst_z = z; +} + +void mcde_ovly_apply(struct mcde_ovly_state *ovly) +{ + if (!ovly->inuse) + return; + + ovly->regs.ch_id = ovly->chnl->id; + ovly->regs.enabled = ovly->paddr != 0; + if (ovly->regs.buf_id) + ovly->regs.baseaddress0 = ovly->paddr; + else + ovly->regs.baseaddress1 = ovly->paddr; + ovly->regs.buf_id = !ovly->regs.buf_id; + switch (ovly->pix_fmt) { + case MCDE_OVLYPIXFMT_RGB565: + ovly->regs.bits_per_pixel = 16; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_RGB565; + ovly->regs.bgr = FALSE; + ovly->regs.bebo = FALSE; + ovly->regs.opq = TRUE; + break; + case MCDE_OVLYPIXFMT_RGB888: + ovly->regs.bits_per_pixel = 24; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_RGB888; + ovly->regs.bgr = TRUE; + ovly->regs.bebo = FALSE; + ovly->regs.opq = TRUE; + break; + default: + break; + } + ovly->regs.ppl = ovly->w; + ovly->regs.lpf = ovly->h; + ovly->regs.ljinc = ovly->stride; + ovly->regs.cropx = ovly->src_x; + ovly->regs.cropy = ovly->src_y; + ovly->regs.xpos = ovly->dst_x; + ovly->regs.ypos = ovly->dst_y; + ovly->regs.z = ovly->dst_z > 0; /* 0 or 1 */ + + ovly->transactionid = ++ovly->chnl->transactionid; + dbg_printk("Overlay applied, chnl=%d\n", ovly->chnl->id); +} + +/* DSI */ +int mcde_dsi_dcs_write(struct mcde_port *port, u8 cmd, u8* data, int len) +{ + int i; + u32 wrdat[4] = { 0, 0, 0, 0 }; + u32 settings; + u8 link = port->link; + u8 virt_id = port->phy.dsi.virt_id; + + if (len > MCDE_MAX_DCS_WRITE) + return -EINVAL; + + wrdat[0] = cmd; + for (i = 1; i <= len; i++) + wrdat[i>>2] |= (data[i-1] << (i & 3)); + + settings = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_ENUM(WRITE) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT(len > 1) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID(virt_id) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE(len+1) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN(TRUE); + if (len == 0) + settings |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM( + DCS_SHORT_WRITE_0); + else if (len == 1) + settings |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM( + DCS_SHORT_WRITE_1); + else + settings |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM( + DCS_LONG_WRITE); + + dsi_wreg(link, DSI_DIRECT_CMD_MAIN_SETTINGS, settings); + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT0, wrdat[0]); + if (len > 3) + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT1, wrdat[1]); + if (len > 7) + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT2, wrdat[2]); + if (len > 11) + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT3, wrdat[3]); + dsi_wreg(link, DSI_DIRECT_CMD_STS_CLR, ~0); + dsi_wreg(link, DSI_DIRECT_CMD_SEND, TRUE); + + mdelay(10); + return 0; +} + +void mcde_enable_dss(void) +{ + /* Setup clocks */ + #define MCDE_PRCM_MMIP_LS_CLAMP_SET 0x420 + #define MCDE_PRCM_APE_RESETN_CLR 0x1E8 + #define MCDE_PRCM_EPOD_C_SET 0x410 + #define MCDE_PRCM_SRAM_LS_SLEEP 0x304 + #define MCDE_PRCM_MMIP_LS_CLAMP_CLR 0x424 + #define MCDE_PRCM_POWER_STATE_SET 0x254 + #define MCDE_PRCM_LCDCLK_MGT 0x044 + #define MCDE_PRCM_MCDECLK_MGT 0x064 + #define MCDE_PRCM_HDMICLK_MGT 0x058 + #define MCDE_PRCM_TVCLK_MGT 0x07c + #define MCDE_PRCM_PLLDSI_FREQ 0x500 + #define MCDE_PRCM_PLLDSI_ENABLE 0x504 + #define MCDE_PRCM_APE_RESETN_SET 0x1E4 + #define MCDE_PRCM_DSI_PLLOUT_SEL 0x530 + #define MCDE_PRCM_DSITVCLK_DIV 0x52C + #define MCDE_PRCM_DSI_SW_RESET 0x324 + + /* Clamp DSS out, DSIPLL in/out, (why not DSS input?) */ + u32 temp; + + u8* prcmu = (u8 *)CFG_PRCMU_BASE; + + writel(0x00600C00, &prcmu[MCDE_PRCM_MMIP_LS_CLAMP_SET]); + mdelay(2); + /* Enable DSS_M_INITN, DSS_L_RESETN, DSIPLL_RESETN resets */ + writel(0x0000000C, &prcmu[MCDE_PRCM_APE_RESETN_CLR]); + mdelay(2); + /* Power on DSS mem */ + writel(0x00200000, &prcmu[MCDE_PRCM_EPOD_C_SET]); + mdelay(2); + /* Power on DSS logic */ + writel(0x00100000, &prcmu[MCDE_PRCM_EPOD_C_SET]); + mdelay(2); + /* Release DSS_SLEEP */ + temp = readl(&prcmu[MCDE_PRCM_SRAM_LS_SLEEP]); + writel(temp & ~0x400, &prcmu[MCDE_PRCM_SRAM_LS_SLEEP]); + mdelay(2); + /* Unclamp DSS out, DSIPLL in/out, (why not DSS input?) */ + writel(0x00600C00, &prcmu[MCDE_PRCM_MMIP_LS_CLAMP_CLR]); + mdelay(2); + /* Power on CSI_DSI */ + writel(0x00008000, &prcmu[MCDE_PRCM_POWER_STATE_SET]); + mdelay(2); + + /* PLLDIV=8, PLLSW=2, CLKEN=1 */ + writel(0x00000148, &prcmu[MCDE_PRCM_LCDCLK_MGT]); + mdelay(2); + /* PLLDIV=5, PLLSW=1, CLKEN=1 */ + writel(0x00000125, &prcmu[MCDE_PRCM_MCDECLK_MGT]); + mdelay(2); + /* PLLDIV=5, PLLSW=2, CLKEN=1 */ + writel(0x00000145, &prcmu[MCDE_PRCM_HDMICLK_MGT]); + mdelay(2); + /* PLLDIV=14, PLLSW=2, CLKEN=1 */ + writel(0x00000145, &prcmu[MCDE_PRCM_TVCLK_MGT]); + mdelay(2); + /* D=32, N=1, R=4, SELDIV2=0 */ + writel(0x00040120, &prcmu[MCDE_PRCM_PLLDSI_FREQ]); + mdelay(2); + /* Start DSI PLL */ + writel(0x00000001, &prcmu[MCDE_PRCM_PLLDSI_ENABLE]); + mdelay(2); + /* Release DSS_M_INITN, DSS_L_RESETN, DSIPLL_RESETN */ + writel(0x0000400C, &prcmu[MCDE_PRCM_APE_RESETN_SET]); + mdelay(2); + /* DSI0=phi/2, DSI1=phi/2 */ + writel(0x00000202, &prcmu[MCDE_PRCM_DSI_PLLOUT_SEL]); + mdelay(2); + /* Enable ESC clk 0/1/2, div0=8, div1=8, div2=3 */ + writel(0x07030303, &prcmu[MCDE_PRCM_DSITVCLK_DIV]); + mdelay(2); + /* Release DSI reset 0/1/2 */ + writel(0x00000007, &prcmu[MCDE_PRCM_DSI_SW_RESET]); + mdelay(2); + dbg_printk("PRCMU setup done!\n"); +} + +int mcde_init(u8 num_data_lanes) +{ + int i; + for (i = 0; i < ARRAY_SIZE(channels); i++) { + channels[i].ovly0->chnl = &channels[i]; + if (channels[i].ovly1) + channels[i].ovly1->chnl = &channels[i]; + } + + dsiio = malloc(num_data_lanes * sizeof(*dsiio)); + if (!dsiio) { + printf("%s: Failed to malloc dsiio\n", __func__); + return -EINVAL; + } + + mcdeio = (u8 *)CFG_MCDE_BASE; + dbg_printk("MCDE iomap: 0x%.8X\n", (u32)mcdeio); + for (i = 0; i < num_data_lanes; i++) { + dsiio[i] = (u8 *)(CFG_DSI_BASE + i*0x1000); + dbg_printk("MCDE DSI%d iomap: 0x%.8X\n", i, (u32)dsiio[i]); + } + return 0; +} + +void mcde_exit(void) +{ + if (dsiio) + free(dsiio); +} diff --git a/board/st/u8500/mcde_regs.h b/board/st/u8500/mcde_regs.h new file mode 100644 index 000000000..57433b810 --- /dev/null +++ b/board/st/u8500/mcde_regs.h @@ -0,0 +1,5098 @@ +/* +* Copyright (C) ST-Ericsson SA 2010 +* +* Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> +* for ST-Ericsson. +* +* License terms: GNU General Public License (GPL), version 2. +*/ + +#ifndef __MCDE_REGS_H__ +#define __MCDE_REGS_H__ + +#define MCDE_VAL2REG(__reg, __fld, __val) \ + (((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK) +#define MCDE_REG2VAL(__reg, __fld, __val) \ + (((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT) + +#define MCDE_CR 0x00000000 +#define MCDE_CR_DSICMD2_EN_SHIFT 0 +#define MCDE_CR_DSICMD2_EN_MASK 0x00000001 +#define MCDE_CR_DSICMD2_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSICMD2_EN, __x) +#define MCDE_CR_DSICMD1_EN_SHIFT 1 +#define MCDE_CR_DSICMD1_EN_MASK 0x00000002 +#define MCDE_CR_DSICMD1_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSICMD1_EN, __x) +#define MCDE_CR_DSICMD0_EN_SHIFT 2 +#define MCDE_CR_DSICMD0_EN_MASK 0x00000004 +#define MCDE_CR_DSICMD0_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSICMD0_EN, __x) +#define MCDE_CR_DSIVID2_EN_SHIFT 3 +#define MCDE_CR_DSIVID2_EN_MASK 0x00000008 +#define MCDE_CR_DSIVID2_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSIVID2_EN, __x) +#define MCDE_CR_DSIVID1_EN_SHIFT 4 +#define MCDE_CR_DSIVID1_EN_MASK 0x00000010 +#define MCDE_CR_DSIVID1_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSIVID1_EN, __x) +#define MCDE_CR_DSIVID0_EN_SHIFT 5 +#define MCDE_CR_DSIVID0_EN_MASK 0x00000020 +#define MCDE_CR_DSIVID0_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSIVID0_EN, __x) +#define MCDE_CR_DBIC1_EN_SHIFT 6 +#define MCDE_CR_DBIC1_EN_MASK 0x00000040 +#define MCDE_CR_DBIC1_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DBIC1_EN, __x) +#define MCDE_CR_DBIC0_EN_SHIFT 7 +#define MCDE_CR_DBIC0_EN_MASK 0x00000080 +#define MCDE_CR_DBIC0_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DBIC0_EN, __x) +#define MCDE_CR_DPIB_EN_SHIFT 8 +#define MCDE_CR_DPIB_EN_MASK 0x00000100 +#define MCDE_CR_DPIB_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DPIB_EN, __x) +#define MCDE_CR_DPIA_EN_SHIFT 9 +#define MCDE_CR_DPIA_EN_MASK 0x00000200 +#define MCDE_CR_DPIA_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DPIA_EN, __x) +#define MCDE_CR_IFIFOCTRLEN_SHIFT 15 +#define MCDE_CR_IFIFOCTRLEN_MASK 0x00008000 +#define MCDE_CR_IFIFOCTRLEN(__x) \ + MCDE_VAL2REG(MCDE_CR, IFIFOCTRLEN, __x) +#define MCDE_CR_F01MUX_SHIFT 16 +#define MCDE_CR_F01MUX_MASK 0x00010000 +#define MCDE_CR_F01MUX(__x) \ + MCDE_VAL2REG(MCDE_CR, F01MUX, __x) +#define MCDE_CR_FABMUX_SHIFT 17 +#define MCDE_CR_FABMUX_MASK 0x00020000 +#define MCDE_CR_FABMUX(__x) \ + MCDE_VAL2REG(MCDE_CR, FABMUX, __x) +#define MCDE_CR_AUTOCLKG_EN_SHIFT 30 +#define MCDE_CR_AUTOCLKG_EN_MASK 0x40000000 +#define MCDE_CR_AUTOCLKG_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, AUTOCLKG_EN, __x) +#define MCDE_CR_MCDEEN_SHIFT 31 +#define MCDE_CR_MCDEEN_MASK 0x80000000 +#define MCDE_CR_MCDEEN(__x) \ + MCDE_VAL2REG(MCDE_CR, MCDEEN, __x) +#define MCDE_CONF0 0x00000004 +#define MCDE_CONF0_SYNCMUX0_SHIFT 0 +#define MCDE_CONF0_SYNCMUX0_MASK 0x00000001 +#define MCDE_CONF0_SYNCMUX0(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX0, __x) +#define MCDE_CONF0_SYNCMUX1_SHIFT 1 +#define MCDE_CONF0_SYNCMUX1_MASK 0x00000002 +#define MCDE_CONF0_SYNCMUX1(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX1, __x) +#define MCDE_CONF0_SYNCMUX2_SHIFT 2 +#define MCDE_CONF0_SYNCMUX2_MASK 0x00000004 +#define MCDE_CONF0_SYNCMUX2(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX2, __x) +#define MCDE_CONF0_SYNCMUX3_SHIFT 3 +#define MCDE_CONF0_SYNCMUX3_MASK 0x00000008 +#define MCDE_CONF0_SYNCMUX3(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX3, __x) +#define MCDE_CONF0_SYNCMUX4_SHIFT 4 +#define MCDE_CONF0_SYNCMUX4_MASK 0x00000010 +#define MCDE_CONF0_SYNCMUX4(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX4, __x) +#define MCDE_CONF0_SYNCMUX5_SHIFT 5 +#define MCDE_CONF0_SYNCMUX5_MASK 0x00000020 +#define MCDE_CONF0_SYNCMUX5(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX5, __x) +#define MCDE_CONF0_SYNCMUX6_SHIFT 6 +#define MCDE_CONF0_SYNCMUX6_MASK 0x00000040 +#define MCDE_CONF0_SYNCMUX6(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX6, __x) +#define MCDE_CONF0_SYNCMUX7_SHIFT 7 +#define MCDE_CONF0_SYNCMUX7_MASK 0x00000080 +#define MCDE_CONF0_SYNCMUX7(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX7, __x) +#define MCDE_CONF0_SWAP_A_C0_SHIFT 8 +#define MCDE_CONF0_SWAP_A_C0_MASK 0x00000100 +#define MCDE_CONF0_SWAP_A_C0(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SWAP_A_C0, __x) +#define MCDE_CONF0_SWAP_B_C1_SHIFT 9 +#define MCDE_CONF0_SWAP_B_C1_MASK 0x00000200 +#define MCDE_CONF0_SWAP_B_C1(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SWAP_B_C1, __x) +#define MCDE_CONF0_FSYNCTRLA_SHIFT 10 +#define MCDE_CONF0_FSYNCTRLA_MASK 0x00000400 +#define MCDE_CONF0_FSYNCTRLA(__x) \ + MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLA, __x) +#define MCDE_CONF0_FSYNCTRLB_SHIFT 11 +#define MCDE_CONF0_FSYNCTRLB_MASK 0x00000800 +#define MCDE_CONF0_FSYNCTRLB(__x) \ + MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLB, __x) +#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12 +#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000 +#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL(__x) \ + MCDE_VAL2REG(MCDE_CONF0, IFIFOCTRLWTRMRKLVL, __x) +#define MCDE_CONF0_OUTMUX0_SHIFT 16 +#define MCDE_CONF0_OUTMUX0_MASK 0x00070000 +#define MCDE_CONF0_OUTMUX0(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX0, __x) +#define MCDE_CONF0_OUTMUX1_SHIFT 19 +#define MCDE_CONF0_OUTMUX1_MASK 0x00380000 +#define MCDE_CONF0_OUTMUX1(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX1, __x) +#define MCDE_CONF0_OUTMUX2_SHIFT 22 +#define MCDE_CONF0_OUTMUX2_MASK 0x01C00000 +#define MCDE_CONF0_OUTMUX2(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX2, __x) +#define MCDE_CONF0_OUTMUX3_SHIFT 25 +#define MCDE_CONF0_OUTMUX3_MASK 0x0E000000 +#define MCDE_CONF0_OUTMUX3(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX3, __x) +#define MCDE_CONF0_OUTMUX4_SHIFT 28 +#define MCDE_CONF0_OUTMUX4_MASK 0x70000000 +#define MCDE_CONF0_OUTMUX4(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX4, __x) +#define MCDE_SSP 0x00000008 +#define MCDE_SSP_SSPDATA_SHIFT 0 +#define MCDE_SSP_SSPDATA_MASK 0x000000FF +#define MCDE_SSP_SSPDATA(__x) \ + MCDE_VAL2REG(MCDE_SSP, SSPDATA, __x) +#define MCDE_SSP_SSPCMD_SHIFT 8 +#define MCDE_SSP_SSPCMD_MASK 0x00000100 +#define MCDE_SSP_SSPCMD_DATA 0 +#define MCDE_SSP_SSPCMD_COMMAND 1 +#define MCDE_SSP_SSPCMD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SSP, SSPCMD, MCDE_SSP_SSPCMD_##__x) +#define MCDE_SSP_SSPCMD(__x) \ + MCDE_VAL2REG(MCDE_SSP, SSPCMD, __x) +#define MCDE_SSP_SSPEN_SHIFT 16 +#define MCDE_SSP_SSPEN_MASK 0x00010000 +#define MCDE_SSP_SSPEN(__x) \ + MCDE_VAL2REG(MCDE_SSP, SSPEN, __x) +#define MCDE_AIS 0x00000100 +#define MCDE_AIS_MCDEPPI_SHIFT 0 +#define MCDE_AIS_MCDEPPI_MASK 0x00000001 +#define MCDE_AIS_MCDEPPI(__x) \ + MCDE_VAL2REG(MCDE_AIS, MCDEPPI, __x) +#define MCDE_AIS_MCDEOVLI_SHIFT 1 +#define MCDE_AIS_MCDEOVLI_MASK 0x00000002 +#define MCDE_AIS_MCDEOVLI(__x) \ + MCDE_VAL2REG(MCDE_AIS, MCDEOVLI, __x) +#define MCDE_AIS_MCDECHNLI_SHIFT 2 +#define MCDE_AIS_MCDECHNLI_MASK 0x00000004 +#define MCDE_AIS_MCDECHNLI(__x) \ + MCDE_VAL2REG(MCDE_AIS, MCDECHNLI, __x) +#define MCDE_AIS_MCDEERRI_SHIFT 3 +#define MCDE_AIS_MCDEERRI_MASK 0x00000008 +#define MCDE_AIS_MCDEERRI(__x) \ + MCDE_VAL2REG(MCDE_AIS, MCDEERRI, __x) +#define MCDE_AIS_DSI0AI_SHIFT 4 +#define MCDE_AIS_DSI0AI_MASK 0x00000010 +#define MCDE_AIS_DSI0AI(__x) \ + MCDE_VAL2REG(MCDE_AIS, DSI0AI, __x) +#define MCDE_AIS_DSI1AI_SHIFT 5 +#define MCDE_AIS_DSI1AI_MASK 0x00000020 +#define MCDE_AIS_DSI1AI(__x) \ + MCDE_VAL2REG(MCDE_AIS, DSI1AI, __x) +#define MCDE_AIS_DSI2AI_SHIFT 6 +#define MCDE_AIS_DSI2AI_MASK 0x00000040 +#define MCDE_AIS_DSI2AI(__x) \ + MCDE_VAL2REG(MCDE_AIS, DSI2AI, __x) +#define MCDE_IMSCPP 0x00000104 +#define MCDE_IMSCPP_VCMPAIM_SHIFT 0 +#define MCDE_IMSCPP_VCMPAIM_MASK 0x00000001 +#define MCDE_IMSCPP_VCMPAIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VCMPAIM, __x) +#define MCDE_IMSCPP_VCMPBIM_SHIFT 1 +#define MCDE_IMSCPP_VCMPBIM_MASK 0x00000002 +#define MCDE_IMSCPP_VCMPBIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VCMPBIM, __x) +#define MCDE_IMSCPP_VSCC0IM_SHIFT 2 +#define MCDE_IMSCPP_VSCC0IM_MASK 0x00000004 +#define MCDE_IMSCPP_VSCC0IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VSCC0IM, __x) +#define MCDE_IMSCPP_VSCC1IM_SHIFT 3 +#define MCDE_IMSCPP_VSCC1IM_MASK 0x00000008 +#define MCDE_IMSCPP_VSCC1IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VSCC1IM, __x) +#define MCDE_IMSCPP_VCMPC0IM_SHIFT 4 +#define MCDE_IMSCPP_VCMPC0IM_MASK 0x00000010 +#define MCDE_IMSCPP_VCMPC0IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VCMPC0IM, __x) +#define MCDE_IMSCPP_VCMPC1IM_SHIFT 5 +#define MCDE_IMSCPP_VCMPC1IM_MASK 0x00000020 +#define MCDE_IMSCPP_VCMPC1IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VCMPC1IM, __x) +#define MCDE_IMSCPP_ROTFDIM_B_SHIFT 6 +#define MCDE_IMSCPP_ROTFDIM_B_MASK 0x00000040 +#define MCDE_IMSCPP_ROTFDIM_B(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, ROTFDIM_B, __x) +#define MCDE_IMSCPP_ROTFDIM_A_SHIFT 7 +#define MCDE_IMSCPP_ROTFDIM_A_MASK 0x00000080 +#define MCDE_IMSCPP_ROTFDIM_A(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, ROTFDIM_A, __x) +#define MCDE_IMSCOVL 0x00000108 +#define MCDE_IMSCOVL_OVLRDIM_SHIFT 0 +#define MCDE_IMSCOVL_OVLRDIM_MASK 0x0000FFFF +#define MCDE_IMSCOVL_OVLRDIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCOVL, OVLRDIM, __x) +#define MCDE_IMSCOVL_OVLFDIM_SHIFT 16 +#define MCDE_IMSCOVL_OVLFDIM_MASK 0xFFFF0000 +#define MCDE_IMSCOVL_OVLFDIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCOVL, OVLFDIM, __x) +#define MCDE_IMSCCHNL 0x0000010C +#define MCDE_IMSCCHNL_CHNLRDIM_SHIFT 0 +#define MCDE_IMSCCHNL_CHNLRDIM_MASK 0x0000FFFF +#define MCDE_IMSCCHNL_CHNLRDIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCCHNL, CHNLRDIM, __x) +#define MCDE_IMSCCHNL_CHNLAIM_SHIFT 16 +#define MCDE_IMSCCHNL_CHNLAIM_MASK 0xFFFF0000 +#define MCDE_IMSCCHNL_CHNLAIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCCHNL, CHNLAIM, __x) +#define MCDE_IMSCERR 0x00000110 +#define MCDE_IMSCERR_FUAIM_SHIFT 0 +#define MCDE_IMSCERR_FUAIM_MASK 0x00000001 +#define MCDE_IMSCERR_FUAIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, FUAIM, __x) +#define MCDE_IMSCERR_FUBIM_SHIFT 1 +#define MCDE_IMSCERR_FUBIM_MASK 0x00000002 +#define MCDE_IMSCERR_FUBIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, FUBIM, __x) +#define MCDE_IMSCERR_SCHBLCKDIM_SHIFT 2 +#define MCDE_IMSCERR_SCHBLCKDIM_MASK 0x00000004 +#define MCDE_IMSCERR_SCHBLCKDIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, SCHBLCKDIM, __x) +#define MCDE_IMSCERR_ROTAFEIM_WRITE_SHIFT 3 +#define MCDE_IMSCERR_ROTAFEIM_WRITE_MASK 0x00000008 +#define MCDE_IMSCERR_ROTAFEIM_WRITE(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, ROTAFEIM_WRITE, __x) +#define MCDE_IMSCERR_ROTAFEIM_READ_SHIFT 4 +#define MCDE_IMSCERR_ROTAFEIM_READ_MASK 0x00000010 +#define MCDE_IMSCERR_ROTAFEIM_READ(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, ROTAFEIM_READ, __x) +#define MCDE_IMSCERR_ROTBFEIM_WRITE_SHIFT 5 +#define MCDE_IMSCERR_ROTBFEIM_WRITE_MASK 0x00000020 +#define MCDE_IMSCERR_ROTBFEIM_WRITE(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, ROTBFEIM_WRITE, __x) +#define MCDE_IMSCERR_ROTBFEIM_READ_SHIFT 6 +#define MCDE_IMSCERR_ROTBFEIM_READ_MASK 0x00000040 +#define MCDE_IMSCERR_ROTBFEIM_READ(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, ROTBFEIM_READ, __x) +#define MCDE_IMSCERR_FUC0IM_SHIFT 7 +#define MCDE_IMSCERR_FUC0IM_MASK 0x00000080 +#define MCDE_IMSCERR_FUC0IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, FUC0IM, __x) +#define MCDE_IMSCERR_FUC1IM_SHIFT 8 +#define MCDE_IMSCERR_FUC1IM_MASK 0x00000100 +#define MCDE_IMSCERR_FUC1IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, FUC1IM, __x) +#define MCDE_IMSCERR_OVLFERRIM_SHIFT 16 +#define MCDE_IMSCERR_OVLFERRIM_MASK 0xFFFF0000 +#define MCDE_IMSCERR_OVLFERRIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, OVLFERRIM, __x) +#define MCDE_RISPP 0x00000114 +#define MCDE_RISPP_VCMPARIS_SHIFT 0 +#define MCDE_RISPP_VCMPARIS_MASK 0x00000001 +#define MCDE_RISPP_VCMPARIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VCMPARIS, __x) +#define MCDE_RISPP_VCMPBRIS_SHIFT 1 +#define MCDE_RISPP_VCMPBRIS_MASK 0x00000002 +#define MCDE_RISPP_VCMPBRIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VCMPBRIS, __x) +#define MCDE_RISPP_VSCC0RIS_SHIFT 2 +#define MCDE_RISPP_VSCC0RIS_MASK 0x00000004 +#define MCDE_RISPP_VSCC0RIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VSCC0RIS, __x) +#define MCDE_RISPP_VSCC1RIS_SHIFT 3 +#define MCDE_RISPP_VSCC1RIS_MASK 0x00000008 +#define MCDE_RISPP_VSCC1RIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VSCC1RIS, __x) +#define MCDE_RISPP_VCMPC0RIS_SHIFT 4 +#define MCDE_RISPP_VCMPC0RIS_MASK 0x00000010 +#define MCDE_RISPP_VCMPC0RIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VCMPC0RIS, __x) +#define MCDE_RISPP_VCMPC1RIS_SHIFT 5 +#define MCDE_RISPP_VCMPC1RIS_MASK 0x00000020 +#define MCDE_RISPP_VCMPC1RIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VCMPC1RIS, __x) +#define MCDE_RISPP_ROTFDRIS_B_SHIFT 6 +#define MCDE_RISPP_ROTFDRIS_B_MASK 0x00000040 +#define MCDE_RISPP_ROTFDRIS_B(__x) \ + MCDE_VAL2REG(MCDE_RISPP, ROTFDRIS_B, __x) +#define MCDE_RISPP_ROTFDRIS_A_SHIFT 7 +#define MCDE_RISPP_ROTFDRIS_A_MASK 0x00000080 +#define MCDE_RISPP_ROTFDRIS_A(__x) \ + MCDE_VAL2REG(MCDE_RISPP, ROTFDRIS_A, __x) +#define MCDE_RISOVL 0x00000118 +#define MCDE_RISOVL_OVLRDRIS_SHIFT 0 +#define MCDE_RISOVL_OVLRDRIS_MASK 0x0000FFFF +#define MCDE_RISOVL_OVLRDRIS(__x) \ + MCDE_VAL2REG(MCDE_RISOVL, OVLRDRIS, __x) +#define MCDE_RISOVL_OVLFDRIS_SHIFT 16 +#define MCDE_RISOVL_OVLFDRIS_MASK 0xFFFF0000 +#define MCDE_RISOVL_OVLFDRIS(__x) \ + MCDE_VAL2REG(MCDE_RISOVL, OVLFDRIS, __x) +#define MCDE_RISCHNL 0x0000011C +#define MCDE_RISCHNL_CHNLRDRIS_SHIFT 0 +#define MCDE_RISCHNL_CHNLRDRIS_MASK 0x0000FFFF +#define MCDE_RISCHNL_CHNLRDRIS(__x) \ + MCDE_VAL2REG(MCDE_RISCHNL, CHNLRDRIS, __x) +#define MCDE_RISCHNL_CHNLARIS_SHIFT 16 +#define MCDE_RISCHNL_CHNLARIS_MASK 0xFFFF0000 +#define MCDE_RISCHNL_CHNLARIS(__x) \ + MCDE_VAL2REG(MCDE_RISCHNL, CHNLARIS, __x) +#define MCDE_RISERR 0x00000120 +#define MCDE_RISERR_FUARIS_SHIFT 0 +#define MCDE_RISERR_FUARIS_MASK 0x00000001 +#define MCDE_RISERR_FUARIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, FUARIS, __x) +#define MCDE_RISERR_FUBRIS_SHIFT 1 +#define MCDE_RISERR_FUBRIS_MASK 0x00000002 +#define MCDE_RISERR_FUBRIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, FUBRIS, __x) +#define MCDE_RISERR_SCHBLCKDRIS_SHIFT 2 +#define MCDE_RISERR_SCHBLCKDRIS_MASK 0x00000004 +#define MCDE_RISERR_SCHBLCKDRIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, SCHBLCKDRIS, __x) +#define MCDE_RISERR_ROTAFERIS_WRITE_SHIFT 3 +#define MCDE_RISERR_ROTAFERIS_WRITE_MASK 0x00000008 +#define MCDE_RISERR_ROTAFERIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_RISERR, ROTAFERIS_WRITE, __x) +#define MCDE_RISERR_ROTAFERIS_READ_SHIFT 4 +#define MCDE_RISERR_ROTAFERIS_READ_MASK 0x00000010 +#define MCDE_RISERR_ROTAFERIS_READ(__x) \ + MCDE_VAL2REG(MCDE_RISERR, ROTAFERIS_READ, __x) +#define MCDE_RISERR_ROTBFERIS_WRITE_SHIFT 5 +#define MCDE_RISERR_ROTBFERIS_WRITE_MASK 0x00000020 +#define MCDE_RISERR_ROTBFERIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_RISERR, ROTBFERIS_WRITE, __x) +#define MCDE_RISERR_ROTBFERIS_READ_SHIFT 6 +#define MCDE_RISERR_ROTBFERIS_READ_MASK 0x00000040 +#define MCDE_RISERR_ROTBFERIS_READ(__x) \ + MCDE_VAL2REG(MCDE_RISERR, ROTBFERIS_READ, __x) +#define MCDE_RISERR_FUC0RIS_SHIFT 7 +#define MCDE_RISERR_FUC0RIS_MASK 0x00000080 +#define MCDE_RISERR_FUC0RIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, FUC0RIS, __x) +#define MCDE_RISERR_FUC1RIS_SHIFT 8 +#define MCDE_RISERR_FUC1RIS_MASK 0x00000100 +#define MCDE_RISERR_FUC1RIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, FUC1RIS, __x) +#define MCDE_RISERR_OVLFERRRIS_SHIFT 16 +#define MCDE_RISERR_OVLFERRRIS_MASK 0xFFFF0000 +#define MCDE_RISERR_OVLFERRRIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, OVLFERRRIS, __x) +#define MCDE_MISPP 0x00000124 +#define MCDE_MISPP_VCMPAMIS_SHIFT 0 +#define MCDE_MISPP_VCMPAMIS_MASK 0x00000001 +#define MCDE_MISPP_VCMPAMIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VCMPAMIS, __x) +#define MCDE_MISPP_VCMPBMIS_SHIFT 1 +#define MCDE_MISPP_VCMPBMIS_MASK 0x00000002 +#define MCDE_MISPP_VCMPBMIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VCMPBMIS, __x) +#define MCDE_MISPP_VSCC0MIS_SHIFT 2 +#define MCDE_MISPP_VSCC0MIS_MASK 0x00000004 +#define MCDE_MISPP_VSCC0MIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VSCC0MIS, __x) +#define MCDE_MISPP_VSCC1MIS_SHIFT 3 +#define MCDE_MISPP_VSCC1MIS_MASK 0x00000008 +#define MCDE_MISPP_VSCC1MIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VSCC1MIS, __x) +#define MCDE_MISPP_VCMPC0MIS_SHIFT 4 +#define MCDE_MISPP_VCMPC0MIS_MASK 0x00000010 +#define MCDE_MISPP_VCMPC0MIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VCMPC0MIS, __x) +#define MCDE_MISPP_VCMPC1MIS_SHIFT 5 +#define MCDE_MISPP_VCMPC1MIS_MASK 0x00000020 +#define MCDE_MISPP_VCMPC1MIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VCMPC1MIS, __x) +#define MCDE_MISPP_ROTFDMIS_A_SHIFT 6 +#define MCDE_MISPP_ROTFDMIS_A_MASK 0x00000040 +#define MCDE_MISPP_ROTFDMIS_A(__x) \ + MCDE_VAL2REG(MCDE_MISPP, ROTFDMIS_A, __x) +#define MCDE_MISPP_ROTFDMIS_B_SHIFT 7 +#define MCDE_MISPP_ROTFDMIS_B_MASK 0x00000080 +#define MCDE_MISPP_ROTFDMIS_B(__x) \ + MCDE_VAL2REG(MCDE_MISPP, ROTFDMIS_B, __x) +#define MCDE_MISOVL 0x00000128 +#define MCDE_MISOVL_OVLRDMIS_SHIFT 0 +#define MCDE_MISOVL_OVLRDMIS_MASK 0x0000FFFF +#define MCDE_MISOVL_OVLRDMIS(__x) \ + MCDE_VAL2REG(MCDE_MISOVL, OVLRDMIS, __x) +#define MCDE_MISOVL_OVLFDMIS_SHIFT 16 +#define MCDE_MISOVL_OVLFDMIS_MASK 0xFFFF0000 +#define MCDE_MISOVL_OVLFDMIS(__x) \ + MCDE_VAL2REG(MCDE_MISOVL, OVLFDMIS, __x) +#define MCDE_MISCHNL 0x0000012C +#define MCDE_MISCHNL_CHNLRDMIS_SHIFT 0 +#define MCDE_MISCHNL_CHNLRDMIS_MASK 0x0000FFFF +#define MCDE_MISCHNL_CHNLRDMIS(__x) \ + MCDE_VAL2REG(MCDE_MISCHNL, CHNLRDMIS, __x) +#define MCDE_MISCHNL_CHNLAMIS_SHIFT 16 +#define MCDE_MISCHNL_CHNLAMIS_MASK 0xFFFF0000 +#define MCDE_MISCHNL_CHNLAMIS(__x) \ + MCDE_VAL2REG(MCDE_MISCHNL, CHNLAMIS, __x) +#define MCDE_MISERR 0x00000130 +#define MCDE_MISERR_FUAMIS_SHIFT 0 +#define MCDE_MISERR_FUAMIS_MASK 0x00000001 +#define MCDE_MISERR_FUAMIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, FUAMIS, __x) +#define MCDE_MISERR_FUBMIS_SHIFT 1 +#define MCDE_MISERR_FUBMIS_MASK 0x00000002 +#define MCDE_MISERR_FUBMIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, FUBMIS, __x) +#define MCDE_MISERR_SCHBLCKDMIS_SHIFT 2 +#define MCDE_MISERR_SCHBLCKDMIS_MASK 0x00000004 +#define MCDE_MISERR_SCHBLCKDMIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, SCHBLCKDMIS, __x) +#define MCDE_MISERR_ROTAFEMIS_WRITE_SHIFT 3 +#define MCDE_MISERR_ROTAFEMIS_WRITE_MASK 0x00000008 +#define MCDE_MISERR_ROTAFEMIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_MISERR, ROTAFEMIS_WRITE, __x) +#define MCDE_MISERR_ROTAFEMIS_READ_SHIFT 4 +#define MCDE_MISERR_ROTAFEMIS_READ_MASK 0x00000010 +#define MCDE_MISERR_ROTAFEMIS_READ(__x) \ + MCDE_VAL2REG(MCDE_MISERR, ROTAFEMIS_READ, __x) +#define MCDE_MISERR_ROTBFEMIS_WRITE_SHIFT 5 +#define MCDE_MISERR_ROTBFEMIS_WRITE_MASK 0x00000020 +#define MCDE_MISERR_ROTBFEMIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_MISERR, ROTBFEMIS_WRITE, __x) +#define MCDE_MISERR_ROTBFEMIS_READ_SHIFT 6 +#define MCDE_MISERR_ROTBFEMIS_READ_MASK 0x00000040 +#define MCDE_MISERR_ROTBFEMIS_READ(__x) \ + MCDE_VAL2REG(MCDE_MISERR, ROTBFEMIS_READ, __x) +#define MCDE_MISERR_FUC0MIS_SHIFT 7 +#define MCDE_MISERR_FUC0MIS_MASK 0x00000080 +#define MCDE_MISERR_FUC0MIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, FUC0MIS, __x) +#define MCDE_MISERR_FUC1MIS_SHIFT 8 +#define MCDE_MISERR_FUC1MIS_MASK 0x00000100 +#define MCDE_MISERR_FUC1MIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, FUC1MIS, __x) +#define MCDE_MISERR_OVLFERMIS_SHIFT 16 +#define MCDE_MISERR_OVLFERMIS_MASK 0xFFFF0000 +#define MCDE_MISERR_OVLFERMIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, OVLFERMIS, __x) +#define MCDE_SISPP 0x00000134 +#define MCDE_SISPP_VCMPASIS_SHIFT 0 +#define MCDE_SISPP_VCMPASIS_MASK 0x00000001 +#define MCDE_SISPP_VCMPASIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VCMPASIS, __x) +#define MCDE_SISPP_VCMPBSIS_SHIFT 1 +#define MCDE_SISPP_VCMPBSIS_MASK 0x00000002 +#define MCDE_SISPP_VCMPBSIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VCMPBSIS, __x) +#define MCDE_SISPP_VSCC0SIS_SHIFT 2 +#define MCDE_SISPP_VSCC0SIS_MASK 0x00000004 +#define MCDE_SISPP_VSCC0SIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VSCC0SIS, __x) +#define MCDE_SISPP_VSCC1SIS_SHIFT 3 +#define MCDE_SISPP_VSCC1SIS_MASK 0x00000008 +#define MCDE_SISPP_VSCC1SIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VSCC1SIS, __x) +#define MCDE_SISPP_VCMPC0SIS_SHIFT 4 +#define MCDE_SISPP_VCMPC0SIS_MASK 0x00000010 +#define MCDE_SISPP_VCMPC0SIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VCMPC0SIS, __x) +#define MCDE_SISPP_VCMPC1SIS_SHIFT 5 +#define MCDE_SISPP_VCMPC1SIS_MASK 0x00000020 +#define MCDE_SISPP_VCMPC1SIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VCMPC1SIS, __x) +#define MCDE_SISPP_ROTFDSIS_A_SHIFT 6 +#define MCDE_SISPP_ROTFDSIS_A_MASK 0x00000040 +#define MCDE_SISPP_ROTFDSIS_A(__x) \ + MCDE_VAL2REG(MCDE_SISPP, ROTFDSIS_A, __x) +#define MCDE_SISPP_ROTFDSIS_B_SHIFT 7 +#define MCDE_SISPP_ROTFDSIS_B_MASK 0x00000080 +#define MCDE_SISPP_ROTFDSIS_B(__x) \ + MCDE_VAL2REG(MCDE_SISPP, ROTFDSIS_B, __x) +#define MCDE_SISOVL 0x00000138 +#define MCDE_SISOVL_OVLRDSIS_SHIFT 0 +#define MCDE_SISOVL_OVLRDSIS_MASK 0x0000FFFF +#define MCDE_SISOVL_OVLRDSIS(__x) \ + MCDE_VAL2REG(MCDE_SISOVL, OVLRDSIS, __x) +#define MCDE_SISOVL_OVLFDSIS_SHIFT 16 +#define MCDE_SISOVL_OVLFDSIS_MASK 0xFFFF0000 +#define MCDE_SISOVL_OVLFDSIS(__x) \ + MCDE_VAL2REG(MCDE_SISOVL, OVLFDSIS, __x) +#define MCDE_SISCHNL 0x0000013C +#define MCDE_SISCHNL_CHNLRDSIS_SHIFT 0 +#define MCDE_SISCHNL_CHNLRDSIS_MASK 0x0000FFFF +#define MCDE_SISCHNL_CHNLRDSIS(__x) \ + MCDE_VAL2REG(MCDE_SISCHNL, CHNLRDSIS, __x) +#define MCDE_SISCHNL_CHNLASIS_SHIFT 16 +#define MCDE_SISCHNL_CHNLASIS_MASK 0xFFFF0000 +#define MCDE_SISCHNL_CHNLASIS(__x) \ + MCDE_VAL2REG(MCDE_SISCHNL, CHNLASIS, __x) +#define MCDE_SISERR 0x00000140 +#define MCDE_SISERR_FUASIS_SHIFT 0 +#define MCDE_SISERR_FUASIS_MASK 0x00000001 +#define MCDE_SISERR_FUASIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, FUASIS, __x) +#define MCDE_SISERR_FUBSIS_SHIFT 1 +#define MCDE_SISERR_FUBSIS_MASK 0x00000002 +#define MCDE_SISERR_FUBSIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, FUBSIS, __x) +#define MCDE_SISERR_SCHBLCKDSIS_SHIFT 2 +#define MCDE_SISERR_SCHBLCKDSIS_MASK 0x00000004 +#define MCDE_SISERR_SCHBLCKDSIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, SCHBLCKDSIS, __x) +#define MCDE_SISERR_ROTAFESIS_WRITE_SHIFT 3 +#define MCDE_SISERR_ROTAFESIS_WRITE_MASK 0x00000008 +#define MCDE_SISERR_ROTAFESIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_SISERR, ROTAFESIS_WRITE, __x) +#define MCDE_SISERR_ROTAFESIS_READ_SHIFT 4 +#define MCDE_SISERR_ROTAFESIS_READ_MASK 0x00000010 +#define MCDE_SISERR_ROTAFESIS_READ(__x) \ + MCDE_VAL2REG(MCDE_SISERR, ROTAFESIS_READ, __x) +#define MCDE_SISERR_ROTBFESIS_WRITE_SHIFT 5 +#define MCDE_SISERR_ROTBFESIS_WRITE_MASK 0x00000020 +#define MCDE_SISERR_ROTBFESIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_SISERR, ROTBFESIS_WRITE, __x) +#define MCDE_SISERR_ROTBFESIS_READ_SHIFT 6 +#define MCDE_SISERR_ROTBFESIS_READ_MASK 0x00000040 +#define MCDE_SISERR_ROTBFESIS_READ(__x) \ + MCDE_VAL2REG(MCDE_SISERR, ROTBFESIS_READ, __x) +#define MCDE_SISERR_FUC0SIS_SHIFT 7 +#define MCDE_SISERR_FUC0SIS_MASK 0x00000080 +#define MCDE_SISERR_FUC0SIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, FUC0SIS, __x) +#define MCDE_SISERR_FUC1SIS_SHIFT 8 +#define MCDE_SISERR_FUC1SIS_MASK 0x00000100 +#define MCDE_SISERR_FUC1SIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, FUC1SIS, __x) +#define MCDE_SISERR_OVLFERSIS_SHIFT 16 +#define MCDE_SISERR_OVLFERSIS_MASK 0xFFFF0000 +#define MCDE_SISERR_OVLFERSIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, OVLFERSIS, __x) +#define MCDE_PID 0x000001FC +#define MCDE_PID_METALFIX_VERSION_SHIFT 0 +#define MCDE_PID_METALFIX_VERSION_MASK 0x000000FF +#define MCDE_PID_METALFIX_VERSION(__x) \ + MCDE_VAL2REG(MCDE_PID, METALFIX_VERSION, __x) +#define MCDE_PID_DEVELOPMENT_VERSION_SHIFT 8 +#define MCDE_PID_DEVELOPMENT_VERSION_MASK 0x0000FF00 +#define MCDE_PID_DEVELOPMENT_VERSION(__x) \ + MCDE_VAL2REG(MCDE_PID, DEVELOPMENT_VERSION, __x) +#define MCDE_PID_MINOR_VERSION_SHIFT 16 +#define MCDE_PID_MINOR_VERSION_MASK 0x00FF0000 +#define MCDE_PID_MINOR_VERSION(__x) \ + MCDE_VAL2REG(MCDE_PID, MINOR_VERSION, __x) +#define MCDE_PID_MAJOR_VERSION_SHIFT 24 +#define MCDE_PID_MAJOR_VERSION_MASK 0xFF000000 +#define MCDE_PID_MAJOR_VERSION(__x) \ + MCDE_VAL2REG(MCDE_PID, MAJOR_VERSION, __x) +#define MCDE_EXTSRC0A0 0x00000200 +#define MCDE_EXTSRC0A0_GROUPOFFSET 0x20 +#define MCDE_EXTSRC0A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC0A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC0A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC1A0 0x00000220 +#define MCDE_EXTSRC1A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC1A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC1A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC2A0 0x00000240 +#define MCDE_EXTSRC2A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC2A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC2A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC3A0 0x00000260 +#define MCDE_EXTSRC3A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC3A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC3A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC4A0 0x00000280 +#define MCDE_EXTSRC4A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC4A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC4A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC5A0 0x000002A0 +#define MCDE_EXTSRC5A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC5A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC5A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC6A0 0x000002C0 +#define MCDE_EXTSRC6A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC6A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC6A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC7A0 0x000002E0 +#define MCDE_EXTSRC7A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC7A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC7A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC8A0 0x00000300 +#define MCDE_EXTSRC8A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC8A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC8A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC9A0 0x00000320 +#define MCDE_EXTSRC9A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC9A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC9A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC0A1 0x00000204 +#define MCDE_EXTSRC0A1_GROUPOFFSET 0x20 +#define MCDE_EXTSRC0A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC0A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC0A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC1A1 0x00000224 +#define MCDE_EXTSRC1A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC1A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC1A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC2A1 0x00000244 +#define MCDE_EXTSRC2A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC2A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC2A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC3A1 0x00000264 +#define MCDE_EXTSRC3A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC3A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC3A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC4A1 0x00000284 +#define MCDE_EXTSRC4A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC4A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC4A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC5A1 0x000002A4 +#define MCDE_EXTSRC5A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC5A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC5A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC6A1 0x000002C4 +#define MCDE_EXTSRC6A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC6A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC6A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC7A1 0x000002E4 +#define MCDE_EXTSRC7A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC7A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC7A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC8A1 0x00000304 +#define MCDE_EXTSRC8A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC8A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC8A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC9A1 0x00000324 +#define MCDE_EXTSRC9A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC9A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC9A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC6A2 0x000002C8 +#define MCDE_EXTSRC6A2_BASEADDRESS2_SHIFT 0 +#define MCDE_EXTSRC6A2_BASEADDRESS2_MASK 0xFFFFFFFF +#define MCDE_EXTSRC6A2_BASEADDRESS2(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6A2, BASEADDRESS2, __x) +#define MCDE_EXTSRC0CONF 0x0000020C +#define MCDE_EXTSRC0CONF_GROUPOFFSET 0x20 +#define MCDE_EXTSRC0CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC0CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC0CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BUF_ID, __x) +#define MCDE_EXTSRC0CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC0CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC0CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BUF_NB, __x) +#define MCDE_EXTSRC0CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC0CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC0CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC0CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC0CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC0CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC0CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC0CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC0CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC0CONF_BPP_RGB444 4 +#define MCDE_EXTSRC0CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC0CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC0CONF_BPP_RGB565 7 +#define MCDE_EXTSRC0CONF_BPP_RGB888 8 +#define MCDE_EXTSRC0CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC0CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC0CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC0CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BPP, MCDE_EXTSRC0CONF_BPP_##__x) +#define MCDE_EXTSRC0CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BPP, __x) +#define MCDE_EXTSRC0CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC0CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC0CONF_BGR_RGB 0 +#define MCDE_EXTSRC0CONF_BGR_BGR 1 +#define MCDE_EXTSRC0CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BGR, MCDE_EXTSRC0CONF_BGR_##__x) +#define MCDE_EXTSRC0CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BGR, __x) +#define MCDE_EXTSRC0CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC0CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC0CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC0CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC0CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BEBO, MCDE_EXTSRC0CONF_BEBO_##__x) +#define MCDE_EXTSRC0CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BEBO, __x) +#define MCDE_EXTSRC0CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC0CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC0CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC0CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC0CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BEPO, MCDE_EXTSRC0CONF_BEPO_##__x) +#define MCDE_EXTSRC0CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BEPO, __x) +#define MCDE_EXTSRC1CONF 0x0000022C +#define MCDE_EXTSRC1CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC1CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC1CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BUF_ID, __x) +#define MCDE_EXTSRC1CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC1CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC1CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BUF_NB, __x) +#define MCDE_EXTSRC1CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC1CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC1CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC1CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC1CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC1CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC1CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC1CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC1CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC1CONF_BPP_RGB444 4 +#define MCDE_EXTSRC1CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC1CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC1CONF_BPP_RGB565 7 +#define MCDE_EXTSRC1CONF_BPP_RGB888 8 +#define MCDE_EXTSRC1CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC1CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC1CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC1CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BPP, MCDE_EXTSRC1CONF_BPP_##__x) +#define MCDE_EXTSRC1CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BPP, __x) +#define MCDE_EXTSRC1CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC1CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC1CONF_BGR_RGB 0 +#define MCDE_EXTSRC1CONF_BGR_BGR 1 +#define MCDE_EXTSRC1CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BGR, MCDE_EXTSRC1CONF_BGR_##__x) +#define MCDE_EXTSRC1CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BGR, __x) +#define MCDE_EXTSRC1CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC1CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC1CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC1CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC1CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BEBO, MCDE_EXTSRC1CONF_BEBO_##__x) +#define MCDE_EXTSRC1CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BEBO, __x) +#define MCDE_EXTSRC1CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC1CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC1CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC1CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC1CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BEPO, MCDE_EXTSRC1CONF_BEPO_##__x) +#define MCDE_EXTSRC1CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BEPO, __x) +#define MCDE_EXTSRC2CONF 0x0000024C +#define MCDE_EXTSRC2CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC2CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC2CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BUF_ID, __x) +#define MCDE_EXTSRC2CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC2CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC2CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BUF_NB, __x) +#define MCDE_EXTSRC2CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC2CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC2CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC2CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC2CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC2CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC2CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC2CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC2CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC2CONF_BPP_RGB444 4 +#define MCDE_EXTSRC2CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC2CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC2CONF_BPP_RGB565 7 +#define MCDE_EXTSRC2CONF_BPP_RGB888 8 +#define MCDE_EXTSRC2CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC2CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC2CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC2CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BPP, MCDE_EXTSRC2CONF_BPP_##__x) +#define MCDE_EXTSRC2CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BPP, __x) +#define MCDE_EXTSRC2CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC2CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC2CONF_BGR_RGB 0 +#define MCDE_EXTSRC2CONF_BGR_BGR 1 +#define MCDE_EXTSRC2CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BGR, MCDE_EXTSRC2CONF_BGR_##__x) +#define MCDE_EXTSRC2CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BGR, __x) +#define MCDE_EXTSRC2CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC2CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC2CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC2CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC2CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BEBO, MCDE_EXTSRC2CONF_BEBO_##__x) +#define MCDE_EXTSRC2CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BEBO, __x) +#define MCDE_EXTSRC2CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC2CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC2CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC2CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC2CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BEPO, MCDE_EXTSRC2CONF_BEPO_##__x) +#define MCDE_EXTSRC2CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BEPO, __x) +#define MCDE_EXTSRC3CONF 0x0000026C +#define MCDE_EXTSRC3CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC3CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC3CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BUF_ID, __x) +#define MCDE_EXTSRC3CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC3CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC3CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BUF_NB, __x) +#define MCDE_EXTSRC3CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC3CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC3CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC3CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC3CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC3CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC3CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC3CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC3CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC3CONF_BPP_RGB444 4 +#define MCDE_EXTSRC3CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC3CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC3CONF_BPP_RGB565 7 +#define MCDE_EXTSRC3CONF_BPP_RGB888 8 +#define MCDE_EXTSRC3CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC3CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC3CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC3CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BPP, MCDE_EXTSRC3CONF_BPP_##__x) +#define MCDE_EXTSRC3CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BPP, __x) +#define MCDE_EXTSRC3CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC3CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC3CONF_BGR_RGB 0 +#define MCDE_EXTSRC3CONF_BGR_BGR 1 +#define MCDE_EXTSRC3CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BGR, MCDE_EXTSRC3CONF_BGR_##__x) +#define MCDE_EXTSRC3CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BGR, __x) +#define MCDE_EXTSRC3CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC3CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC3CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC3CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC3CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BEBO, MCDE_EXTSRC3CONF_BEBO_##__x) +#define MCDE_EXTSRC3CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BEBO, __x) +#define MCDE_EXTSRC3CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC3CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC3CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC3CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC3CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BEPO, MCDE_EXTSRC3CONF_BEPO_##__x) +#define MCDE_EXTSRC3CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BEPO, __x) +#define MCDE_EXTSRC4CONF 0x0000028C +#define MCDE_EXTSRC4CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC4CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC4CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BUF_ID, __x) +#define MCDE_EXTSRC4CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC4CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC4CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BUF_NB, __x) +#define MCDE_EXTSRC4CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC4CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC4CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC4CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC4CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC4CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC4CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC4CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC4CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC4CONF_BPP_RGB444 4 +#define MCDE_EXTSRC4CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC4CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC4CONF_BPP_RGB565 7 +#define MCDE_EXTSRC4CONF_BPP_RGB888 8 +#define MCDE_EXTSRC4CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC4CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC4CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC4CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BPP, MCDE_EXTSRC4CONF_BPP_##__x) +#define MCDE_EXTSRC4CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BPP, __x) +#define MCDE_EXTSRC4CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC4CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC4CONF_BGR_RGB 0 +#define MCDE_EXTSRC4CONF_BGR_BGR 1 +#define MCDE_EXTSRC4CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BGR, MCDE_EXTSRC4CONF_BGR_##__x) +#define MCDE_EXTSRC4CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BGR, __x) +#define MCDE_EXTSRC4CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC4CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC4CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC4CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC4CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BEBO, MCDE_EXTSRC4CONF_BEBO_##__x) +#define MCDE_EXTSRC4CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BEBO, __x) +#define MCDE_EXTSRC4CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC4CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC4CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC4CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC4CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BEPO, MCDE_EXTSRC4CONF_BEPO_##__x) +#define MCDE_EXTSRC4CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BEPO, __x) +#define MCDE_EXTSRC5CONF 0x000002AC +#define MCDE_EXTSRC5CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC5CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC5CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BUF_ID, __x) +#define MCDE_EXTSRC5CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC5CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC5CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BUF_NB, __x) +#define MCDE_EXTSRC5CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC5CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC5CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC5CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC5CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC5CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC5CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC5CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC5CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC5CONF_BPP_RGB444 4 +#define MCDE_EXTSRC5CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC5CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC5CONF_BPP_RGB565 7 +#define MCDE_EXTSRC5CONF_BPP_RGB888 8 +#define MCDE_EXTSRC5CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC5CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC5CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC5CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BPP, MCDE_EXTSRC5CONF_BPP_##__x) +#define MCDE_EXTSRC5CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BPP, __x) +#define MCDE_EXTSRC5CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC5CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC5CONF_BGR_RGB 0 +#define MCDE_EXTSRC5CONF_BGR_BGR 1 +#define MCDE_EXTSRC5CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BGR, MCDE_EXTSRC5CONF_BGR_##__x) +#define MCDE_EXTSRC5CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BGR, __x) +#define MCDE_EXTSRC5CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC5CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC5CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC5CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC5CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BEBO, MCDE_EXTSRC5CONF_BEBO_##__x) +#define MCDE_EXTSRC5CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BEBO, __x) +#define MCDE_EXTSRC5CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC5CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC5CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC5CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC5CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BEPO, MCDE_EXTSRC5CONF_BEPO_##__x) +#define MCDE_EXTSRC5CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BEPO, __x) +#define MCDE_EXTSRC6CONF 0x000002CC +#define MCDE_EXTSRC6CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC6CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC6CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BUF_ID, __x) +#define MCDE_EXTSRC6CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC6CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC6CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BUF_NB, __x) +#define MCDE_EXTSRC6CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC6CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC6CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC6CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC6CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC6CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC6CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC6CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC6CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC6CONF_BPP_RGB444 4 +#define MCDE_EXTSRC6CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC6CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC6CONF_BPP_RGB565 7 +#define MCDE_EXTSRC6CONF_BPP_RGB888 8 +#define MCDE_EXTSRC6CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC6CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC6CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC6CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BPP, MCDE_EXTSRC6CONF_BPP_##__x) +#define MCDE_EXTSRC6CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BPP, __x) +#define MCDE_EXTSRC6CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC6CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC6CONF_BGR_RGB 0 +#define MCDE_EXTSRC6CONF_BGR_BGR 1 +#define MCDE_EXTSRC6CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BGR, MCDE_EXTSRC6CONF_BGR_##__x) +#define MCDE_EXTSRC6CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BGR, __x) +#define MCDE_EXTSRC6CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC6CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC6CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC6CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC6CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BEBO, MCDE_EXTSRC6CONF_BEBO_##__x) +#define MCDE_EXTSRC6CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BEBO, __x) +#define MCDE_EXTSRC6CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC6CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC6CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC6CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC6CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BEPO, MCDE_EXTSRC6CONF_BEPO_##__x) +#define MCDE_EXTSRC6CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BEPO, __x) +#define MCDE_EXTSRC7CONF 0x000002EC +#define MCDE_EXTSRC7CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC7CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC7CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BUF_ID, __x) +#define MCDE_EXTSRC7CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC7CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC7CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BUF_NB, __x) +#define MCDE_EXTSRC7CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC7CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC7CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC7CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC7CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC7CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC7CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC7CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC7CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC7CONF_BPP_RGB444 4 +#define MCDE_EXTSRC7CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC7CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC7CONF_BPP_RGB565 7 +#define MCDE_EXTSRC7CONF_BPP_RGB888 8 +#define MCDE_EXTSRC7CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC7CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC7CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC7CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BPP, MCDE_EXTSRC7CONF_BPP_##__x) +#define MCDE_EXTSRC7CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BPP, __x) +#define MCDE_EXTSRC7CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC7CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC7CONF_BGR_RGB 0 +#define MCDE_EXTSRC7CONF_BGR_BGR 1 +#define MCDE_EXTSRC7CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BGR, MCDE_EXTSRC7CONF_BGR_##__x) +#define MCDE_EXTSRC7CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BGR, __x) +#define MCDE_EXTSRC7CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC7CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC7CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC7CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC7CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BEBO, MCDE_EXTSRC7CONF_BEBO_##__x) +#define MCDE_EXTSRC7CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BEBO, __x) +#define MCDE_EXTSRC7CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC7CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC7CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC7CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC7CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BEPO, MCDE_EXTSRC7CONF_BEPO_##__x) +#define MCDE_EXTSRC7CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BEPO, __x) +#define MCDE_EXTSRC8CONF 0x0000030C +#define MCDE_EXTSRC8CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC8CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC8CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BUF_ID, __x) +#define MCDE_EXTSRC8CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC8CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC8CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BUF_NB, __x) +#define MCDE_EXTSRC8CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC8CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC8CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC8CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC8CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC8CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC8CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC8CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC8CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC8CONF_BPP_RGB444 4 +#define MCDE_EXTSRC8CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC8CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC8CONF_BPP_RGB565 7 +#define MCDE_EXTSRC8CONF_BPP_RGB888 8 +#define MCDE_EXTSRC8CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC8CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC8CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC8CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BPP, MCDE_EXTSRC8CONF_BPP_##__x) +#define MCDE_EXTSRC8CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BPP, __x) +#define MCDE_EXTSRC8CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC8CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC8CONF_BGR_RGB 0 +#define MCDE_EXTSRC8CONF_BGR_BGR 1 +#define MCDE_EXTSRC8CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BGR, MCDE_EXTSRC8CONF_BGR_##__x) +#define MCDE_EXTSRC8CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BGR, __x) +#define MCDE_EXTSRC8CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC8CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC8CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC8CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC8CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BEBO, MCDE_EXTSRC8CONF_BEBO_##__x) +#define MCDE_EXTSRC8CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BEBO, __x) +#define MCDE_EXTSRC8CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC8CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC8CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC8CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC8CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BEPO, MCDE_EXTSRC8CONF_BEPO_##__x) +#define MCDE_EXTSRC8CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BEPO, __x) +#define MCDE_EXTSRC9CONF 0x0000032C +#define MCDE_EXTSRC9CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC9CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC9CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BUF_ID, __x) +#define MCDE_EXTSRC9CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC9CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC9CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BUF_NB, __x) +#define MCDE_EXTSRC9CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC9CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC9CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC9CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC9CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC9CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC9CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC9CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC9CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC9CONF_BPP_RGB444 4 +#define MCDE_EXTSRC9CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC9CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC9CONF_BPP_RGB565 7 +#define MCDE_EXTSRC9CONF_BPP_RGB888 8 +#define MCDE_EXTSRC9CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC9CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC9CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC9CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BPP, MCDE_EXTSRC9CONF_BPP_##__x) +#define MCDE_EXTSRC9CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BPP, __x) +#define MCDE_EXTSRC9CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC9CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC9CONF_BGR_RGB 0 +#define MCDE_EXTSRC9CONF_BGR_BGR 1 +#define MCDE_EXTSRC9CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BGR, MCDE_EXTSRC9CONF_BGR_##__x) +#define MCDE_EXTSRC9CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BGR, __x) +#define MCDE_EXTSRC9CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC9CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC9CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC9CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC9CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BEBO, MCDE_EXTSRC9CONF_BEBO_##__x) +#define MCDE_EXTSRC9CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BEBO, __x) +#define MCDE_EXTSRC9CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC9CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC9CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC9CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC9CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BEPO, MCDE_EXTSRC9CONF_BEPO_##__x) +#define MCDE_EXTSRC9CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BEPO, __x) +#define MCDE_EXTSRC0CR 0x00000210 +#define MCDE_EXTSRC0CR_GROUPOFFSET 0x20 +#define MCDE_EXTSRC0CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC0CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC0CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC0CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC0CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC0CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, SEL_MOD, MCDE_EXTSRC0CR_SEL_MOD_##__x) +#define MCDE_EXTSRC0CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, SEL_MOD, __x) +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC0CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC0CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC0CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC0CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC0CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC0CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC0CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC1CR 0x00000230 +#define MCDE_EXTSRC1CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC1CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC1CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC1CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC1CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC1CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, SEL_MOD, MCDE_EXTSRC1CR_SEL_MOD_##__x) +#define MCDE_EXTSRC1CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, SEL_MOD, __x) +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC1CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC1CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC1CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC1CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC1CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC1CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC1CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC2CR 0x00000250 +#define MCDE_EXTSRC2CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC2CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC2CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC2CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC2CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC2CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, SEL_MOD, MCDE_EXTSRC2CR_SEL_MOD_##__x) +#define MCDE_EXTSRC2CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, SEL_MOD, __x) +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC2CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC2CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC2CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC2CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC2CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC2CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC2CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC3CR 0x00000270 +#define MCDE_EXTSRC3CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC3CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC3CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC3CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC3CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC3CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, SEL_MOD, MCDE_EXTSRC3CR_SEL_MOD_##__x) +#define MCDE_EXTSRC3CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, SEL_MOD, __x) +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC3CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC3CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC3CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC3CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC3CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC3CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC3CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC4CR 0x00000290 +#define MCDE_EXTSRC4CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC4CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC4CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC4CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC4CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC4CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, SEL_MOD, MCDE_EXTSRC4CR_SEL_MOD_##__x) +#define MCDE_EXTSRC4CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, SEL_MOD, __x) +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC4CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC4CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC4CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC4CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC4CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC4CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC4CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC5CR 0x000002B0 +#define MCDE_EXTSRC5CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC5CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC5CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC5CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC5CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC5CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, SEL_MOD, MCDE_EXTSRC5CR_SEL_MOD_##__x) +#define MCDE_EXTSRC5CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, SEL_MOD, __x) +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC5CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC5CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC5CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC5CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC5CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC5CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC5CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC6CR 0x000002D0 +#define MCDE_EXTSRC6CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC6CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC6CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC6CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC6CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC6CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, SEL_MOD, MCDE_EXTSRC6CR_SEL_MOD_##__x) +#define MCDE_EXTSRC6CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, SEL_MOD, __x) +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC6CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC6CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC6CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC6CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC6CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC6CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC6CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC7CR 0x000002F0 +#define MCDE_EXTSRC7CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC7CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC7CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC7CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC7CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC7CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, SEL_MOD, MCDE_EXTSRC7CR_SEL_MOD_##__x) +#define MCDE_EXTSRC7CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, SEL_MOD, __x) +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC7CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC7CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC7CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC7CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC7CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC7CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC7CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC8CR 0x00000310 +#define MCDE_EXTSRC8CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC8CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC8CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC8CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC8CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC8CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, SEL_MOD, MCDE_EXTSRC8CR_SEL_MOD_##__x) +#define MCDE_EXTSRC8CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, SEL_MOD, __x) +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC8CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC8CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC8CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC8CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC8CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC8CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC8CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC9CR 0x00000330 +#define MCDE_EXTSRC9CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC9CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC9CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC9CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC9CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC9CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, SEL_MOD, MCDE_EXTSRC9CR_SEL_MOD_##__x) +#define MCDE_EXTSRC9CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, SEL_MOD, __x) +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC9CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC9CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC9CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC9CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC9CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC9CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC9CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, FORCE_FS_DIV, __x) +#define MCDE_OVL0CR 0x00000400 +#define MCDE_OVL0CR_GROUPOFFSET 0x20 +#define MCDE_OVL0CR_OVLEN_SHIFT 0 +#define MCDE_OVL0CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL0CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, OVLEN, __x) +#define MCDE_OVL0CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL0CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL0CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL0CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL0CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL0CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, COLCCTRL, MCDE_OVL0CR_COLCCTRL_##__x) +#define MCDE_OVL0CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, COLCCTRL, __x) +#define MCDE_OVL0CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL0CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL0CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, CKEYGEN, __x) +#define MCDE_OVL0CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL0CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL0CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, ALPHAPMEN, __x) +#define MCDE_OVL0CR_OVLF_SHIFT 5 +#define MCDE_OVL0CR_OVLF_MASK 0x00000020 +#define MCDE_OVL0CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, OVLF, __x) +#define MCDE_OVL0CR_OVLR_SHIFT 6 +#define MCDE_OVL0CR_OVLR_MASK 0x00000040 +#define MCDE_OVL0CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, OVLR, __x) +#define MCDE_OVL0CR_OVLB_SHIFT 7 +#define MCDE_OVL0CR_OVLB_MASK 0x00000080 +#define MCDE_OVL0CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, OVLB, __x) +#define MCDE_OVL0CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL0CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL0CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, FETCH_ROPC, __x) +#define MCDE_OVL0CR_STBPRIO_SHIFT 16 +#define MCDE_OVL0CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL0CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, STBPRIO, __x) +#define MCDE_OVL0CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL0CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL0CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, BURSTSIZE, __x) +#define MCDE_OVL0CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL0CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL0CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, MAXOUTSTANDING, __x) +#define MCDE_OVL0CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL0CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL0CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, ROTBURSTSIZE, __x) +#define MCDE_OVL1CR 0x00000420 +#define MCDE_OVL1CR_OVLEN_SHIFT 0 +#define MCDE_OVL1CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL1CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, OVLEN, __x) +#define MCDE_OVL1CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL1CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL1CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL1CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL1CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL1CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, COLCCTRL, MCDE_OVL1CR_COLCCTRL_##__x) +#define MCDE_OVL1CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, COLCCTRL, __x) +#define MCDE_OVL1CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL1CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL1CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, CKEYGEN, __x) +#define MCDE_OVL1CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL1CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL1CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, ALPHAPMEN, __x) +#define MCDE_OVL1CR_OVLF_SHIFT 5 +#define MCDE_OVL1CR_OVLF_MASK 0x00000020 +#define MCDE_OVL1CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, OVLF, __x) +#define MCDE_OVL1CR_OVLR_SHIFT 6 +#define MCDE_OVL1CR_OVLR_MASK 0x00000040 +#define MCDE_OVL1CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, OVLR, __x) +#define MCDE_OVL1CR_OVLB_SHIFT 7 +#define MCDE_OVL1CR_OVLB_MASK 0x00000080 +#define MCDE_OVL1CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, OVLB, __x) +#define MCDE_OVL1CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL1CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL1CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, FETCH_ROPC, __x) +#define MCDE_OVL1CR_STBPRIO_SHIFT 16 +#define MCDE_OVL1CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL1CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, STBPRIO, __x) +#define MCDE_OVL1CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL1CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL1CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, BURSTSIZE, __x) +#define MCDE_OVL1CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL1CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL1CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, MAXOUTSTANDING, __x) +#define MCDE_OVL1CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL1CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL1CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, ROTBURSTSIZE, __x) +#define MCDE_OVL2CR 0x00000440 +#define MCDE_OVL2CR_OVLEN_SHIFT 0 +#define MCDE_OVL2CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL2CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, OVLEN, __x) +#define MCDE_OVL2CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL2CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL2CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL2CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL2CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL2CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, COLCCTRL, MCDE_OVL2CR_COLCCTRL_##__x) +#define MCDE_OVL2CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, COLCCTRL, __x) +#define MCDE_OVL2CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL2CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL2CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, CKEYGEN, __x) +#define MCDE_OVL2CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL2CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL2CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, ALPHAPMEN, __x) +#define MCDE_OVL2CR_OVLF_SHIFT 5 +#define MCDE_OVL2CR_OVLF_MASK 0x00000020 +#define MCDE_OVL2CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, OVLF, __x) +#define MCDE_OVL2CR_OVLR_SHIFT 6 +#define MCDE_OVL2CR_OVLR_MASK 0x00000040 +#define MCDE_OVL2CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, OVLR, __x) +#define MCDE_OVL2CR_OVLB_SHIFT 7 +#define MCDE_OVL2CR_OVLB_MASK 0x00000080 +#define MCDE_OVL2CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, OVLB, __x) +#define MCDE_OVL2CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL2CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL2CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, FETCH_ROPC, __x) +#define MCDE_OVL2CR_STBPRIO_SHIFT 16 +#define MCDE_OVL2CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL2CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, STBPRIO, __x) +#define MCDE_OVL2CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL2CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL2CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, BURSTSIZE, __x) +#define MCDE_OVL2CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL2CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL2CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, MAXOUTSTANDING, __x) +#define MCDE_OVL2CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL2CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL2CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, ROTBURSTSIZE, __x) +#define MCDE_OVL3CR 0x00000460 +#define MCDE_OVL3CR_OVLEN_SHIFT 0 +#define MCDE_OVL3CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL3CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, OVLEN, __x) +#define MCDE_OVL3CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL3CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL3CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL3CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL3CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL3CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, COLCCTRL, MCDE_OVL3CR_COLCCTRL_##__x) +#define MCDE_OVL3CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, COLCCTRL, __x) +#define MCDE_OVL3CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL3CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL3CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, CKEYGEN, __x) +#define MCDE_OVL3CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL3CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL3CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, ALPHAPMEN, __x) +#define MCDE_OVL3CR_OVLF_SHIFT 5 +#define MCDE_OVL3CR_OVLF_MASK 0x00000020 +#define MCDE_OVL3CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, OVLF, __x) +#define MCDE_OVL3CR_OVLR_SHIFT 6 +#define MCDE_OVL3CR_OVLR_MASK 0x00000040 +#define MCDE_OVL3CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, OVLR, __x) +#define MCDE_OVL3CR_OVLB_SHIFT 7 +#define MCDE_OVL3CR_OVLB_MASK 0x00000080 +#define MCDE_OVL3CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, OVLB, __x) +#define MCDE_OVL3CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL3CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL3CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, FETCH_ROPC, __x) +#define MCDE_OVL3CR_STBPRIO_SHIFT 16 +#define MCDE_OVL3CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL3CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, STBPRIO, __x) +#define MCDE_OVL3CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL3CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL3CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, BURSTSIZE, __x) +#define MCDE_OVL3CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL3CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL3CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, MAXOUTSTANDING, __x) +#define MCDE_OVL3CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL3CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL3CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, ROTBURSTSIZE, __x) +#define MCDE_OVL4CR 0x00000480 +#define MCDE_OVL4CR_OVLEN_SHIFT 0 +#define MCDE_OVL4CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL4CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, OVLEN, __x) +#define MCDE_OVL4CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL4CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL4CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL4CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL4CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL4CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, COLCCTRL, MCDE_OVL4CR_COLCCTRL_##__x) +#define MCDE_OVL4CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, COLCCTRL, __x) +#define MCDE_OVL4CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL4CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL4CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, CKEYGEN, __x) +#define MCDE_OVL4CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL4CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL4CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, ALPHAPMEN, __x) +#define MCDE_OVL4CR_OVLF_SHIFT 5 +#define MCDE_OVL4CR_OVLF_MASK 0x00000020 +#define MCDE_OVL4CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, OVLF, __x) +#define MCDE_OVL4CR_OVLR_SHIFT 6 +#define MCDE_OVL4CR_OVLR_MASK 0x00000040 +#define MCDE_OVL4CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, OVLR, __x) +#define MCDE_OVL4CR_OVLB_SHIFT 7 +#define MCDE_OVL4CR_OVLB_MASK 0x00000080 +#define MCDE_OVL4CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, OVLB, __x) +#define MCDE_OVL4CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL4CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL4CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, FETCH_ROPC, __x) +#define MCDE_OVL4CR_STBPRIO_SHIFT 16 +#define MCDE_OVL4CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL4CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, STBPRIO, __x) +#define MCDE_OVL4CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL4CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL4CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, BURSTSIZE, __x) +#define MCDE_OVL4CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL4CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL4CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, MAXOUTSTANDING, __x) +#define MCDE_OVL4CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL4CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL4CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, ROTBURSTSIZE, __x) +#define MCDE_OVL5CR 0x000004A0 +#define MCDE_OVL5CR_OVLEN_SHIFT 0 +#define MCDE_OVL5CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL5CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, OVLEN, __x) +#define MCDE_OVL5CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL5CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL5CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL5CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL5CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL5CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, COLCCTRL, MCDE_OVL5CR_COLCCTRL_##__x) +#define MCDE_OVL5CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, COLCCTRL, __x) +#define MCDE_OVL5CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL5CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL5CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, CKEYGEN, __x) +#define MCDE_OVL5CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL5CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL5CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, ALPHAPMEN, __x) +#define MCDE_OVL5CR_OVLF_SHIFT 5 +#define MCDE_OVL5CR_OVLF_MASK 0x00000020 +#define MCDE_OVL5CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, OVLF, __x) +#define MCDE_OVL5CR_OVLR_SHIFT 6 +#define MCDE_OVL5CR_OVLR_MASK 0x00000040 +#define MCDE_OVL5CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, OVLR, __x) +#define MCDE_OVL5CR_OVLB_SHIFT 7 +#define MCDE_OVL5CR_OVLB_MASK 0x00000080 +#define MCDE_OVL5CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, OVLB, __x) +#define MCDE_OVL5CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL5CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL5CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, FETCH_ROPC, __x) +#define MCDE_OVL5CR_STBPRIO_SHIFT 16 +#define MCDE_OVL5CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL5CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, STBPRIO, __x) +#define MCDE_OVL5CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL5CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL5CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, BURSTSIZE, __x) +#define MCDE_OVL5CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL5CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL5CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, MAXOUTSTANDING, __x) +#define MCDE_OVL5CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL5CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL5CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, ROTBURSTSIZE, __x) +#define MCDE_OVL0CONF 0x00000404 +#define MCDE_OVL0CONF_GROUPOFFSET 0x20 +#define MCDE_OVL0CONF_PPL_SHIFT 0 +#define MCDE_OVL0CONF_PPL_MASK 0x000007FF +#define MCDE_OVL0CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF, PPL, __x) +#define MCDE_OVL0CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL0CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL0CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF, EXTSRC_ID, __x) +#define MCDE_OVL0CONF_LPF_SHIFT 16 +#define MCDE_OVL0CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL0CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF, LPF, __x) +#define MCDE_OVL1CONF 0x00000424 +#define MCDE_OVL1CONF_PPL_SHIFT 0 +#define MCDE_OVL1CONF_PPL_MASK 0x000007FF +#define MCDE_OVL1CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF, PPL, __x) +#define MCDE_OVL1CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL1CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL1CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF, EXTSRC_ID, __x) +#define MCDE_OVL1CONF_LPF_SHIFT 16 +#define MCDE_OVL1CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL1CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF, LPF, __x) +#define MCDE_OVL2CONF 0x00000444 +#define MCDE_OVL2CONF_PPL_SHIFT 0 +#define MCDE_OVL2CONF_PPL_MASK 0x000007FF +#define MCDE_OVL2CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF, PPL, __x) +#define MCDE_OVL2CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL2CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL2CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF, EXTSRC_ID, __x) +#define MCDE_OVL2CONF_LPF_SHIFT 16 +#define MCDE_OVL2CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL2CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF, LPF, __x) +#define MCDE_OVL3CONF 0x00000464 +#define MCDE_OVL3CONF_PPL_SHIFT 0 +#define MCDE_OVL3CONF_PPL_MASK 0x000007FF +#define MCDE_OVL3CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF, PPL, __x) +#define MCDE_OVL3CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL3CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL3CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF, EXTSRC_ID, __x) +#define MCDE_OVL3CONF_LPF_SHIFT 16 +#define MCDE_OVL3CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL3CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF, LPF, __x) +#define MCDE_OVL4CONF 0x00000484 +#define MCDE_OVL4CONF_PPL_SHIFT 0 +#define MCDE_OVL4CONF_PPL_MASK 0x000007FF +#define MCDE_OVL4CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF, PPL, __x) +#define MCDE_OVL4CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL4CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL4CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF, EXTSRC_ID, __x) +#define MCDE_OVL4CONF_LPF_SHIFT 16 +#define MCDE_OVL4CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL4CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF, LPF, __x) +#define MCDE_OVL5CONF 0x000004A4 +#define MCDE_OVL5CONF_PPL_SHIFT 0 +#define MCDE_OVL5CONF_PPL_MASK 0x000007FF +#define MCDE_OVL5CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF, PPL, __x) +#define MCDE_OVL5CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL5CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL5CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF, EXTSRC_ID, __x) +#define MCDE_OVL5CONF_LPF_SHIFT 16 +#define MCDE_OVL5CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL5CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF, LPF, __x) +#define MCDE_OVL0CONF2 0x00000408 +#define MCDE_OVL0CONF2_GROUPOFFSET 0x20 +#define MCDE_OVL0CONF2_BP_SHIFT 0 +#define MCDE_OVL0CONF2_BP_MASK 0x00000001 +#define MCDE_OVL0CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL0CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL0CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, BP, MCDE_OVL0CONF2_BP_##__x) +#define MCDE_OVL0CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, BP, __x) +#define MCDE_OVL0CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL0CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL0CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, ALPHAVALUE, __x) +#define MCDE_OVL0CONF2_OPQ_SHIFT 9 +#define MCDE_OVL0CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL0CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, OPQ, __x) +#define MCDE_OVL0CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL0CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL0CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, PIXOFF, __x) +#define MCDE_OVL0CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL0CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL0CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL1CONF2 0x00000428 +#define MCDE_OVL1CONF2_BP_SHIFT 0 +#define MCDE_OVL1CONF2_BP_MASK 0x00000001 +#define MCDE_OVL1CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL1CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL1CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, BP, MCDE_OVL1CONF2_BP_##__x) +#define MCDE_OVL1CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, BP, __x) +#define MCDE_OVL1CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL1CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL1CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, ALPHAVALUE, __x) +#define MCDE_OVL1CONF2_OPQ_SHIFT 9 +#define MCDE_OVL1CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL1CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, OPQ, __x) +#define MCDE_OVL1CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL1CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL1CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, PIXOFF, __x) +#define MCDE_OVL1CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL1CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL1CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL2CONF2 0x00000448 +#define MCDE_OVL2CONF2_BP_SHIFT 0 +#define MCDE_OVL2CONF2_BP_MASK 0x00000001 +#define MCDE_OVL2CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL2CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL2CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, BP, MCDE_OVL2CONF2_BP_##__x) +#define MCDE_OVL2CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, BP, __x) +#define MCDE_OVL2CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL2CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL2CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, ALPHAVALUE, __x) +#define MCDE_OVL2CONF2_OPQ_SHIFT 9 +#define MCDE_OVL2CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL2CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, OPQ, __x) +#define MCDE_OVL2CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL2CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL2CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, PIXOFF, __x) +#define MCDE_OVL2CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL2CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL2CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL3CONF2 0x00000468 +#define MCDE_OVL3CONF2_BP_SHIFT 0 +#define MCDE_OVL3CONF2_BP_MASK 0x00000001 +#define MCDE_OVL3CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL3CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL3CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, BP, MCDE_OVL3CONF2_BP_##__x) +#define MCDE_OVL3CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, BP, __x) +#define MCDE_OVL3CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL3CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL3CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, ALPHAVALUE, __x) +#define MCDE_OVL3CONF2_OPQ_SHIFT 9 +#define MCDE_OVL3CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL3CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, OPQ, __x) +#define MCDE_OVL3CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL3CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL3CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, PIXOFF, __x) +#define MCDE_OVL3CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL3CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL3CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL4CONF2 0x00000488 +#define MCDE_OVL4CONF2_BP_SHIFT 0 +#define MCDE_OVL4CONF2_BP_MASK 0x00000001 +#define MCDE_OVL4CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL4CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL4CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, BP, MCDE_OVL4CONF2_BP_##__x) +#define MCDE_OVL4CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, BP, __x) +#define MCDE_OVL4CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL4CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL4CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, ALPHAVALUE, __x) +#define MCDE_OVL4CONF2_OPQ_SHIFT 9 +#define MCDE_OVL4CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL4CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, OPQ, __x) +#define MCDE_OVL4CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL4CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL4CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, PIXOFF, __x) +#define MCDE_OVL4CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL4CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL4CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL5CONF2 0x000004A8 +#define MCDE_OVL5CONF2_BP_SHIFT 0 +#define MCDE_OVL5CONF2_BP_MASK 0x00000001 +#define MCDE_OVL5CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL5CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL5CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, BP, MCDE_OVL5CONF2_BP_##__x) +#define MCDE_OVL5CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, BP, __x) +#define MCDE_OVL5CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL5CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL5CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, ALPHAVALUE, __x) +#define MCDE_OVL5CONF2_OPQ_SHIFT 9 +#define MCDE_OVL5CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL5CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, OPQ, __x) +#define MCDE_OVL5CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL5CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL5CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, PIXOFF, __x) +#define MCDE_OVL5CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL5CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL5CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL0LJINC 0x0000040C +#define MCDE_OVL0LJINC_GROUPOFFSET 0x20 +#define MCDE_OVL0LJINC_LJINC_SHIFT 0 +#define MCDE_OVL0LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL0LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL0LJINC, LJINC, __x) +#define MCDE_OVL1LJINC 0x0000042C +#define MCDE_OVL1LJINC_LJINC_SHIFT 0 +#define MCDE_OVL1LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL1LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL1LJINC, LJINC, __x) +#define MCDE_OVL2LJINC 0x0000044C +#define MCDE_OVL2LJINC_LJINC_SHIFT 0 +#define MCDE_OVL2LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL2LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL2LJINC, LJINC, __x) +#define MCDE_OVL3LJINC 0x0000046C +#define MCDE_OVL3LJINC_LJINC_SHIFT 0 +#define MCDE_OVL3LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL3LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL3LJINC, LJINC, __x) +#define MCDE_OVL4LJINC 0x0000048C +#define MCDE_OVL4LJINC_LJINC_SHIFT 0 +#define MCDE_OVL4LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL4LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL4LJINC, LJINC, __x) +#define MCDE_OVL5LJINC 0x000004AC +#define MCDE_OVL5LJINC_LJINC_SHIFT 0 +#define MCDE_OVL5LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL5LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL5LJINC, LJINC, __x) +#define MCDE_OVL0CROP 0x00000410 +#define MCDE_OVL0CROP_GROUPOFFSET 0x20 +#define MCDE_OVL0CROP_TMRGN_SHIFT 0 +#define MCDE_OVL0CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL0CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CROP, TMRGN, __x) +#define MCDE_OVL0CROP_LMRGN_SHIFT 22 +#define MCDE_OVL0CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL0CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CROP, LMRGN, __x) +#define MCDE_OVL1CROP 0x00000430 +#define MCDE_OVL1CROP_TMRGN_SHIFT 0 +#define MCDE_OVL1CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL1CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CROP, TMRGN, __x) +#define MCDE_OVL1CROP_LMRGN_SHIFT 22 +#define MCDE_OVL1CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL1CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CROP, LMRGN, __x) +#define MCDE_OVL2CROP 0x00000450 +#define MCDE_OVL2CROP_TMRGN_SHIFT 0 +#define MCDE_OVL2CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL2CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CROP, TMRGN, __x) +#define MCDE_OVL2CROP_LMRGN_SHIFT 22 +#define MCDE_OVL2CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL2CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CROP, LMRGN, __x) +#define MCDE_OVL3CROP 0x00000470 +#define MCDE_OVL3CROP_TMRGN_SHIFT 0 +#define MCDE_OVL3CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL3CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CROP, TMRGN, __x) +#define MCDE_OVL3CROP_LMRGN_SHIFT 22 +#define MCDE_OVL3CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL3CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CROP, LMRGN, __x) +#define MCDE_OVL4CROP 0x00000490 +#define MCDE_OVL4CROP_TMRGN_SHIFT 0 +#define MCDE_OVL4CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL4CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CROP, TMRGN, __x) +#define MCDE_OVL4CROP_LMRGN_SHIFT 22 +#define MCDE_OVL4CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL4CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CROP, LMRGN, __x) +#define MCDE_OVL5CROP 0x000004B0 +#define MCDE_OVL5CROP_TMRGN_SHIFT 0 +#define MCDE_OVL5CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL5CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CROP, TMRGN, __x) +#define MCDE_OVL5CROP_LMRGN_SHIFT 22 +#define MCDE_OVL5CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL5CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CROP, LMRGN, __x) +#define MCDE_OVL0COMP 0x00000414 +#define MCDE_OVL0COMP_GROUPOFFSET 0x20 +#define MCDE_OVL0COMP_XPOS_SHIFT 0 +#define MCDE_OVL0COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL0COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL0COMP, XPOS, __x) +#define MCDE_OVL0COMP_CH_ID_SHIFT 11 +#define MCDE_OVL0COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL0COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL0COMP, CH_ID, __x) +#define MCDE_OVL0COMP_YPOS_SHIFT 16 +#define MCDE_OVL0COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL0COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL0COMP, YPOS, __x) +#define MCDE_OVL0COMP_Z_SHIFT 27 +#define MCDE_OVL0COMP_Z_MASK 0x78000000 +#define MCDE_OVL0COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL0COMP, Z, __x) +#define MCDE_OVL1COMP 0x00000434 +#define MCDE_OVL1COMP_XPOS_SHIFT 0 +#define MCDE_OVL1COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL1COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL1COMP, XPOS, __x) +#define MCDE_OVL1COMP_CH_ID_SHIFT 11 +#define MCDE_OVL1COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL1COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL1COMP, CH_ID, __x) +#define MCDE_OVL1COMP_YPOS_SHIFT 16 +#define MCDE_OVL1COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL1COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL1COMP, YPOS, __x) +#define MCDE_OVL1COMP_Z_SHIFT 27 +#define MCDE_OVL1COMP_Z_MASK 0x78000000 +#define MCDE_OVL1COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL1COMP, Z, __x) +#define MCDE_OVL2COMP 0x00000454 +#define MCDE_OVL2COMP_XPOS_SHIFT 0 +#define MCDE_OVL2COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL2COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL2COMP, XPOS, __x) +#define MCDE_OVL2COMP_CH_ID_SHIFT 11 +#define MCDE_OVL2COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL2COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL2COMP, CH_ID, __x) +#define MCDE_OVL2COMP_YPOS_SHIFT 16 +#define MCDE_OVL2COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL2COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL2COMP, YPOS, __x) +#define MCDE_OVL2COMP_Z_SHIFT 27 +#define MCDE_OVL2COMP_Z_MASK 0x78000000 +#define MCDE_OVL2COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL2COMP, Z, __x) +#define MCDE_OVL3COMP 0x00000474 +#define MCDE_OVL3COMP_XPOS_SHIFT 0 +#define MCDE_OVL3COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL3COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL3COMP, XPOS, __x) +#define MCDE_OVL3COMP_CH_ID_SHIFT 11 +#define MCDE_OVL3COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL3COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL3COMP, CH_ID, __x) +#define MCDE_OVL3COMP_YPOS_SHIFT 16 +#define MCDE_OVL3COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL3COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL3COMP, YPOS, __x) +#define MCDE_OVL3COMP_Z_SHIFT 27 +#define MCDE_OVL3COMP_Z_MASK 0x78000000 +#define MCDE_OVL3COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL3COMP, Z, __x) +#define MCDE_OVL4COMP 0x00000494 +#define MCDE_OVL4COMP_XPOS_SHIFT 0 +#define MCDE_OVL4COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL4COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL4COMP, XPOS, __x) +#define MCDE_OVL4COMP_CH_ID_SHIFT 11 +#define MCDE_OVL4COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL4COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL4COMP, CH_ID, __x) +#define MCDE_OVL4COMP_YPOS_SHIFT 16 +#define MCDE_OVL4COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL4COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL4COMP, YPOS, __x) +#define MCDE_OVL4COMP_Z_SHIFT 27 +#define MCDE_OVL4COMP_Z_MASK 0x78000000 +#define MCDE_OVL4COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL4COMP, Z, __x) +#define MCDE_OVL5COMP 0x000004B4 +#define MCDE_OVL5COMP_XPOS_SHIFT 0 +#define MCDE_OVL5COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL5COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL5COMP, XPOS, __x) +#define MCDE_OVL5COMP_CH_ID_SHIFT 11 +#define MCDE_OVL5COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL5COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL5COMP, CH_ID, __x) +#define MCDE_OVL5COMP_YPOS_SHIFT 16 +#define MCDE_OVL5COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL5COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL5COMP, YPOS, __x) +#define MCDE_OVL5COMP_Z_SHIFT 27 +#define MCDE_OVL5COMP_Z_MASK 0x78000000 +#define MCDE_OVL5COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL5COMP, Z, __x) +#define MCDE_CHNL0CONF 0x00000600 +#define MCDE_CHNL0CONF_GROUPOFFSET 0x20 +#define MCDE_CHNL0CONF_PPL_SHIFT 0 +#define MCDE_CHNL0CONF_PPL_MASK 0x000007FF +#define MCDE_CHNL0CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_CHNL0CONF, PPL, __x) +#define MCDE_CHNL0CONF_LPF_SHIFT 16 +#define MCDE_CHNL0CONF_LPF_MASK 0x07FF0000 +#define MCDE_CHNL0CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_CHNL0CONF, LPF, __x) +#define MCDE_CHNL1CONF 0x00000620 +#define MCDE_CHNL1CONF_PPL_SHIFT 0 +#define MCDE_CHNL1CONF_PPL_MASK 0x000007FF +#define MCDE_CHNL1CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_CHNL1CONF, PPL, __x) +#define MCDE_CHNL1CONF_LPF_SHIFT 16 +#define MCDE_CHNL1CONF_LPF_MASK 0x07FF0000 +#define MCDE_CHNL1CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_CHNL1CONF, LPF, __x) +#define MCDE_CHNL2CONF 0x00000640 +#define MCDE_CHNL2CONF_PPL_SHIFT 0 +#define MCDE_CHNL2CONF_PPL_MASK 0x000007FF +#define MCDE_CHNL2CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_CHNL2CONF, PPL, __x) +#define MCDE_CHNL2CONF_LPF_SHIFT 16 +#define MCDE_CHNL2CONF_LPF_MASK 0x07FF0000 +#define MCDE_CHNL2CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_CHNL2CONF, LPF, __x) +#define MCDE_CHNL3CONF 0x00000660 +#define MCDE_CHNL3CONF_PPL_SHIFT 0 +#define MCDE_CHNL3CONF_PPL_MASK 0x000007FF +#define MCDE_CHNL3CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_CHNL3CONF, PPL, __x) +#define MCDE_CHNL3CONF_LPF_SHIFT 16 +#define MCDE_CHNL3CONF_LPF_MASK 0x07FF0000 +#define MCDE_CHNL3CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_CHNL3CONF, LPF, __x) +#define MCDE_CHNL0STAT 0x00000604 +#define MCDE_CHNL0STAT_GROUPOFFSET 0x20 +#define MCDE_CHNL0STAT_CHNLRD_SHIFT 0 +#define MCDE_CHNL0STAT_CHNLRD_MASK 0x00000001 +#define MCDE_CHNL0STAT_CHNLRD(__x) \ + MCDE_VAL2REG(MCDE_CHNL0STAT, CHNLRD, __x) +#define MCDE_CHNL0STAT_CHNLA_SHIFT 1 +#define MCDE_CHNL0STAT_CHNLA_MASK 0x00000002 +#define MCDE_CHNL0STAT_CHNLA(__x) \ + MCDE_VAL2REG(MCDE_CHNL0STAT, CHNLA, __x) +#define MCDE_CHNL0STAT_CHNLBLBCKGND_EN_SHIFT 16 +#define MCDE_CHNL0STAT_CHNLBLBCKGND_EN_MASK 0x00010000 +#define MCDE_CHNL0STAT_CHNLBLBCKGND_EN(__x) \ + MCDE_VAL2REG(MCDE_CHNL0STAT, CHNLBLBCKGND_EN, __x) +#define MCDE_CHNL1STAT 0x00000624 +#define MCDE_CHNL1STAT_CHNLRD_SHIFT 0 +#define MCDE_CHNL1STAT_CHNLRD_MASK 0x00000001 +#define MCDE_CHNL1STAT_CHNLRD(__x) \ + MCDE_VAL2REG(MCDE_CHNL1STAT, CHNLRD, __x) +#define MCDE_CHNL1STAT_CHNLA_SHIFT 1 +#define MCDE_CHNL1STAT_CHNLA_MASK 0x00000002 +#define MCDE_CHNL1STAT_CHNLA(__x) \ + MCDE_VAL2REG(MCDE_CHNL1STAT, CHNLA, __x) +#define MCDE_CHNL1STAT_CHNLBLBCKGND_EN_SHIFT 16 +#define MCDE_CHNL1STAT_CHNLBLBCKGND_EN_MASK 0x00010000 +#define MCDE_CHNL1STAT_CHNLBLBCKGND_EN(__x) \ + MCDE_VAL2REG(MCDE_CHNL1STAT, CHNLBLBCKGND_EN, __x) +#define MCDE_CHNL2STAT 0x00000644 +#define MCDE_CHNL2STAT_CHNLRD_SHIFT 0 +#define MCDE_CHNL2STAT_CHNLRD_MASK 0x00000001 +#define MCDE_CHNL2STAT_CHNLRD(__x) \ + MCDE_VAL2REG(MCDE_CHNL2STAT, CHNLRD, __x) +#define MCDE_CHNL2STAT_CHNLA_SHIFT 1 +#define MCDE_CHNL2STAT_CHNLA_MASK 0x00000002 +#define MCDE_CHNL2STAT_CHNLA(__x) \ + MCDE_VAL2REG(MCDE_CHNL2STAT, CHNLA, __x) +#define MCDE_CHNL2STAT_CHNLBLBCKGND_EN_SHIFT 16 +#define MCDE_CHNL2STAT_CHNLBLBCKGND_EN_MASK 0x00010000 +#define MCDE_CHNL2STAT_CHNLBLBCKGND_EN(__x) \ + MCDE_VAL2REG(MCDE_CHNL2STAT, CHNLBLBCKGND_EN, __x) +#define MCDE_CHNL3STAT 0x00000664 +#define MCDE_CHNL3STAT_CHNLRD_SHIFT 0 +#define MCDE_CHNL3STAT_CHNLRD_MASK 0x00000001 +#define MCDE_CHNL3STAT_CHNLRD(__x) \ + MCDE_VAL2REG(MCDE_CHNL3STAT, CHNLRD, __x) +#define MCDE_CHNL3STAT_CHNLA_SHIFT 1 +#define MCDE_CHNL3STAT_CHNLA_MASK 0x00000002 +#define MCDE_CHNL3STAT_CHNLA(__x) \ + MCDE_VAL2REG(MCDE_CHNL3STAT, CHNLA, __x) +#define MCDE_CHNL3STAT_CHNLBLBCKGND_EN_SHIFT 16 +#define MCDE_CHNL3STAT_CHNLBLBCKGND_EN_MASK 0x00010000 +#define MCDE_CHNL3STAT_CHNLBLBCKGND_EN(__x) \ + MCDE_VAL2REG(MCDE_CHNL3STAT, CHNLBLBCKGND_EN, __x) +#define MCDE_CHNL0SYNCHMOD 0x00000608 +#define MCDE_CHNL0SYNCHMOD_GROUPOFFSET 0x20 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_MASK 0x00000003 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT 0 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_AUTO 1 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE 2 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_EXTERNAL 3 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, SRC_SYNCH, \ + MCDE_CHNL0SYNCHMOD_SRC_SYNCH_##__x) +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, SRC_SYNCH, __x) +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1 +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2 +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, OUT_SYNCH_SRC, \ + MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_##__x) +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, OUT_SYNCH_SRC, __x) +#define MCDE_CHNL1SYNCHMOD 0x00000628 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_MASK 0x00000003 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_OUTPUT 0 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_AUTO 1 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_SOFTWARE 2 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_EXTERNAL 3 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, SRC_SYNCH, \ + MCDE_CHNL1SYNCHMOD_SRC_SYNCH_##__x) +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, SRC_SYNCH, __x) +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1 +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2 +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, OUT_SYNCH_SRC, \ + MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_##__x) +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, OUT_SYNCH_SRC, __x) +#define MCDE_CHNL2SYNCHMOD 0x00000648 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_MASK 0x00000003 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_OUTPUT 0 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_AUTO 1 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_SOFTWARE 2 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_EXTERNAL 3 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, SRC_SYNCH, \ + MCDE_CHNL2SYNCHMOD_SRC_SYNCH_##__x) +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, SRC_SYNCH, __x) +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1 +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2 +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, OUT_SYNCH_SRC, \ + MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_##__x) +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, OUT_SYNCH_SRC, __x) +#define MCDE_CHNL3SYNCHMOD 0x00000668 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_MASK 0x00000003 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_OUTPUT 0 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_AUTO 1 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_SOFTWARE 2 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_EXTERNAL 3 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, SRC_SYNCH, \ + MCDE_CHNL3SYNCHMOD_SRC_SYNCH_##__x) +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, SRC_SYNCH, __x) +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1 +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2 +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, OUT_SYNCH_SRC, \ + MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_##__x) +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, OUT_SYNCH_SRC, __x) +#define MCDE_CHNL0SYNCHSW 0x0000060C +#define MCDE_CHNL0SYNCHSW_GROUPOFFSET 0x20 +#define MCDE_CHNL0SYNCHSW_SW_TRIG_SHIFT 0 +#define MCDE_CHNL0SYNCHSW_SW_TRIG_MASK 0x00000001 +#define MCDE_CHNL0SYNCHSW_SW_TRIG(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHSW, SW_TRIG, __x) +#define MCDE_CHNL1SYNCHSW 0x0000062C +#define MCDE_CHNL1SYNCHSW_SW_TRIG_SHIFT 0 +#define MCDE_CHNL1SYNCHSW_SW_TRIG_MASK 0x00000001 +#define MCDE_CHNL1SYNCHSW_SW_TRIG(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHSW, SW_TRIG, __x) +#define MCDE_CHNL2SYNCHSW 0x0000064C +#define MCDE_CHNL2SYNCHSW_SW_TRIG_SHIFT 0 +#define MCDE_CHNL2SYNCHSW_SW_TRIG_MASK 0x00000001 +#define MCDE_CHNL2SYNCHSW_SW_TRIG(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHSW, SW_TRIG, __x) +#define MCDE_CHNL3SYNCHSW 0x0000066C +#define MCDE_CHNL3SYNCHSW_SW_TRIG_SHIFT 0 +#define MCDE_CHNL3SYNCHSW_SW_TRIG_MASK 0x00000001 +#define MCDE_CHNL3SYNCHSW_SW_TRIG(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHSW, SW_TRIG, __x) +#define MCDE_CHNL0BCKGNDCOL 0x00000610 +#define MCDE_CHNL0BCKGNDCOL_GROUPOFFSET 0x20 +#define MCDE_CHNL0BCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNL0BCKGNDCOL_B_MASK 0x000000FF +#define MCDE_CHNL0BCKGNDCOL_B(__x) \ + MCDE_VAL2REG(MCDE_CHNL0BCKGNDCOL, B, __x) +#define MCDE_CHNL0BCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNL0BCKGNDCOL_G_MASK 0x0000FF00 +#define MCDE_CHNL0BCKGNDCOL_G(__x) \ + MCDE_VAL2REG(MCDE_CHNL0BCKGNDCOL, G, __x) +#define MCDE_CHNL0BCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNL0BCKGNDCOL_R_MASK 0x00FF0000 +#define MCDE_CHNL0BCKGNDCOL_R(__x) \ + MCDE_VAL2REG(MCDE_CHNL0BCKGNDCOL, R, __x) +#define MCDE_CHNL1BCKGNDCOL 0x00000630 +#define MCDE_CHNL1BCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNL1BCKGNDCOL_B_MASK 0x000000FF +#define MCDE_CHNL1BCKGNDCOL_B(__x) \ + MCDE_VAL2REG(MCDE_CHNL1BCKGNDCOL, B, __x) +#define MCDE_CHNL1BCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNL1BCKGNDCOL_G_MASK 0x0000FF00 +#define MCDE_CHNL1BCKGNDCOL_G(__x) \ + MCDE_VAL2REG(MCDE_CHNL1BCKGNDCOL, G, __x) +#define MCDE_CHNL1BCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNL1BCKGNDCOL_R_MASK 0x00FF0000 +#define MCDE_CHNL1BCKGNDCOL_R(__x) \ + MCDE_VAL2REG(MCDE_CHNL1BCKGNDCOL, R, __x) +#define MCDE_CHNL2BCKGNDCOL 0x00000650 +#define MCDE_CHNL2BCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNL2BCKGNDCOL_B_MASK 0x000000FF +#define MCDE_CHNL2BCKGNDCOL_B(__x) \ + MCDE_VAL2REG(MCDE_CHNL2BCKGNDCOL, B, __x) +#define MCDE_CHNL2BCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNL2BCKGNDCOL_G_MASK 0x0000FF00 +#define MCDE_CHNL2BCKGNDCOL_G(__x) \ + MCDE_VAL2REG(MCDE_CHNL2BCKGNDCOL, G, __x) +#define MCDE_CHNL2BCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNL2BCKGNDCOL_R_MASK 0x00FF0000 +#define MCDE_CHNL2BCKGNDCOL_R(__x) \ + MCDE_VAL2REG(MCDE_CHNL2BCKGNDCOL, R, __x) +#define MCDE_CHNL3BCKGNDCOL 0x00000670 +#define MCDE_CHNL3BCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNL3BCKGNDCOL_B_MASK 0x000000FF +#define MCDE_CHNL3BCKGNDCOL_B(__x) \ + MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, B, __x) +#define MCDE_CHNL3BCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNL3BCKGNDCOL_G_MASK 0x0000FF00 +#define MCDE_CHNL3BCKGNDCOL_G(__x) \ + MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, G, __x) +#define MCDE_CHNL3BCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNL3BCKGNDCOL_R_MASK 0x00FF0000 +#define MCDE_CHNL3BCKGNDCOL_R(__x) \ + MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, R, __x) +#define MCDE_CHNL0PRIO 0x00000614 +#define MCDE_CHNL0PRIO_GROUPOFFSET 0x20 +#define MCDE_CHNL0PRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNL0PRIO_CHNLPRIO_MASK 0x0000000F +#define MCDE_CHNL0PRIO_CHNLPRIO(__x) \ + MCDE_VAL2REG(MCDE_CHNL0PRIO, CHNLPRIO, __x) +#define MCDE_CHNL1PRIO 0x00000634 +#define MCDE_CHNL1PRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNL1PRIO_CHNLPRIO_MASK 0x0000000F +#define MCDE_CHNL1PRIO_CHNLPRIO(__x) \ + MCDE_VAL2REG(MCDE_CHNL1PRIO, CHNLPRIO, __x) +#define MCDE_CHNL2PRIO 0x00000654 +#define MCDE_CHNL2PRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNL2PRIO_CHNLPRIO_MASK 0x0000000F +#define MCDE_CHNL2PRIO_CHNLPRIO(__x) \ + MCDE_VAL2REG(MCDE_CHNL2PRIO, CHNLPRIO, __x) +#define MCDE_CHNL3PRIO 0x00000674 +#define MCDE_CHNL3PRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNL3PRIO_CHNLPRIO_MASK 0x0000000F +#define MCDE_CHNL3PRIO_CHNLPRIO(__x) \ + MCDE_VAL2REG(MCDE_CHNL3PRIO, CHNLPRIO, __x) +#define MCDE_CRA0 0x00000800 +#define MCDE_CRA0_GROUPOFFSET 0x200 +#define MCDE_CRA0_FLOEN_SHIFT 0 +#define MCDE_CRA0_FLOEN_MASK 0x00000001 +#define MCDE_CRA0_FLOEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLOEN, __x) +#define MCDE_CRA0_POWEREN_SHIFT 1 +#define MCDE_CRA0_POWEREN_MASK 0x00000002 +#define MCDE_CRA0_POWEREN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, POWEREN, __x) +#define MCDE_CRA0_BLENDEN_SHIFT 2 +#define MCDE_CRA0_BLENDEN_MASK 0x00000004 +#define MCDE_CRA0_BLENDEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, BLENDEN, __x) +#define MCDE_CRA0_AFLICKEN_SHIFT 3 +#define MCDE_CRA0_AFLICKEN_MASK 0x00000008 +#define MCDE_CRA0_AFLICKEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, AFLICKEN, __x) +#define MCDE_CRA0_PALEN_SHIFT 4 +#define MCDE_CRA0_PALEN_MASK 0x00000010 +#define MCDE_CRA0_PALEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, PALEN, __x) +#define MCDE_CRA0_DITHEN_SHIFT 5 +#define MCDE_CRA0_DITHEN_MASK 0x00000020 +#define MCDE_CRA0_DITHEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, DITHEN, __x) +#define MCDE_CRA0_GAMEN_SHIFT 6 +#define MCDE_CRA0_GAMEN_MASK 0x00000040 +#define MCDE_CRA0_GAMEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, GAMEN, __x) +#define MCDE_CRA0_KEYCTRL_SHIFT 7 +#define MCDE_CRA0_KEYCTRL_MASK 0x00000380 +#define MCDE_CRA0_KEYCTRL_OFF 0 +#define MCDE_CRA0_KEYCTRL_ALPHA_RGB 1 +#define MCDE_CRA0_KEYCTRL_RGB 2 +#define MCDE_CRA0_KEYCTRL_FALPHA_FRGB 4 +#define MCDE_CRA0_KEYCTRL_FRGB 5 +#define MCDE_CRA0_KEYCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, KEYCTRL, MCDE_CRA0_KEYCTRL_##__x) +#define MCDE_CRA0_KEYCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRA0, KEYCTRL, __x) +#define MCDE_CRA0_BLENDCTRL_SHIFT 10 +#define MCDE_CRA0_BLENDCTRL_MASK 0x00000400 +#define MCDE_CRA0_BLENDCTRL_SOURCE 0 +#define MCDE_CRA0_BLENDCTRL_CONSTANT 1 +#define MCDE_CRA0_BLENDCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, BLENDCTRL, MCDE_CRA0_BLENDCTRL_##__x) +#define MCDE_CRA0_BLENDCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRA0, BLENDCTRL, __x) +#define MCDE_CRA0_FLICKMODE_SHIFT 11 +#define MCDE_CRA0_FLICKMODE_MASK 0x00001800 +#define MCDE_CRA0_FLICKMODE_FORCE_FILTER_0 0 +#define MCDE_CRA0_FLICKMODE_ADAPTIVE 1 +#define MCDE_CRA0_FLICKMODE_TEST_MODE 2 +#define MCDE_CRA0_FLICKMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLICKMODE, MCDE_CRA0_FLICKMODE_##__x) +#define MCDE_CRA0_FLICKMODE(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLICKMODE, __x) +#define MCDE_CRA0_FLOCKFORMAT_SHIFT 13 +#define MCDE_CRA0_FLOCKFORMAT_MASK 0x00002000 +#define MCDE_CRA0_FLOCKFORMAT_YCBCR 0 +#define MCDE_CRA0_FLOCKFORMAT_RGB 1 +#define MCDE_CRA0_FLOCKFORMAT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLOCKFORMAT, MCDE_CRA0_FLOCKFORMAT_##__x) +#define MCDE_CRA0_FLOCKFORMAT(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLOCKFORMAT, __x) +#define MCDE_CRA0_PALMODE_SHIFT 14 +#define MCDE_CRA0_PALMODE_MASK 0x00004000 +#define MCDE_CRA0_PALMODE_PALETTE 0 +#define MCDE_CRA0_PALMODE_GAMMA 1 +#define MCDE_CRA0_PALMODE(__x) \ + MCDE_VAL2REG(MCDE_CRA0, PALMODE, __x) +#define MCDE_CRA0_OLEDEN_SHIFT 15 +#define MCDE_CRA0_OLEDEN_MASK 0x00008000 +#define MCDE_CRA0_OLEDEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, OLEDEN, __x) +#define MCDE_CRA0_ALPHABLEND_SHIFT 16 +#define MCDE_CRA0_ALPHABLEND_MASK 0x00FF0000 +#define MCDE_CRA0_ALPHABLEND(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ALPHABLEND, __x) +#define MCDE_CRA0_ROTEN_SHIFT 24 +#define MCDE_CRA0_ROTEN_MASK 0x01000000 +#define MCDE_CRA0_ROTEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ROTEN, __x) +#define MCDE_CRA0_ROTBURSTSIZE_SHIFT 25 +#define MCDE_CRA0_ROTBURSTSIZE_MASK 0x0E000000 +#define MCDE_CRA0_ROTBURSTSIZE_1W 0 +#define MCDE_CRA0_ROTBURSTSIZE_2W 1 +#define MCDE_CRA0_ROTBURSTSIZE_4W 2 +#define MCDE_CRA0_ROTBURSTSIZE_8W 3 +#define MCDE_CRA0_ROTBURSTSIZE_16W 4 +#define MCDE_CRA0_ROTBURSTSIZE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE, MCDE_CRA0_ROTBURSTSIZE_##__x) +#define MCDE_CRA0_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE, __x) +#define MCDE_CRA0_ROTBURSTSIZE_HW_SHIFT 28 +#define MCDE_CRA0_ROTBURSTSIZE_HW_MASK 0x10000000 +#define MCDE_CRA0_ROTBURSTSIZE_HW(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_HW, __x) +#define MCDE_CRB0 0x00000A00 +#define MCDE_CRB0_FLOEN_SHIFT 0 +#define MCDE_CRB0_FLOEN_MASK 0x00000001 +#define MCDE_CRB0_FLOEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLOEN, __x) +#define MCDE_CRB0_POWEREN_SHIFT 1 +#define MCDE_CRB0_POWEREN_MASK 0x00000002 +#define MCDE_CRB0_POWEREN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, POWEREN, __x) +#define MCDE_CRB0_BLENDEN_SHIFT 2 +#define MCDE_CRB0_BLENDEN_MASK 0x00000004 +#define MCDE_CRB0_BLENDEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, BLENDEN, __x) +#define MCDE_CRB0_AFLICKEN_SHIFT 3 +#define MCDE_CRB0_AFLICKEN_MASK 0x00000008 +#define MCDE_CRB0_AFLICKEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, AFLICKEN, __x) +#define MCDE_CRB0_PALEN_SHIFT 4 +#define MCDE_CRB0_PALEN_MASK 0x00000010 +#define MCDE_CRB0_PALEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, PALEN, __x) +#define MCDE_CRB0_DITHEN_SHIFT 5 +#define MCDE_CRB0_DITHEN_MASK 0x00000020 +#define MCDE_CRB0_DITHEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, DITHEN, __x) +#define MCDE_CRB0_GAMEN_SHIFT 6 +#define MCDE_CRB0_GAMEN_MASK 0x00000040 +#define MCDE_CRB0_GAMEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, GAMEN, __x) +#define MCDE_CRB0_KEYCTRL_SHIFT 7 +#define MCDE_CRB0_KEYCTRL_MASK 0x00000380 +#define MCDE_CRB0_KEYCTRL_OFF 0 +#define MCDE_CRB0_KEYCTRL_ALPHA_RGB 1 +#define MCDE_CRB0_KEYCTRL_RGB 2 +#define MCDE_CRB0_KEYCTRL_FALPHA_FRGB 4 +#define MCDE_CRB0_KEYCTRL_FRGB 5 +#define MCDE_CRB0_KEYCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, KEYCTRL, MCDE_CRB0_KEYCTRL_##__x) +#define MCDE_CRB0_KEYCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRB0, KEYCTRL, __x) +#define MCDE_CRB0_BLENDCTRL_SHIFT 10 +#define MCDE_CRB0_BLENDCTRL_MASK 0x00000400 +#define MCDE_CRB0_BLENDCTRL_SOURCE 0 +#define MCDE_CRB0_BLENDCTRL_CONSTANT 1 +#define MCDE_CRB0_BLENDCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, BLENDCTRL, MCDE_CRB0_BLENDCTRL_##__x) +#define MCDE_CRB0_BLENDCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRB0, BLENDCTRL, __x) +#define MCDE_CRB0_FLICKMODE_SHIFT 11 +#define MCDE_CRB0_FLICKMODE_MASK 0x00001800 +#define MCDE_CRB0_FLICKMODE_FORCE_FILTER_0 0 +#define MCDE_CRB0_FLICKMODE_ADAPTIVE 1 +#define MCDE_CRB0_FLICKMODE_TEST_MODE 2 +#define MCDE_CRB0_FLICKMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLICKMODE, MCDE_CRB0_FLICKMODE_##__x) +#define MCDE_CRB0_FLICKMODE(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLICKMODE, __x) +#define MCDE_CRB0_FLOCKFORMAT_SHIFT 13 +#define MCDE_CRB0_FLOCKFORMAT_MASK 0x00002000 +#define MCDE_CRB0_FLOCKFORMAT_YCBCR 0 +#define MCDE_CRB0_FLOCKFORMAT_RGB 1 +#define MCDE_CRB0_FLOCKFORMAT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLOCKFORMAT, MCDE_CRB0_FLOCKFORMAT_##__x) +#define MCDE_CRB0_FLOCKFORMAT(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLOCKFORMAT, __x) +#define MCDE_CRB0_PALMODE_SHIFT 14 +#define MCDE_CRB0_PALMODE_MASK 0x00004000 +#define MCDE_CRB0_PALMODE_PALETTE 0 +#define MCDE_CRB0_PALMODE_GAMMA 1 +#define MCDE_CRB0_PALMODE(__x) \ + MCDE_VAL2REG(MCDE_CRB0, PALMODE, __x) +#define MCDE_CRB0_OLEDEN_SHIFT 15 +#define MCDE_CRB0_OLEDEN_MASK 0x00008000 +#define MCDE_CRB0_OLEDEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, OLEDEN, __x) +#define MCDE_CRB0_ALPHABLEND_SHIFT 16 +#define MCDE_CRB0_ALPHABLEND_MASK 0x00FF0000 +#define MCDE_CRB0_ALPHABLEND(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ALPHABLEND, __x) +#define MCDE_CRB0_ROTEN_SHIFT 24 +#define MCDE_CRB0_ROTEN_MASK 0x01000000 +#define MCDE_CRB0_ROTEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ROTEN, __x) +#define MCDE_CRB0_ROTBURSTSIZE_SHIFT 25 +#define MCDE_CRB0_ROTBURSTSIZE_MASK 0x0E000000 +#define MCDE_CRB0_ROTBURSTSIZE_1W 0 +#define MCDE_CRB0_ROTBURSTSIZE_2W 1 +#define MCDE_CRB0_ROTBURSTSIZE_4W 2 +#define MCDE_CRB0_ROTBURSTSIZE_8W 3 +#define MCDE_CRB0_ROTBURSTSIZE_16W 4 +#define MCDE_CRB0_ROTBURSTSIZE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE, MCDE_CRB0_ROTBURSTSIZE_##__x) +#define MCDE_CRB0_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE, __x) +#define MCDE_CRB0_ROTBURSTSIZE_HW_SHIFT 28 +#define MCDE_CRB0_ROTBURSTSIZE_HW_MASK 0x10000000 +#define MCDE_CRB0_ROTBURSTSIZE_HW(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_HW, __x) +#define MCDE_CRA1 0x00000804 +#define MCDE_CRA1_GROUPOFFSET 0x200 +#define MCDE_CRA1_PCD_SHIFT 0 +#define MCDE_CRA1_PCD_MASK 0x000003FF +#define MCDE_CRA1_PCD(__x) \ + MCDE_VAL2REG(MCDE_CRA1, PCD, __x) +#define MCDE_CRA1_CLKSEL_SHIFT 10 +#define MCDE_CRA1_CLKSEL_MASK 0x00001C00 +#define MCDE_CRA1_CLKSEL_LCD 0 +#define MCDE_CRA1_CLKSEL_HDMI 1 +#define MCDE_CRA1_CLKSEL_TV 2 +#define MCDE_CRA1_CLKSEL_EXT_TV1 3 +#define MCDE_CRA1_CLKSEL_EXT_TV2 4 +#define MCDE_CRA1_CLKSEL_166MHZ 5 +#define MCDE_CRA1_CLKSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CLKSEL, MCDE_CRA1_CLKSEL_##__x) +#define MCDE_CRA1_CLKSEL(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CLKSEL, __x) +#define MCDE_CRA1_CDWIN_SHIFT 13 +#define MCDE_CRA1_CDWIN_MASK 0x0001E000 +#define MCDE_CRA1_CDWIN_8BBP_C1 0 +#define MCDE_CRA1_CDWIN_12BBP_C1 1 +#define MCDE_CRA1_CDWIN_12BBP_C2 2 +#define MCDE_CRA1_CDWIN_16BBP_C1 3 +#define MCDE_CRA1_CDWIN_16BBP_C2 4 +#define MCDE_CRA1_CDWIN_18BBP_C1 5 +#define MCDE_CRA1_CDWIN_18BBP_C2 6 +#define MCDE_CRA1_CDWIN_24BBP 7 +#define MCDE_CRA1_CDWIN_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CDWIN, MCDE_CRA1_CDWIN_##__x) +#define MCDE_CRA1_CDWIN(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CDWIN, __x) +#define MCDE_CRA1_OUTBPP_SHIFT 25 +#define MCDE_CRA1_OUTBPP_MASK 0x1E000000 +#define MCDE_CRA1_OUTBPP_MONO1 0 +#define MCDE_CRA1_OUTBPP_MONO2 1 +#define MCDE_CRA1_OUTBPP_MONO4 2 +#define MCDE_CRA1_OUTBPP_MONO8 3 +#define MCDE_CRA1_OUTBPP_8BPP 4 +#define MCDE_CRA1_OUTBPP_12BPP 5 +#define MCDE_CRA1_OUTBPP_15BPP 6 +#define MCDE_CRA1_OUTBPP_16BPP 7 +#define MCDE_CRA1_OUTBPP_18BPP 8 +#define MCDE_CRA1_OUTBPP_24BPP 9 +#define MCDE_CRA1_OUTBPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA1, OUTBPP, MCDE_CRA1_OUTBPP_##__x) +#define MCDE_CRA1_OUTBPP(__x) \ + MCDE_VAL2REG(MCDE_CRA1, OUTBPP, __x) +#define MCDE_CRA1_BCD_SHIFT 29 +#define MCDE_CRA1_BCD_MASK 0x20000000 +#define MCDE_CRA1_BCD(__x) \ + MCDE_VAL2REG(MCDE_CRA1, BCD, __x) +#define MCDE_CRA1_CLKTYPE_SHIFT 30 +#define MCDE_CRA1_CLKTYPE_MASK 0x40000000 +#define MCDE_CRA1_CLKTYPE_EXTERNAL 0 +#define MCDE_CRA1_CLKTYPE_INTERNAL 1 +#define MCDE_CRA1_CLKTYPE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, MCDE_CRA1_CLKTYPE_##__x) +#define MCDE_CRA1_CLKTYPE(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, __x) +#define MCDE_CRA1_TEFFECTEN_SHIFT 31 +#define MCDE_CRA1_TEFFECTEN_MASK 0x80000000 +#define MCDE_CRA1_TEFFECTEN(__x) \ + MCDE_VAL2REG(MCDE_CRA1, TEFFECTEN, __x) +#define MCDE_CRB1 0x00000A04 +#define MCDE_CRB1_PCD_SHIFT 0 +#define MCDE_CRB1_PCD_MASK 0x000003FF +#define MCDE_CRB1_PCD(__x) \ + MCDE_VAL2REG(MCDE_CRB1, PCD, __x) +#define MCDE_CRB1_CLKSEL_SHIFT 10 +#define MCDE_CRB1_CLKSEL_MASK 0x00001C00 +#define MCDE_CRB1_CLKSEL_LCD 0 +#define MCDE_CRB1_CLKSEL_HDMI 1 +#define MCDE_CRB1_CLKSEL_TV 2 +#define MCDE_CRB1_CLKSEL_EXT_TV1 3 +#define MCDE_CRB1_CLKSEL_EXT_TV2 4 +#define MCDE_CRB1_CLKSEL_166MHZ 5 +#define MCDE_CRB1_CLKSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CLKSEL, MCDE_CRB1_CLKSEL_##__x) +#define MCDE_CRB1_CLKSEL(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CLKSEL, __x) +#define MCDE_CRB1_CDWIN_SHIFT 13 +#define MCDE_CRB1_CDWIN_MASK 0x0001E000 +#define MCDE_CRB1_CDWIN_8BBP_C1 0 +#define MCDE_CRB1_CDWIN_12BBP_C1 1 +#define MCDE_CRB1_CDWIN_12BBP_C2 2 +#define MCDE_CRB1_CDWIN_16BBP_C1 3 +#define MCDE_CRB1_CDWIN_16BBP_C2 4 +#define MCDE_CRB1_CDWIN_18BBP_C1 5 +#define MCDE_CRB1_CDWIN_18BBP_C2 6 +#define MCDE_CRB1_CDWIN_24BBP 7 +#define MCDE_CRB1_CDWIN_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CDWIN, MCDE_CRB1_CDWIN_##__x) +#define MCDE_CRB1_CDWIN(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CDWIN, __x) +#define MCDE_CRB1_OUTBPP_SHIFT 25 +#define MCDE_CRB1_OUTBPP_MASK 0x1E000000 +#define MCDE_CRB1_OUTBPP_MONO1 0 +#define MCDE_CRB1_OUTBPP_MONO2 1 +#define MCDE_CRB1_OUTBPP_MONO4 2 +#define MCDE_CRB1_OUTBPP_MONO8 3 +#define MCDE_CRB1_OUTBPP_8BPP 4 +#define MCDE_CRB1_OUTBPP_12BPP 5 +#define MCDE_CRB1_OUTBPP_15BPP 6 +#define MCDE_CRB1_OUTBPP_16BPP 7 +#define MCDE_CRB1_OUTBPP_18BPP 8 +#define MCDE_CRB1_OUTBPP_24BPP 9 +#define MCDE_CRB1_OUTBPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB1, OUTBPP, MCDE_CRB1_OUTBPP_##__x) +#define MCDE_CRB1_OUTBPP(__x) \ + MCDE_VAL2REG(MCDE_CRB1, OUTBPP, __x) +#define MCDE_CRB1_BCD_SHIFT 29 +#define MCDE_CRB1_BCD_MASK 0x20000000 +#define MCDE_CRB1_BCD(__x) \ + MCDE_VAL2REG(MCDE_CRB1, BCD, __x) +#define MCDE_CRB1_CLKTYPE_SHIFT 30 +#define MCDE_CRB1_CLKTYPE_MASK 0x40000000 +#define MCDE_CRB1_CLKTYPE_EXTERNAL 0 +#define MCDE_CRB1_CLKTYPE_INTERNAL 1 +#define MCDE_CRB1_CLKTYPE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, MCDE_CRB1_CLKTYPE_##__x) +#define MCDE_CRB1_CLKTYPE(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, __x) +#define MCDE_CRB1_TEFFECTEN_SHIFT 31 +#define MCDE_CRB1_TEFFECTEN_MASK 0x80000000 +#define MCDE_CRB1_TEFFECTEN(__x) \ + MCDE_VAL2REG(MCDE_CRB1, TEFFECTEN, __x) +#define MCDE_COLKEYA 0x00000808 +#define MCDE_COLKEYA_GROUPOFFSET 0x200 +#define MCDE_COLKEYA_KEYB_SHIFT 0 +#define MCDE_COLKEYA_KEYB_MASK 0x000000FF +#define MCDE_COLKEYA_KEYB(__x) \ + MCDE_VAL2REG(MCDE_COLKEYA, KEYB, __x) +#define MCDE_COLKEYA_KEYG_SHIFT 8 +#define MCDE_COLKEYA_KEYG_MASK 0x0000FF00 +#define MCDE_COLKEYA_KEYG(__x) \ + MCDE_VAL2REG(MCDE_COLKEYA, KEYG, __x) +#define MCDE_COLKEYA_KEYR_SHIFT 16 +#define MCDE_COLKEYA_KEYR_MASK 0x00FF0000 +#define MCDE_COLKEYA_KEYR(__x) \ + MCDE_VAL2REG(MCDE_COLKEYA, KEYR, __x) +#define MCDE_COLKEYA_KEYA_SHIFT 24 +#define MCDE_COLKEYA_KEYA_MASK 0xFF000000 +#define MCDE_COLKEYA_KEYA(__x) \ + MCDE_VAL2REG(MCDE_COLKEYA, KEYA, __x) +#define MCDE_COLKEYB 0x00000A08 +#define MCDE_COLKEYB_KEYB_SHIFT 0 +#define MCDE_COLKEYB_KEYB_MASK 0x000000FF +#define MCDE_COLKEYB_KEYB(__x) \ + MCDE_VAL2REG(MCDE_COLKEYB, KEYB, __x) +#define MCDE_COLKEYB_KEYG_SHIFT 8 +#define MCDE_COLKEYB_KEYG_MASK 0x0000FF00 +#define MCDE_COLKEYB_KEYG(__x) \ + MCDE_VAL2REG(MCDE_COLKEYB, KEYG, __x) +#define MCDE_COLKEYB_KEYR_SHIFT 16 +#define MCDE_COLKEYB_KEYR_MASK 0x00FF0000 +#define MCDE_COLKEYB_KEYR(__x) \ + MCDE_VAL2REG(MCDE_COLKEYB, KEYR, __x) +#define MCDE_COLKEYB_KEYA_SHIFT 24 +#define MCDE_COLKEYB_KEYA_MASK 0xFF000000 +#define MCDE_COLKEYB_KEYA(__x) \ + MCDE_VAL2REG(MCDE_COLKEYB, KEYA, __x) +#define MCDE_FCOLKEYA 0x0000080C +#define MCDE_FCOLKEYA_GROUPOFFSET 0x200 +#define MCDE_FCOLKEYA_FKEYB_SHIFT 0 +#define MCDE_FCOLKEYA_FKEYB_MASK 0x000000FF +#define MCDE_FCOLKEYA_FKEYB(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYA, FKEYB, __x) +#define MCDE_FCOLKEYA_FKEYG_SHIFT 8 +#define MCDE_FCOLKEYA_FKEYG_MASK 0x0000FF00 +#define MCDE_FCOLKEYA_FKEYG(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYA, FKEYG, __x) +#define MCDE_FCOLKEYA_FKEYR_SHIFT 16 +#define MCDE_FCOLKEYA_FKEYR_MASK 0x00FF0000 +#define MCDE_FCOLKEYA_FKEYR(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYA, FKEYR, __x) +#define MCDE_FCOLKEYA_FKEYA_SHIFT 24 +#define MCDE_FCOLKEYA_FKEYA_MASK 0xFF000000 +#define MCDE_FCOLKEYA_FKEYA(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYA, FKEYA, __x) +#define MCDE_FCOLKEYB 0x00000A0C +#define MCDE_FCOLKEYB_FKEYB_SHIFT 0 +#define MCDE_FCOLKEYB_FKEYB_MASK 0x000000FF +#define MCDE_FCOLKEYB_FKEYB(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYB, FKEYB, __x) +#define MCDE_FCOLKEYB_FKEYG_SHIFT 8 +#define MCDE_FCOLKEYB_FKEYG_MASK 0x0000FF00 +#define MCDE_FCOLKEYB_FKEYG(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYB, FKEYG, __x) +#define MCDE_FCOLKEYB_FKEYR_SHIFT 16 +#define MCDE_FCOLKEYB_FKEYR_MASK 0x00FF0000 +#define MCDE_FCOLKEYB_FKEYR(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYB, FKEYR, __x) +#define MCDE_FCOLKEYB_FKEYA_SHIFT 24 +#define MCDE_FCOLKEYB_FKEYA_MASK 0xFF000000 +#define MCDE_FCOLKEYB_FKEYA(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYB, FKEYA, __x) +#define MCDE_RGBCONV1A 0x00000810 +#define MCDE_RGBCONV1A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV1A_YR_GREEN_SHIFT 0 +#define MCDE_RGBCONV1A_YR_GREEN_MASK 0x000007FF +#define MCDE_RGBCONV1A_YR_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV1A, YR_GREEN, __x) +#define MCDE_RGBCONV1A_YR_RED_SHIFT 16 +#define MCDE_RGBCONV1A_YR_RED_MASK 0x07FF0000 +#define MCDE_RGBCONV1A_YR_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV1A, YR_RED, __x) +#define MCDE_RGBCONV1B 0x00000A10 +#define MCDE_RGBCONV1B_YR_GREEN_SHIFT 0 +#define MCDE_RGBCONV1B_YR_GREEN_MASK 0x000007FF +#define MCDE_RGBCONV1B_YR_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV1B, YR_GREEN, __x) +#define MCDE_RGBCONV1B_YR_RED_SHIFT 16 +#define MCDE_RGBCONV1B_YR_RED_MASK 0x07FF0000 +#define MCDE_RGBCONV1B_YR_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV1B, YR_RED, __x) +#define MCDE_RGBCONV2A 0x00000814 +#define MCDE_RGBCONV2A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV2A_CR_RED_SHIFT 0 +#define MCDE_RGBCONV2A_CR_RED_MASK 0x000007FF +#define MCDE_RGBCONV2A_CR_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV2A, CR_RED, __x) +#define MCDE_RGBCONV2A_YR_BLUE_SHIFT 16 +#define MCDE_RGBCONV2A_YR_BLUE_MASK 0x07FF0000 +#define MCDE_RGBCONV2A_YR_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV2A, YR_BLUE, __x) +#define MCDE_RGBCONV2B 0x00000A14 +#define MCDE_RGBCONV2B_CR_RED_SHIFT 0 +#define MCDE_RGBCONV2B_CR_RED_MASK 0x000007FF +#define MCDE_RGBCONV2B_CR_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV2B, CR_RED, __x) +#define MCDE_RGBCONV2B_YR_BLUE_SHIFT 16 +#define MCDE_RGBCONV2B_YR_BLUE_MASK 0x07FF0000 +#define MCDE_RGBCONV2B_YR_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV2B, YR_BLUE, __x) +#define MCDE_RGBCONV3A 0x00000818 +#define MCDE_RGBCONV3A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV3A_CR_BLUE_SHIFT 0 +#define MCDE_RGBCONV3A_CR_BLUE_MASK 0x000007FF +#define MCDE_RGBCONV3A_CR_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV3A, CR_BLUE, __x) +#define MCDE_RGBCONV3A_CR_GREEN_SHIFT 16 +#define MCDE_RGBCONV3A_CR_GREEN_MASK 0x07FF0000 +#define MCDE_RGBCONV3A_CR_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV3A, CR_GREEN, __x) +#define MCDE_RGBCONV3B 0x00000A18 +#define MCDE_RGBCONV3B_CR_BLUE_SHIFT 0 +#define MCDE_RGBCONV3B_CR_BLUE_MASK 0x000007FF +#define MCDE_RGBCONV3B_CR_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV3B, CR_BLUE, __x) +#define MCDE_RGBCONV3B_CR_GREEN_SHIFT 16 +#define MCDE_RGBCONV3B_CR_GREEN_MASK 0x07FF0000 +#define MCDE_RGBCONV3B_CR_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV3B, CR_GREEN, __x) +#define MCDE_RGBCONV4A 0x0000081C +#define MCDE_RGBCONV4A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV4A_CB_GREEN_SHIFT 0 +#define MCDE_RGBCONV4A_CB_GREEN_MASK 0x000007FF +#define MCDE_RGBCONV4A_CB_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV4A, CB_GREEN, __x) +#define MCDE_RGBCONV4A_CB_RED_SHIFT 16 +#define MCDE_RGBCONV4A_CB_RED_MASK 0x07FF0000 +#define MCDE_RGBCONV4A_CB_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV4A, CB_RED, __x) +#define MCDE_RGBCONV4B 0x00000A1C +#define MCDE_RGBCONV4B_CB_GREEN_SHIFT 0 +#define MCDE_RGBCONV4B_CB_GREEN_MASK 0x000007FF +#define MCDE_RGBCONV4B_CB_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV4B, CB_GREEN, __x) +#define MCDE_RGBCONV4B_CB_RED_SHIFT 16 +#define MCDE_RGBCONV4B_CB_RED_MASK 0x07FF0000 +#define MCDE_RGBCONV4B_CB_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV4B, CB_RED, __x) +#define MCDE_RGBCONV5A 0x00000820 +#define MCDE_RGBCONV5A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV5A_OFF_RED_SHIFT 0 +#define MCDE_RGBCONV5A_OFF_RED_MASK 0x000007FF +#define MCDE_RGBCONV5A_OFF_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV5A, OFF_RED, __x) +#define MCDE_RGBCONV5A_CB_BLUE_SHIFT 16 +#define MCDE_RGBCONV5A_CB_BLUE_MASK 0x07FF0000 +#define MCDE_RGBCONV5A_CB_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV5A, CB_BLUE, __x) +#define MCDE_RGBCONV5B 0x00000A20 +#define MCDE_RGBCONV5B_OFF_RED_SHIFT 0 +#define MCDE_RGBCONV5B_OFF_RED_MASK 0x000007FF +#define MCDE_RGBCONV5B_OFF_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV5B, OFF_RED, __x) +#define MCDE_RGBCONV5B_CB_BLUE_SHIFT 16 +#define MCDE_RGBCONV5B_CB_BLUE_MASK 0x07FF0000 +#define MCDE_RGBCONV5B_CB_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV5B, CB_BLUE, __x) +#define MCDE_RGBCONV6A 0x00000824 +#define MCDE_RGBCONV6A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV6A_OFF_BLUE_SHIFT 0 +#define MCDE_RGBCONV6A_OFF_BLUE_MASK 0x000007FF +#define MCDE_RGBCONV6A_OFF_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV6A, OFF_BLUE, __x) +#define MCDE_RGBCONV6A_OFF_GREEN_SHIFT 16 +#define MCDE_RGBCONV6A_OFF_GREEN_MASK 0x07FF0000 +#define MCDE_RGBCONV6A_OFF_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV6A, OFF_GREEN, __x) +#define MCDE_RGBCONV6B 0x00000A24 +#define MCDE_RGBCONV6B_OFF_BLUE_SHIFT 0 +#define MCDE_RGBCONV6B_OFF_BLUE_MASK 0x000007FF +#define MCDE_RGBCONV6B_OFF_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV6B, OFF_BLUE, __x) +#define MCDE_RGBCONV6B_OFF_GREEN_SHIFT 16 +#define MCDE_RGBCONV6B_OFF_GREEN_MASK 0x07FF0000 +#define MCDE_RGBCONV6B_OFF_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV6B, OFF_GREEN, __x) +#define MCDE_FFCOEFA0 0x00000828 +#define MCDE_FFCOEFA0_GROUPOFFSET 0x200 +#define MCDE_FFCOEFA0_COEFF0_N1_SHIFT 0 +#define MCDE_FFCOEFA0_COEFF0_N1_MASK 0x000000FF +#define MCDE_FFCOEFA0_COEFF0_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N1, __x) +#define MCDE_FFCOEFA0_COEFF0_N2_SHIFT 8 +#define MCDE_FFCOEFA0_COEFF0_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFA0_COEFF0_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N2, __x) +#define MCDE_FFCOEFA0_COEFF0_N3_SHIFT 16 +#define MCDE_FFCOEFA0_COEFF0_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFA0_COEFF0_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N3, __x) +#define MCDE_FFCOEFA0_T0_SHIFT 24 +#define MCDE_FFCOEFA0_T0_MASK 0x0F000000 +#define MCDE_FFCOEFA0_T0(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA0, T0, __x) +#define MCDE_FFCOEFB0 0x00000A28 +#define MCDE_FFCOEFB0_COEFF0_N1_SHIFT 0 +#define MCDE_FFCOEFB0_COEFF0_N1_MASK 0x000000FF +#define MCDE_FFCOEFB0_COEFF0_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N1, __x) +#define MCDE_FFCOEFB0_COEFF0_N2_SHIFT 8 +#define MCDE_FFCOEFB0_COEFF0_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFB0_COEFF0_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N2, __x) +#define MCDE_FFCOEFB0_COEFF0_N3_SHIFT 16 +#define MCDE_FFCOEFB0_COEFF0_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFB0_COEFF0_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N3, __x) +#define MCDE_FFCOEFB0_T0_SHIFT 24 +#define MCDE_FFCOEFB0_T0_MASK 0x0F000000 +#define MCDE_FFCOEFB0_T0(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB0, T0, __x) +#define MCDE_FFCOEFA1 0x0000082C +#define MCDE_FFCOEFA1_GROUPOFFSET 0x200 +#define MCDE_FFCOEFA1_COEFF1_N1_SHIFT 0 +#define MCDE_FFCOEFA1_COEFF1_N1_MASK 0x000000FF +#define MCDE_FFCOEFA1_COEFF1_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N1, __x) +#define MCDE_FFCOEFA1_COEFF1_N2_SHIFT 8 +#define MCDE_FFCOEFA1_COEFF1_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFA1_COEFF1_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N2, __x) +#define MCDE_FFCOEFA1_COEFF1_N3_SHIFT 16 +#define MCDE_FFCOEFA1_COEFF1_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFA1_COEFF1_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N3, __x) +#define MCDE_FFCOEFA1_T1_SHIFT 24 +#define MCDE_FFCOEFA1_T1_MASK 0x0F000000 +#define MCDE_FFCOEFA1_T1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA1, T1, __x) +#define MCDE_FFCOEFB1 0x00000A2C +#define MCDE_FFCOEFB1_COEFF1_N1_SHIFT 0 +#define MCDE_FFCOEFB1_COEFF1_N1_MASK 0x000000FF +#define MCDE_FFCOEFB1_COEFF1_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N1, __x) +#define MCDE_FFCOEFB1_COEFF1_N2_SHIFT 8 +#define MCDE_FFCOEFB1_COEFF1_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFB1_COEFF1_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N2, __x) +#define MCDE_FFCOEFB1_COEFF1_N3_SHIFT 16 +#define MCDE_FFCOEFB1_COEFF1_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFB1_COEFF1_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N3, __x) +#define MCDE_FFCOEFB1_T1_SHIFT 24 +#define MCDE_FFCOEFB1_T1_MASK 0x0F000000 +#define MCDE_FFCOEFB1_T1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB1, T1, __x) +#define MCDE_FFCOEFA2 0x00000830 +#define MCDE_FFCOEFA2_GROUPOFFSET 0x200 +#define MCDE_FFCOEFA2_COEFF2_N1_SHIFT 0 +#define MCDE_FFCOEFA2_COEFF2_N1_MASK 0x000000FF +#define MCDE_FFCOEFA2_COEFF2_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N1, __x) +#define MCDE_FFCOEFA2_COEFF2_N2_SHIFT 8 +#define MCDE_FFCOEFA2_COEFF2_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFA2_COEFF2_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N2, __x) +#define MCDE_FFCOEFA2_COEFF2_N3_SHIFT 16 +#define MCDE_FFCOEFA2_COEFF2_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFA2_COEFF2_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N3, __x) +#define MCDE_FFCOEFA2_T2_SHIFT 24 +#define MCDE_FFCOEFA2_T2_MASK 0x0F000000 +#define MCDE_FFCOEFA2_T2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA2, T2, __x) +#define MCDE_FFCOEFB2 0x00000A30 +#define MCDE_FFCOEFB2_COEFF2_N1_SHIFT 0 +#define MCDE_FFCOEFB2_COEFF2_N1_MASK 0x000000FF +#define MCDE_FFCOEFB2_COEFF2_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N1, __x) +#define MCDE_FFCOEFB2_COEFF2_N2_SHIFT 8 +#define MCDE_FFCOEFB2_COEFF2_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFB2_COEFF2_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N2, __x) +#define MCDE_FFCOEFB2_COEFF2_N3_SHIFT 16 +#define MCDE_FFCOEFB2_COEFF2_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFB2_COEFF2_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N3, __x) +#define MCDE_FFCOEFB2_T2_SHIFT 24 +#define MCDE_FFCOEFB2_T2_MASK 0x0F000000 +#define MCDE_FFCOEFB2_T2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB2, T2, __x) +#define MCDE_TVCRA 0x00000838 +#define MCDE_TVCRA_GROUPOFFSET 0x200 +#define MCDE_TVCRA_SEL_MOD_SHIFT 0 +#define MCDE_TVCRA_SEL_MOD_MASK 0x00000001 +#define MCDE_TVCRA_SEL_MOD_LCD 0 +#define MCDE_TVCRA_SEL_MOD_TV 1 +#define MCDE_TVCRA_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, SEL_MOD, MCDE_TVCRA_SEL_MOD_##__x) +#define MCDE_TVCRA_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, SEL_MOD, __x) +#define MCDE_TVCRA_INTEREN_SHIFT 1 +#define MCDE_TVCRA_INTEREN_MASK 0x00000002 +#define MCDE_TVCRA_INTEREN(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, INTEREN, __x) +#define MCDE_TVCRA_IFIELD_SHIFT 2 +#define MCDE_TVCRA_IFIELD_MASK 0x00000004 +#define MCDE_TVCRA_IFIELD(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, IFIELD, __x) +#define MCDE_TVCRA_TVMODE_SHIFT 3 +#define MCDE_TVCRA_TVMODE_MASK 0x00000038 +#define MCDE_TVCRA_TVMODE_SDTV_656P 0 +#define MCDE_TVCRA_TVMODE_HDTV_480P 1 +#define MCDE_TVCRA_TVMODE_HDTV_720P 2 +#define MCDE_TVCRA_TVMODE_SDTV_656P_LE 3 +#define MCDE_TVCRA_TVMODE_SDTV_656P_BE 4 +#define MCDE_TVCRA_TVMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, TVMODE, MCDE_TVCRA_TVMODE_##__x) +#define MCDE_TVCRA_TVMODE(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, TVMODE, __x) +#define MCDE_TVCRA_SDTVMODE_SHIFT 6 +#define MCDE_TVCRA_SDTVMODE_MASK 0x000000C0 +#define MCDE_TVCRA_SDTVMODE_Y0CBY1CR 0 +#define MCDE_TVCRA_SDTVMODE_CBY0CRY1 1 +#define MCDE_TVCRA_SDTVMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, SDTVMODE, MCDE_TVCRA_SDTVMODE_##__x) +#define MCDE_TVCRA_SDTVMODE(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, SDTVMODE, __x) +#define MCDE_TVCRA_AVRGEN_SHIFT 8 +#define MCDE_TVCRA_AVRGEN_MASK 0x00000100 +#define MCDE_TVCRA_AVRGEN(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, AVRGEN, __x) +#define MCDE_TVCRB 0x00000A38 +#define MCDE_TVCRB_SEL_MOD_SHIFT 0 +#define MCDE_TVCRB_SEL_MOD_MASK 0x00000001 +#define MCDE_TVCRB_SEL_MOD_LCD 0 +#define MCDE_TVCRB_SEL_MOD_TV 1 +#define MCDE_TVCRB_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, SEL_MOD, MCDE_TVCRB_SEL_MOD_##__x) +#define MCDE_TVCRB_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, SEL_MOD, __x) +#define MCDE_TVCRB_INTEREN_SHIFT 1 +#define MCDE_TVCRB_INTEREN_MASK 0x00000002 +#define MCDE_TVCRB_INTEREN(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, INTEREN, __x) +#define MCDE_TVCRB_IFIELD_SHIFT 2 +#define MCDE_TVCRB_IFIELD_MASK 0x00000004 +#define MCDE_TVCRB_IFIELD(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, IFIELD, __x) +#define MCDE_TVCRB_TVMODE_SHIFT 3 +#define MCDE_TVCRB_TVMODE_MASK 0x00000038 +#define MCDE_TVCRB_TVMODE_SDTV_656P 0 +#define MCDE_TVCRB_TVMODE_HDTV_480P 1 +#define MCDE_TVCRB_TVMODE_HDTV_720P 2 +#define MCDE_TVCRB_TVMODE_SDTV_656P_LE 3 +#define MCDE_TVCRB_TVMODE_SDTV_656P_BE 4 +#define MCDE_TVCRB_TVMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, TVMODE, MCDE_TVCRB_TVMODE_##__x) +#define MCDE_TVCRB_TVMODE(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, TVMODE, __x) +#define MCDE_TVCRB_SDTVMODE_SHIFT 6 +#define MCDE_TVCRB_SDTVMODE_MASK 0x000000C0 +#define MCDE_TVCRB_SDTVMODE_Y0CBY1CR 0 +#define MCDE_TVCRB_SDTVMODE_CBY0CRY1 1 +#define MCDE_TVCRB_SDTVMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, SDTVMODE, MCDE_TVCRB_SDTVMODE_##__x) +#define MCDE_TVCRB_SDTVMODE(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, SDTVMODE, __x) +#define MCDE_TVCRB_AVRGEN_SHIFT 8 +#define MCDE_TVCRB_AVRGEN_MASK 0x00000100 +#define MCDE_TVCRB_AVRGEN(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, AVRGEN, __x) +#define MCDE_TVBL1A 0x0000083C +#define MCDE_TVBL1A_GROUPOFFSET 0x200 +#define MCDE_TVBL1A_BEL1_SHIFT 0 +#define MCDE_TVBL1A_BEL1_MASK 0x000007FF +#define MCDE_TVBL1A_BEL1(__x) \ + MCDE_VAL2REG(MCDE_TVBL1A, BEL1, __x) +#define MCDE_TVBL1A_BSL1_SHIFT 16 +#define MCDE_TVBL1A_BSL1_MASK 0x07FF0000 +#define MCDE_TVBL1A_BSL1(__x) \ + MCDE_VAL2REG(MCDE_TVBL1A, BSL1, __x) +#define MCDE_TVBL1B 0x00000A3C +#define MCDE_TVBL1B_BEL1_SHIFT 0 +#define MCDE_TVBL1B_BEL1_MASK 0x000007FF +#define MCDE_TVBL1B_BEL1(__x) \ + MCDE_VAL2REG(MCDE_TVBL1B, BEL1, __x) +#define MCDE_TVBL1B_BSL1_SHIFT 16 +#define MCDE_TVBL1B_BSL1_MASK 0x07FF0000 +#define MCDE_TVBL1B_BSL1(__x) \ + MCDE_VAL2REG(MCDE_TVBL1B, BSL1, __x) +#define MCDE_TVISLA 0x00000840 +#define MCDE_TVISLA_GROUPOFFSET 0x200 +#define MCDE_TVISLA_FSL1_SHIFT 0 +#define MCDE_TVISLA_FSL1_MASK 0x000007FF +#define MCDE_TVISLA_FSL1(__x) \ + MCDE_VAL2REG(MCDE_TVISLA, FSL1, __x) +#define MCDE_TVISLA_FSL2_SHIFT 16 +#define MCDE_TVISLA_FSL2_MASK 0x07FF0000 +#define MCDE_TVISLA_FSL2(__x) \ + MCDE_VAL2REG(MCDE_TVISLA, FSL2, __x) +#define MCDE_TVISLB 0x00000A40 +#define MCDE_TVISLB_FSL1_SHIFT 0 +#define MCDE_TVISLB_FSL1_MASK 0x000007FF +#define MCDE_TVISLB_FSL1(__x) \ + MCDE_VAL2REG(MCDE_TVISLB, FSL1, __x) +#define MCDE_TVISLB_FSL2_SHIFT 16 +#define MCDE_TVISLB_FSL2_MASK 0x07FF0000 +#define MCDE_TVISLB_FSL2(__x) \ + MCDE_VAL2REG(MCDE_TVISLB, FSL2, __x) +#define MCDE_TVDVOA 0x00000844 +#define MCDE_TVDVOA_GROUPOFFSET 0x200 +#define MCDE_TVDVOA_DVO1_SHIFT 0 +#define MCDE_TVDVOA_DVO1_MASK 0x000007FF +#define MCDE_TVDVOA_DVO1(__x) \ + MCDE_VAL2REG(MCDE_TVDVOA, DVO1, __x) +#define MCDE_TVDVOA_DVO2_SHIFT 16 +#define MCDE_TVDVOA_DVO2_MASK 0x07FF0000 +#define MCDE_TVDVOA_DVO2(__x) \ + MCDE_VAL2REG(MCDE_TVDVOA, DVO2, __x) +#define MCDE_TVDVOB 0x00000A44 +#define MCDE_TVDVOB_DVO1_SHIFT 0 +#define MCDE_TVDVOB_DVO1_MASK 0x000007FF +#define MCDE_TVDVOB_DVO1(__x) \ + MCDE_VAL2REG(MCDE_TVDVOB, DVO1, __x) +#define MCDE_TVDVOB_DVO2_SHIFT 16 +#define MCDE_TVDVOB_DVO2_MASK 0x07FF0000 +#define MCDE_TVDVOB_DVO2(__x) \ + MCDE_VAL2REG(MCDE_TVDVOB, DVO2, __x) +#define MCDE_TVTIM1A 0x0000084C +#define MCDE_TVTIM1A_GROUPOFFSET 0x200 +#define MCDE_TVTIM1A_DHO_SHIFT 0 +#define MCDE_TVTIM1A_DHO_MASK 0x000007FF +#define MCDE_TVTIM1A_DHO(__x) \ + MCDE_VAL2REG(MCDE_TVTIM1A, DHO, __x) +#define MCDE_TVTIM1B 0x00000A4C +#define MCDE_TVTIM1B_DHO_SHIFT 0 +#define MCDE_TVTIM1B_DHO_MASK 0x000007FF +#define MCDE_TVTIM1B_DHO(__x) \ + MCDE_VAL2REG(MCDE_TVTIM1B, DHO, __x) +#define MCDE_TVLBALWA 0x00000850 +#define MCDE_TVLBALWA_GROUPOFFSET 0x200 +#define MCDE_TVLBALWA_ALW_SHIFT 0 +#define MCDE_TVLBALWA_ALW_MASK 0x000007FF +#define MCDE_TVLBALWA_ALW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWA, ALW, __x) +#define MCDE_TVLBALWA_LBW_SHIFT 16 +#define MCDE_TVLBALWA_LBW_MASK 0x07FF0000 +#define MCDE_TVLBALWA_LBW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWA, LBW, __x) +#define MCDE_TVLBALWB 0x00000A50 +#define MCDE_TVLBALWB_ALW_SHIFT 0 +#define MCDE_TVLBALWB_ALW_MASK 0x000007FF +#define MCDE_TVLBALWB_ALW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWB, ALW, __x) +#define MCDE_TVLBALWB_LBW_SHIFT 16 +#define MCDE_TVLBALWB_LBW_MASK 0x07FF0000 +#define MCDE_TVLBALWB_LBW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWB, LBW, __x) +#define MCDE_TVBL2A 0x00000854 +#define MCDE_TVBL2A_GROUPOFFSET 0x200 +#define MCDE_TVBL2A_BEL2_SHIFT 0 +#define MCDE_TVBL2A_BEL2_MASK 0x000007FF +#define MCDE_TVBL2A_BEL2(__x) \ + MCDE_VAL2REG(MCDE_TVBL2A, BEL2, __x) +#define MCDE_TVBL2A_BSL2_SHIFT 16 +#define MCDE_TVBL2A_BSL2_MASK 0x07FF0000 +#define MCDE_TVBL2A_BSL2(__x) \ + MCDE_VAL2REG(MCDE_TVBL2A, BSL2, __x) +#define MCDE_TVBL2B 0x00000A54 +#define MCDE_TVBL2B_BEL2_SHIFT 0 +#define MCDE_TVBL2B_BEL2_MASK 0x000007FF +#define MCDE_TVBL2B_BEL2(__x) \ + MCDE_VAL2REG(MCDE_TVBL2B, BEL2, __x) +#define MCDE_TVBL2B_BSL2_SHIFT 16 +#define MCDE_TVBL2B_BSL2_MASK 0x07FF0000 +#define MCDE_TVBL2B_BSL2(__x) \ + MCDE_VAL2REG(MCDE_TVBL2B, BSL2, __x) +#define MCDE_TVBLUA 0x00000858 +#define MCDE_TVBLUA_GROUPOFFSET 0x200 +#define MCDE_TVBLUA_TVBLU_SHIFT 0 +#define MCDE_TVBLUA_TVBLU_MASK 0x000000FF +#define MCDE_TVBLUA_TVBLU(__x) \ + MCDE_VAL2REG(MCDE_TVBLUA, TVBLU, __x) +#define MCDE_TVBLUA_TVBCB_SHIFT 8 +#define MCDE_TVBLUA_TVBCB_MASK 0x0000FF00 +#define MCDE_TVBLUA_TVBCB(__x) \ + MCDE_VAL2REG(MCDE_TVBLUA, TVBCB, __x) +#define MCDE_TVBLUA_TVBCR_SHIFT 16 +#define MCDE_TVBLUA_TVBCR_MASK 0x00FF0000 +#define MCDE_TVBLUA_TVBCR(__x) \ + MCDE_VAL2REG(MCDE_TVBLUA, TVBCR, __x) +#define MCDE_TVBLUB 0x00000A58 +#define MCDE_TVBLUB_TVBLU_SHIFT 0 +#define MCDE_TVBLUB_TVBLU_MASK 0x000000FF +#define MCDE_TVBLUB_TVBLU(__x) \ + MCDE_VAL2REG(MCDE_TVBLUB, TVBLU, __x) +#define MCDE_TVBLUB_TVBCB_SHIFT 8 +#define MCDE_TVBLUB_TVBCB_MASK 0x0000FF00 +#define MCDE_TVBLUB_TVBCB(__x) \ + MCDE_VAL2REG(MCDE_TVBLUB, TVBCB, __x) +#define MCDE_TVBLUB_TVBCR_SHIFT 16 +#define MCDE_TVBLUB_TVBCR_MASK 0x00FF0000 +#define MCDE_TVBLUB_TVBCR(__x) \ + MCDE_VAL2REG(MCDE_TVBLUB, TVBCR, __x) +#define MCDE_LCDTIM0A 0x0000085C +#define MCDE_LCDTIM0A_GROUPOFFSET 0x200 +#define MCDE_LCDTIM0A_PSDEL0_SHIFT 0 +#define MCDE_LCDTIM0A_PSDEL0_MASK 0x000000FF +#define MCDE_LCDTIM0A_PSDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSDEL0, __x) +#define MCDE_LCDTIM0A_PSDEL1_SHIFT 1 +#define MCDE_LCDTIM0A_PSDEL1_MASK 0x0000001E +#define MCDE_LCDTIM0A_PSDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSDEL1, __x) +#define MCDE_LCDTIM0A_PSLOADSEL_SHIFT 12 +#define MCDE_LCDTIM0A_PSLOADSEL_MASK 0x00003000 +#define MCDE_LCDTIM0A_PSLOADSEL_HBP 0 +#define MCDE_LCDTIM0A_PSLOADSEL_CLP 1 +#define MCDE_LCDTIM0A_PSLOADSEL_HFP 2 +#define MCDE_LCDTIM0A_PSLOADSEL_HSW 3 +#define MCDE_LCDTIM0A_PSLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSLOADSEL, MCDE_LCDTIM0A_PSLOADSEL_##__x) +#define MCDE_LCDTIM0A_PSLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSLOADSEL, __x) +#define MCDE_LCDTIM0A_PSTGEN_SHIFT 14 +#define MCDE_LCDTIM0A_PSTGEN_MASK 0x00004000 +#define MCDE_LCDTIM0A_PSTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSTGEN, __x) +#define MCDE_LCDTIM0A_PSVAEN_SHIFT 15 +#define MCDE_LCDTIM0A_PSVAEN_MASK 0x00008000 +#define MCDE_LCDTIM0A_PSVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSVAEN, __x) +#define MCDE_LCDTIM0A_REVDEL0_SHIFT 16 +#define MCDE_LCDTIM0A_REVDEL0_MASK 0x00FF0000 +#define MCDE_LCDTIM0A_REVDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVDEL0, __x) +#define MCDE_LCDTIM0A_REVDEL1_SHIFT 24 +#define MCDE_LCDTIM0A_REVDEL1_MASK 0x0F000000 +#define MCDE_LCDTIM0A_REVDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVDEL1, __x) +#define MCDE_LCDTIM0A_REVLOADSEL_SHIFT 28 +#define MCDE_LCDTIM0A_REVLOADSEL_MASK 0x30000000 +#define MCDE_LCDTIM0A_REVLOADSEL_HBP 0 +#define MCDE_LCDTIM0A_REVLOADSEL_CLP 1 +#define MCDE_LCDTIM0A_REVLOADSEL_HFP 2 +#define MCDE_LCDTIM0A_REVLOADSEL_HSW 3 +#define MCDE_LCDTIM0A_REVLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVLOADSEL, MCDE_LCDTIM0A_REVLOADSEL_##__x) +#define MCDE_LCDTIM0A_REVLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVLOADSEL, __x) +#define MCDE_LCDTIM0A_REVTGEN_SHIFT 30 +#define MCDE_LCDTIM0A_REVTGEN_MASK 0x40000000 +#define MCDE_LCDTIM0A_REVTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVTGEN, __x) +#define MCDE_LCDTIM0A_REVVAEN_SHIFT 31 +#define MCDE_LCDTIM0A_REVVAEN_MASK 0x80000000 +#define MCDE_LCDTIM0A_REVVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVVAEN, __x) +#define MCDE_LCDTIM0B 0x00000A5C +#define MCDE_LCDTIM0B_PSDEL0_SHIFT 0 +#define MCDE_LCDTIM0B_PSDEL0_MASK 0x000000FF +#define MCDE_LCDTIM0B_PSDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSDEL0, __x) +#define MCDE_LCDTIM0B_PSDEL1_SHIFT 1 +#define MCDE_LCDTIM0B_PSDEL1_MASK 0x0000001E +#define MCDE_LCDTIM0B_PSDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSDEL1, __x) +#define MCDE_LCDTIM0B_PSLOADSEL_SHIFT 12 +#define MCDE_LCDTIM0B_PSLOADSEL_MASK 0x00003000 +#define MCDE_LCDTIM0B_PSLOADSEL_HBP 0 +#define MCDE_LCDTIM0B_PSLOADSEL_CLP 1 +#define MCDE_LCDTIM0B_PSLOADSEL_HFP 2 +#define MCDE_LCDTIM0B_PSLOADSEL_HSW 3 +#define MCDE_LCDTIM0B_PSLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSLOADSEL, MCDE_LCDTIM0B_PSLOADSEL_##__x) +#define MCDE_LCDTIM0B_PSLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSLOADSEL, __x) +#define MCDE_LCDTIM0B_PSTGEN_SHIFT 14 +#define MCDE_LCDTIM0B_PSTGEN_MASK 0x00004000 +#define MCDE_LCDTIM0B_PSTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSTGEN, __x) +#define MCDE_LCDTIM0B_PSVAEN_SHIFT 15 +#define MCDE_LCDTIM0B_PSVAEN_MASK 0x00008000 +#define MCDE_LCDTIM0B_PSVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSVAEN, __x) +#define MCDE_LCDTIM0B_REVDEL0_SHIFT 16 +#define MCDE_LCDTIM0B_REVDEL0_MASK 0x00FF0000 +#define MCDE_LCDTIM0B_REVDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVDEL0, __x) +#define MCDE_LCDTIM0B_REVDEL1_SHIFT 24 +#define MCDE_LCDTIM0B_REVDEL1_MASK 0x0F000000 +#define MCDE_LCDTIM0B_REVDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVDEL1, __x) +#define MCDE_LCDTIM0B_REVLOADSEL_SHIFT 28 +#define MCDE_LCDTIM0B_REVLOADSEL_MASK 0x30000000 +#define MCDE_LCDTIM0B_REVLOADSEL_HBP 0 +#define MCDE_LCDTIM0B_REVLOADSEL_CLP 1 +#define MCDE_LCDTIM0B_REVLOADSEL_HFP 2 +#define MCDE_LCDTIM0B_REVLOADSEL_HSW 3 +#define MCDE_LCDTIM0B_REVLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVLOADSEL, MCDE_LCDTIM0B_REVLOADSEL_##__x) +#define MCDE_LCDTIM0B_REVLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVLOADSEL, __x) +#define MCDE_LCDTIM0B_REVTGEN_SHIFT 30 +#define MCDE_LCDTIM0B_REVTGEN_MASK 0x40000000 +#define MCDE_LCDTIM0B_REVTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVTGEN, __x) +#define MCDE_LCDTIM0B_REVVAEN_SHIFT 31 +#define MCDE_LCDTIM0B_REVVAEN_MASK 0x80000000 +#define MCDE_LCDTIM0B_REVVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVVAEN, __x) +#define MCDE_LCDTIM1A 0x00000860 +#define MCDE_LCDTIM1A_GROUPOFFSET 0x200 +#define MCDE_LCDTIM1A_SPLDEL0_SHIFT 0 +#define MCDE_LCDTIM1A_SPLDEL0_MASK 0x000000FF +#define MCDE_LCDTIM1A_SPLDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLDEL0, __x) +#define MCDE_LCDTIM1A_SPLDEL1_SHIFT 8 +#define MCDE_LCDTIM1A_SPLDEL1_MASK 0x00000F00 +#define MCDE_LCDTIM1A_SPLDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLDEL1, __x) +#define MCDE_LCDTIM1A_SPLLOADSEL_SHIFT 12 +#define MCDE_LCDTIM1A_SPLLOADSEL_MASK 0x00003000 +#define MCDE_LCDTIM1A_SPLLOADSEL_HBP 0 +#define MCDE_LCDTIM1A_SPLLOADSEL_CLP 1 +#define MCDE_LCDTIM1A_SPLLOADSEL_HFP 2 +#define MCDE_LCDTIM1A_SPLLOADSEL_HSW 3 +#define MCDE_LCDTIM1A_SPLLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLLOADSEL, MCDE_LCDTIM1A_SPLLOADSEL_##__x) +#define MCDE_LCDTIM1A_SPLLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLLOADSEL, __x) +#define MCDE_LCDTIM1A_SPLTGEN_SHIFT 14 +#define MCDE_LCDTIM1A_SPLTGEN_MASK 0x00004000 +#define MCDE_LCDTIM1A_SPLTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLTGEN, __x) +#define MCDE_LCDTIM1A_SPLVAEN_SHIFT 15 +#define MCDE_LCDTIM1A_SPLVAEN_MASK 0x00008000 +#define MCDE_LCDTIM1A_SPLVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLVAEN, __x) +#define MCDE_LCDTIM1A_ICLSP_SHIFT 16 +#define MCDE_LCDTIM1A_ICLSP_MASK 0x00010000 +#define MCDE_LCDTIM1A_ICLSP(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, ICLSP, __x) +#define MCDE_LCDTIM1A_ICLREV_SHIFT 17 +#define MCDE_LCDTIM1A_ICLREV_MASK 0x00020000 +#define MCDE_LCDTIM1A_ICLREV(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, ICLREV, __x) +#define MCDE_LCDTIM1A_LCLSPL_SHIFT 18 +#define MCDE_LCDTIM1A_LCLSPL_MASK 0x00040000 +#define MCDE_LCDTIM1A_LCLSPL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, LCLSPL, __x) +#define MCDE_LCDTIM1A_IVP_SHIFT 19 +#define MCDE_LCDTIM1A_IVP_MASK 0x00080000 +#define MCDE_LCDTIM1A_IVP(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IVP, __x) +#define MCDE_LCDTIM1A_IVS_SHIFT 20 +#define MCDE_LCDTIM1A_IVS_MASK 0x00100000 +#define MCDE_LCDTIM1A_IVS(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IVS, __x) +#define MCDE_LCDTIM1A_IHS_SHIFT 21 +#define MCDE_LCDTIM1A_IHS_MASK 0x00200000 +#define MCDE_LCDTIM1A_IHS(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IHS, __x) +#define MCDE_LCDTIM1A_IPC_SHIFT 22 +#define MCDE_LCDTIM1A_IPC_MASK 0x00400000 +#define MCDE_LCDTIM1A_IPC(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IPC, __x) +#define MCDE_LCDTIM1A_IOE_SHIFT 23 +#define MCDE_LCDTIM1A_IOE_MASK 0x00800000 +#define MCDE_LCDTIM1A_IOE(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IOE, __x) +#define MCDE_LCDTIM1B 0x00000A60 +#define MCDE_LCDTIM1B_SPLDEL0_SHIFT 0 +#define MCDE_LCDTIM1B_SPLDEL0_MASK 0x000000FF +#define MCDE_LCDTIM1B_SPLDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLDEL0, __x) +#define MCDE_LCDTIM1B_SPLDEL1_SHIFT 8 +#define MCDE_LCDTIM1B_SPLDEL1_MASK 0x00000F00 +#define MCDE_LCDTIM1B_SPLDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLDEL1, __x) +#define MCDE_LCDTIM1B_SPLLOADSEL_SHIFT 12 +#define MCDE_LCDTIM1B_SPLLOADSEL_MASK 0x00003000 +#define MCDE_LCDTIM1B_SPLLOADSEL_HBP 0 +#define MCDE_LCDTIM1B_SPLLOADSEL_CLP 1 +#define MCDE_LCDTIM1B_SPLLOADSEL_HFP 2 +#define MCDE_LCDTIM1B_SPLLOADSEL_HSW 3 +#define MCDE_LCDTIM1B_SPLLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLLOADSEL, MCDE_LCDTIM1B_SPLLOADSEL_##__x) +#define MCDE_LCDTIM1B_SPLLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLLOADSEL, __x) +#define MCDE_LCDTIM1B_SPLTGEN_SHIFT 14 +#define MCDE_LCDTIM1B_SPLTGEN_MASK 0x00004000 +#define MCDE_LCDTIM1B_SPLTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLTGEN, __x) +#define MCDE_LCDTIM1B_SPLVAEN_SHIFT 15 +#define MCDE_LCDTIM1B_SPLVAEN_MASK 0x00008000 +#define MCDE_LCDTIM1B_SPLVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLVAEN, __x) +#define MCDE_LCDTIM1B_ICLSP_SHIFT 16 +#define MCDE_LCDTIM1B_ICLSP_MASK 0x00010000 +#define MCDE_LCDTIM1B_ICLSP(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, ICLSP, __x) +#define MCDE_LCDTIM1B_ICLREV_SHIFT 17 +#define MCDE_LCDTIM1B_ICLREV_MASK 0x00020000 +#define MCDE_LCDTIM1B_ICLREV(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, ICLREV, __x) +#define MCDE_LCDTIM1B_LCLSPL_SHIFT 18 +#define MCDE_LCDTIM1B_LCLSPL_MASK 0x00040000 +#define MCDE_LCDTIM1B_LCLSPL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, LCLSPL, __x) +#define MCDE_LCDTIM1B_IVP_SHIFT 19 +#define MCDE_LCDTIM1B_IVP_MASK 0x00080000 +#define MCDE_LCDTIM1B_IVP(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IVP, __x) +#define MCDE_LCDTIM1B_IVS_SHIFT 20 +#define MCDE_LCDTIM1B_IVS_MASK 0x00100000 +#define MCDE_LCDTIM1B_IVS(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IVS, __x) +#define MCDE_LCDTIM1B_IHS_SHIFT 21 +#define MCDE_LCDTIM1B_IHS_MASK 0x00200000 +#define MCDE_LCDTIM1B_IHS(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IHS, __x) +#define MCDE_LCDTIM1B_IPC_SHIFT 22 +#define MCDE_LCDTIM1B_IPC_MASK 0x00400000 +#define MCDE_LCDTIM1B_IPC(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IPC, __x) +#define MCDE_LCDTIM1B_IOE_SHIFT 23 +#define MCDE_LCDTIM1B_IOE_MASK 0x00800000 +#define MCDE_LCDTIM1B_IOE(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IOE, __x) +#define MCDE_DITCTRLA 0x00000864 +#define MCDE_DITCTRLA_GROUPOFFSET 0x200 +#define MCDE_DITCTRLA_TEMP_SHIFT 0 +#define MCDE_DITCTRLA_TEMP_MASK 0x00000001 +#define MCDE_DITCTRLA_TEMP(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, TEMP, __x) +#define MCDE_DITCTRLA_COMP_SHIFT 1 +#define MCDE_DITCTRLA_COMP_MASK 0x00000002 +#define MCDE_DITCTRLA_COMP(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, COMP, __x) +#define MCDE_DITCTRLA_MASK_SHIFT 4 +#define MCDE_DITCTRLA_MASK_MASK 0x00000010 +#define MCDE_DITCTRLA_MASK(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, MASK, __x) +#define MCDE_DITCTRLA_FOFFX_SHIFT 5 +#define MCDE_DITCTRLA_FOFFX_MASK 0x000003E0 +#define MCDE_DITCTRLA_FOFFX(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, FOFFX, __x) +#define MCDE_DITCTRLA_FOFFY_SHIFT 10 +#define MCDE_DITCTRLA_FOFFY_MASK 0x00007C00 +#define MCDE_DITCTRLA_FOFFY(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, FOFFY, __x) +#define MCDE_DITCTRLB 0x00000A64 +#define MCDE_DITCTRLB_TEMP_SHIFT 0 +#define MCDE_DITCTRLB_TEMP_MASK 0x00000001 +#define MCDE_DITCTRLB_TEMP(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, TEMP, __x) +#define MCDE_DITCTRLB_COMP_SHIFT 1 +#define MCDE_DITCTRLB_COMP_MASK 0x00000002 +#define MCDE_DITCTRLB_COMP(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, COMP, __x) +#define MCDE_DITCTRLB_MASK_SHIFT 4 +#define MCDE_DITCTRLB_MASK_MASK 0x00000010 +#define MCDE_DITCTRLB_MASK(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, MASK, __x) +#define MCDE_DITCTRLB_FOFFX_SHIFT 5 +#define MCDE_DITCTRLB_FOFFX_MASK 0x000003E0 +#define MCDE_DITCTRLB_FOFFX(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, FOFFX, __x) +#define MCDE_DITCTRLB_FOFFY_SHIFT 10 +#define MCDE_DITCTRLB_FOFFY_MASK 0x00007C00 +#define MCDE_DITCTRLB_FOFFY(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, FOFFY, __x) +#define MCDE_DITOFFA 0x00000868 +#define MCDE_DITOFFA_GROUPOFFSET 0x200 +#define MCDE_DITOFFA_XG_SHIFT 0 +#define MCDE_DITOFFA_XG_MASK 0x0000001F +#define MCDE_DITOFFA_XG(__x) \ + MCDE_VAL2REG(MCDE_DITOFFA, XG, __x) +#define MCDE_DITOFFA_YG_SHIFT 8 +#define MCDE_DITOFFA_YG_MASK 0x00001F00 +#define MCDE_DITOFFA_YG(__x) \ + MCDE_VAL2REG(MCDE_DITOFFA, YG, __x) +#define MCDE_DITOFFA_XB_SHIFT 16 +#define MCDE_DITOFFA_XB_MASK 0x001F0000 +#define MCDE_DITOFFA_XB(__x) \ + MCDE_VAL2REG(MCDE_DITOFFA, XB, __x) +#define MCDE_DITOFFA_YB_SHIFT 24 +#define MCDE_DITOFFA_YB_MASK 0x1F000000 +#define MCDE_DITOFFA_YB(__x) \ + MCDE_VAL2REG(MCDE_DITOFFA, YB, __x) +#define MCDE_DITOFFB 0x00000A68 +#define MCDE_DITOFFB_XG_SHIFT 0 +#define MCDE_DITOFFB_XG_MASK 0x0000001F +#define MCDE_DITOFFB_XG(__x) \ + MCDE_VAL2REG(MCDE_DITOFFB, XG, __x) +#define MCDE_DITOFFB_YG_SHIFT 8 +#define MCDE_DITOFFB_YG_MASK 0x00001F00 +#define MCDE_DITOFFB_YG(__x) \ + MCDE_VAL2REG(MCDE_DITOFFB, YG, __x) +#define MCDE_DITOFFB_XB_SHIFT 16 +#define MCDE_DITOFFB_XB_MASK 0x001F0000 +#define MCDE_DITOFFB_XB(__x) \ + MCDE_VAL2REG(MCDE_DITOFFB, XB, __x) +#define MCDE_DITOFFB_YB_SHIFT 24 +#define MCDE_DITOFFB_YB_MASK 0x1F000000 +#define MCDE_DITOFFB_YB(__x) \ + MCDE_VAL2REG(MCDE_DITOFFB, YB, __x) +#define MCDE_PAL0A 0x0000086C +#define MCDE_PAL0A_GROUPOFFSET 0x200 +#define MCDE_PAL0A_BLUE_SHIFT 0 +#define MCDE_PAL0A_BLUE_MASK 0x00000FFF +#define MCDE_PAL0A_BLUE(__x) \ + MCDE_VAL2REG(MCDE_PAL0A, BLUE, __x) +#define MCDE_PAL0A_GREEN_SHIFT 16 +#define MCDE_PAL0A_GREEN_MASK 0x0FFF0000 +#define MCDE_PAL0A_GREEN(__x) \ + MCDE_VAL2REG(MCDE_PAL0A, GREEN, __x) +#define MCDE_PAL0B 0x00000A6C +#define MCDE_PAL0B_BLUE_SHIFT 0 +#define MCDE_PAL0B_BLUE_MASK 0x00000FFF +#define MCDE_PAL0B_BLUE(__x) \ + MCDE_VAL2REG(MCDE_PAL0B, BLUE, __x) +#define MCDE_PAL0B_GREEN_SHIFT 16 +#define MCDE_PAL0B_GREEN_MASK 0x0FFF0000 +#define MCDE_PAL0B_GREEN(__x) \ + MCDE_VAL2REG(MCDE_PAL0B, GREEN, __x) +#define MCDE_PAL1A 0x00000870 +#define MCDE_PAL1A_GROUPOFFSET 0x200 +#define MCDE_PAL1A_RED_SHIFT 0 +#define MCDE_PAL1A_RED_MASK 0x00000FFF +#define MCDE_PAL1A_RED(__x) \ + MCDE_VAL2REG(MCDE_PAL1A, RED, __x) +#define MCDE_PAL1B 0x00000A70 +#define MCDE_PAL1B_RED_SHIFT 0 +#define MCDE_PAL1B_RED_MASK 0x00000FFF +#define MCDE_PAL1B_RED(__x) \ + MCDE_VAL2REG(MCDE_PAL1B, RED, __x) +#define MCDE_ROTADD0A 0x00000874 +#define MCDE_ROTADD0A_GROUPOFFSET 0x200 +#define MCDE_ROTADD0A_ROTADD0_SHIFT 0 +#define MCDE_ROTADD0A_ROTADD0_MASK 0xFFFFFFFF +#define MCDE_ROTADD0A_ROTADD0(__x) \ + MCDE_VAL2REG(MCDE_ROTADD0A, ROTADD0, __x) +#define MCDE_ROTADD0B 0x00000A74 +#define MCDE_ROTADD0B_ROTADD0_SHIFT 0 +#define MCDE_ROTADD0B_ROTADD0_MASK 0xFFFFFFFF +#define MCDE_ROTADD0B_ROTADD0(__x) \ + MCDE_VAL2REG(MCDE_ROTADD0B, ROTADD0, __x) +#define MCDE_ROTADD1A 0x00000878 +#define MCDE_ROTADD1A_GROUPOFFSET 0x200 +#define MCDE_ROTADD1A_ROTADD1_SHIFT 0 +#define MCDE_ROTADD1A_ROTADD1_MASK 0xFFFFFFFF +#define MCDE_ROTADD1A_ROTADD1(__x) \ + MCDE_VAL2REG(MCDE_ROTADD1A, ROTADD1, __x) +#define MCDE_ROTADD1B 0x00000A78 +#define MCDE_ROTADD1B_ROTADD1_SHIFT 0 +#define MCDE_ROTADD1B_ROTADD1_MASK 0xFFFFFFFF +#define MCDE_ROTADD1B_ROTADD1(__x) \ + MCDE_VAL2REG(MCDE_ROTADD1B, ROTADD1, __x) +#define MCDE_ROTACONF 0x0000087C +#define MCDE_ROTACONF_GROUPOFFSET 0x200 +#define MCDE_ROTACONF_ROTBURSTSIZE_SHIFT 0 +#define MCDE_ROTACONF_ROTBURSTSIZE_MASK 0x00000003 +#define MCDE_ROTACONF_ROTBURSTSIZE_1W 0 +#define MCDE_ROTACONF_ROTBURSTSIZE_2W 1 +#define MCDE_ROTACONF_ROTBURSTSIZE_4W 2 +#define MCDE_ROTACONF_ROTBURSTSIZE_8W 3 +#define MCDE_ROTACONF_ROTBURSTSIZE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE, \ + MCDE_ROTACONF_ROTBURSTSIZE_##__x) +#define MCDE_ROTACONF_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE, __x) +#define MCDE_ROTACONF_ROTBURSTSIZE_HW_SHIFT 2 +#define MCDE_ROTACONF_ROTBURSTSIZE_HW_MASK 0x00000004 +#define MCDE_ROTACONF_ROTBURSTSIZE_HW(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE_HW, __x) +#define MCDE_ROTACONF_ROTDIR_SHIFT 3 +#define MCDE_ROTACONF_ROTDIR_MASK 0x00000008 +#define MCDE_ROTACONF_ROTDIR_CCW 0 +#define MCDE_ROTACONF_ROTDIR_CW 1 +#define MCDE_ROTACONF_ROTDIR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTDIR, MCDE_ROTACONF_ROTDIR_##__x) +#define MCDE_ROTACONF_ROTDIR(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTDIR, __x) +#define MCDE_ROTACONF_WR_MAXOUT_SHIFT 4 +#define MCDE_ROTACONF_WR_MAXOUT_MASK 0x00000030 +#define MCDE_ROTACONF_WR_MAXOUT(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, WR_MAXOUT, __x) +#define MCDE_ROTACONF_RD_MAXOUT_SHIFT 6 +#define MCDE_ROTACONF_RD_MAXOUT_MASK 0x000000C0 +#define MCDE_ROTACONF_RD_MAXOUT(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, RD_MAXOUT, __x) +#define MCDE_ROTACONF_STRIP_WIDTH_SHIFT 8 +#define MCDE_ROTACONF_STRIP_WIDTH_MASK 0x0000FF00 +#define MCDE_ROTACONF_STRIP_WIDTH_2PIX 0 +#define MCDE_ROTACONF_STRIP_WIDTH_4PIX 1 +#define MCDE_ROTACONF_STRIP_WIDTH_8PIX 2 +#define MCDE_ROTACONF_STRIP_WIDTH_16PIX 3 +#define MCDE_ROTACONF_STRIP_WIDTH_32PIX 4 +#define MCDE_ROTACONF_STRIP_WIDTH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, STRIP_WIDTH, \ + MCDE_ROTACONF_STRIP_WIDTH_##__x) +#define MCDE_ROTACONF_STRIP_WIDTH(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, STRIP_WIDTH, __x) +#define MCDE_ROTACONF_WR_ROPC_SHIFT 16 +#define MCDE_ROTACONF_WR_ROPC_MASK 0x00FF0000 +#define MCDE_ROTACONF_WR_ROPC(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, WR_ROPC, __x) +#define MCDE_ROTACONF_RD_ROPC_SHIFT 24 +#define MCDE_ROTACONF_RD_ROPC_MASK 0xFF000000 +#define MCDE_ROTACONF_RD_ROPC(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, RD_ROPC, __x) +#define MCDE_ROTBCONF 0x00000A7C +#define MCDE_ROTBCONF_ROTBURSTSIZE_SHIFT 0 +#define MCDE_ROTBCONF_ROTBURSTSIZE_MASK 0x00000003 +#define MCDE_ROTBCONF_ROTBURSTSIZE_1W 0 +#define MCDE_ROTBCONF_ROTBURSTSIZE_2W 1 +#define MCDE_ROTBCONF_ROTBURSTSIZE_4W 2 +#define MCDE_ROTBCONF_ROTBURSTSIZE_8W 3 +#define MCDE_ROTBCONF_ROTBURSTSIZE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE, \ + MCDE_ROTBCONF_ROTBURSTSIZE_##__x) +#define MCDE_ROTBCONF_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE, __x) +#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_SHIFT 2 +#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_MASK 0x00000004 +#define MCDE_ROTBCONF_ROTBURSTSIZE_HW(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE_HW, __x) +#define MCDE_ROTBCONF_ROTDIR_SHIFT 3 +#define MCDE_ROTBCONF_ROTDIR_MASK 0x00000008 +#define MCDE_ROTBCONF_ROTDIR_CCW 0 +#define MCDE_ROTBCONF_ROTDIR_CW 1 +#define MCDE_ROTBCONF_ROTDIR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTDIR, MCDE_ROTBCONF_ROTDIR_##__x) +#define MCDE_ROTBCONF_ROTDIR(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTDIR, __x) +#define MCDE_ROTBCONF_WR_MAXOUT_SHIFT 4 +#define MCDE_ROTBCONF_WR_MAXOUT_MASK 0x00000030 +#define MCDE_ROTBCONF_WR_MAXOUT(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, WR_MAXOUT, __x) +#define MCDE_ROTBCONF_RD_MAXOUT_SHIFT 6 +#define MCDE_ROTBCONF_RD_MAXOUT_MASK 0x000000C0 +#define MCDE_ROTBCONF_RD_MAXOUT(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, RD_MAXOUT, __x) +#define MCDE_ROTBCONF_STRIP_WIDTH_SHIFT 8 +#define MCDE_ROTBCONF_STRIP_WIDTH_MASK 0x0000FF00 +#define MCDE_ROTBCONF_STRIP_WIDTH_2PIX 0 +#define MCDE_ROTBCONF_STRIP_WIDTH_4PIX 1 +#define MCDE_ROTBCONF_STRIP_WIDTH_8PIX 2 +#define MCDE_ROTBCONF_STRIP_WIDTH_16PIX 3 +#define MCDE_ROTBCONF_STRIP_WIDTH_32PIX 4 +#define MCDE_ROTBCONF_STRIP_WIDTH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, STRIP_WIDTH, \ + MCDE_ROTBCONF_STRIP_WIDTH_##__x) +#define MCDE_ROTBCONF_STRIP_WIDTH(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, STRIP_WIDTH, __x) +#define MCDE_ROTBCONF_WR_ROPC_SHIFT 16 +#define MCDE_ROTBCONF_WR_ROPC_MASK 0x00FF0000 +#define MCDE_ROTBCONF_WR_ROPC(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, WR_ROPC, __x) +#define MCDE_ROTBCONF_RD_ROPC_SHIFT 24 +#define MCDE_ROTBCONF_RD_ROPC_MASK 0xFF000000 +#define MCDE_ROTBCONF_RD_ROPC(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, RD_ROPC, __x) +#define MCDE_SYNCHCONFA 0x00000880 +#define MCDE_SYNCHCONFA_GROUPOFFSET 0x200 +#define MCDE_SYNCHCONFA_HWREQVEVENT_SHIFT 0 +#define MCDE_SYNCHCONFA_HWREQVEVENT_MASK 0x00000003 +#define MCDE_SYNCHCONFA_HWREQVEVENT_VSYNC 0 +#define MCDE_SYNCHCONFA_HWREQVEVENT_BACK_PORCH 1 +#define MCDE_SYNCHCONFA_HWREQVEVENT_ACTIVE_VIDEO 2 +#define MCDE_SYNCHCONFA_HWREQVEVENT_FRONT_PORCH 3 +#define MCDE_SYNCHCONFA_HWREQVEVENT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, HWREQVEVENT, \ + MCDE_SYNCHCONFA_HWREQVEVENT_##__x) +#define MCDE_SYNCHCONFA_HWREQVEVENT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, HWREQVEVENT, __x) +#define MCDE_SYNCHCONFA_HWREQVCNT_SHIFT 2 +#define MCDE_SYNCHCONFA_HWREQVCNT_MASK 0x0000FFFC +#define MCDE_SYNCHCONFA_HWREQVCNT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, HWREQVCNT, __x) +#define MCDE_SYNCHCONFA_SWINTVEVENT_SHIFT 16 +#define MCDE_SYNCHCONFA_SWINTVEVENT_MASK 0x00030000 +#define MCDE_SYNCHCONFA_SWINTVEVENT_VSYNC 0 +#define MCDE_SYNCHCONFA_SWINTVEVENT_BACK_PORCH 1 +#define MCDE_SYNCHCONFA_SWINTVEVENT_ACTIVE_VIDEO 2 +#define MCDE_SYNCHCONFA_SWINTVEVENT_FRONT_PORCH 3 +#define MCDE_SYNCHCONFA_SWINTVEVENT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, SWINTVEVENT, \ + MCDE_SYNCHCONFA_SWINTVEVENT_##__x) +#define MCDE_SYNCHCONFA_SWINTVEVENT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, SWINTVEVENT, __x) +#define MCDE_SYNCHCONFA_SWINTVCNT_SHIFT 18 +#define MCDE_SYNCHCONFA_SWINTVCNT_MASK 0xFFFC0000 +#define MCDE_SYNCHCONFA_SWINTVCNT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, SWINTVCNT, __x) +#define MCDE_SYNCHCONFB 0x00000A80 +#define MCDE_SYNCHCONFB_HWREQVEVENT_SHIFT 0 +#define MCDE_SYNCHCONFB_HWREQVEVENT_MASK 0x00000003 +#define MCDE_SYNCHCONFB_HWREQVEVENT_VSYNC 0 +#define MCDE_SYNCHCONFB_HWREQVEVENT_BACK_PORCH 1 +#define MCDE_SYNCHCONFB_HWREQVEVENT_ACTIVE_VIDEO 2 +#define MCDE_SYNCHCONFB_HWREQVEVENT_FRONT_PORCH 3 +#define MCDE_SYNCHCONFB_HWREQVEVENT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, HWREQVEVENT, \ + MCDE_SYNCHCONFB_HWREQVEVENT_##__x) +#define MCDE_SYNCHCONFB_HWREQVEVENT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, HWREQVEVENT, __x) +#define MCDE_SYNCHCONFB_HWREQVCNT_SHIFT 2 +#define MCDE_SYNCHCONFB_HWREQVCNT_MASK 0x0000FFFC +#define MCDE_SYNCHCONFB_HWREQVCNT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, HWREQVCNT, __x) +#define MCDE_SYNCHCONFB_SWINTVEVENT_SHIFT 16 +#define MCDE_SYNCHCONFB_SWINTVEVENT_MASK 0x00030000 +#define MCDE_SYNCHCONFB_SWINTVEVENT_VSYNC 0 +#define MCDE_SYNCHCONFB_SWINTVEVENT_BACK_PORCH 1 +#define MCDE_SYNCHCONFB_SWINTVEVENT_ACTIVE_VIDEO 2 +#define MCDE_SYNCHCONFB_SWINTVEVENT_FRONT_PORCH 3 +#define MCDE_SYNCHCONFB_SWINTVEVENT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, SWINTVEVENT, \ + MCDE_SYNCHCONFB_SWINTVEVENT_##__x) +#define MCDE_SYNCHCONFB_SWINTVEVENT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, SWINTVEVENT, __x) +#define MCDE_SYNCHCONFB_SWINTVCNT_SHIFT 18 +#define MCDE_SYNCHCONFB_SWINTVCNT_MASK 0xFFFC0000 +#define MCDE_SYNCHCONFB_SWINTVCNT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, SWINTVCNT, __x) +#define MCDE_GAM0A 0x00000888 +#define MCDE_GAM0A_GROUPOFFSET 0x200 +#define MCDE_GAM0A_BLUE_SHIFT 0 +#define MCDE_GAM0A_BLUE_MASK 0x00FFFFFF +#define MCDE_GAM0A_BLUE(__x) \ + MCDE_VAL2REG(MCDE_GAM0A, BLUE, __x) +#define MCDE_GAM0B 0x00000A88 +#define MCDE_GAM0B_BLUE_SHIFT 0 +#define MCDE_GAM0B_BLUE_MASK 0x00FFFFFF +#define MCDE_GAM0B_BLUE(__x) \ + MCDE_VAL2REG(MCDE_GAM0B, BLUE, __x) +#define MCDE_GAM1A 0x0000088C +#define MCDE_GAM1A_GROUPOFFSET 0x200 +#define MCDE_GAM1A_GREEN_SHIFT 0 +#define MCDE_GAM1A_GREEN_MASK 0x00FFFFFF +#define MCDE_GAM1A_GREEN(__x) \ + MCDE_VAL2REG(MCDE_GAM1A, GREEN, __x) +#define MCDE_GAM1B 0x00000A8C +#define MCDE_GAM1B_GREEN_SHIFT 0 +#define MCDE_GAM1B_GREEN_MASK 0x00FFFFFF +#define MCDE_GAM1B_GREEN(__x) \ + MCDE_VAL2REG(MCDE_GAM1B, GREEN, __x) +#define MCDE_GAM2A 0x00000890 +#define MCDE_GAM2A_GROUPOFFSET 0x200 +#define MCDE_GAM2A_RED_SHIFT 0 +#define MCDE_GAM2A_RED_MASK 0x00FFFFFF +#define MCDE_GAM2A_RED(__x) \ + MCDE_VAL2REG(MCDE_GAM2A, RED, __x) +#define MCDE_GAM2B 0x00000A90 +#define MCDE_GAM2B_RED_SHIFT 0 +#define MCDE_GAM2B_RED_MASK 0x00FFFFFF +#define MCDE_GAM2B_RED(__x) \ + MCDE_VAL2REG(MCDE_GAM2B, RED, __x) +#define MCDE_OLEDCONV1A 0x00000894 +#define MCDE_OLEDCONV1A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV1A_ALPHA_RED_SHIFT 0 +#define MCDE_OLEDCONV1A_ALPHA_RED_MASK 0x00003FFF +#define MCDE_OLEDCONV1A_ALPHA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV1A, ALPHA_RED, __x) +#define MCDE_OLEDCONV1A_ALPHA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV1A_ALPHA_GREEN_MASK 0x3FFF0000 +#define MCDE_OLEDCONV1A_ALPHA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV1A, ALPHA_GREEN, __x) +#define MCDE_OLEDCONV1B 0x00000A94 +#define MCDE_OLEDCONV1B_ALPHA_RED_SHIFT 0 +#define MCDE_OLEDCONV1B_ALPHA_RED_MASK 0x00003FFF +#define MCDE_OLEDCONV1B_ALPHA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV1B, ALPHA_RED, __x) +#define MCDE_OLEDCONV1B_ALPHA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV1B_ALPHA_GREEN_MASK 0x3FFF0000 +#define MCDE_OLEDCONV1B_ALPHA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV1B, ALPHA_GREEN, __x) +#define MCDE_OLEDCONV2A 0x00000898 +#define MCDE_OLEDCONV2A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV2A_ALPHA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV2A_ALPHA_BLUE_MASK 0x00003FFF +#define MCDE_OLEDCONV2A_ALPHA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV2A, ALPHA_BLUE, __x) +#define MCDE_OLEDCONV2A_BETA_RED_SHIFT 16 +#define MCDE_OLEDCONV2A_BETA_RED_MASK 0x3FFF0000 +#define MCDE_OLEDCONV2A_BETA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV2A, BETA_RED, __x) +#define MCDE_OLEDCONV2B 0x00000A98 +#define MCDE_OLEDCONV2B_ALPHA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV2B_ALPHA_BLUE_MASK 0x00003FFF +#define MCDE_OLEDCONV2B_ALPHA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV2B, ALPHA_BLUE, __x) +#define MCDE_OLEDCONV2B_BETA_RED_SHIFT 16 +#define MCDE_OLEDCONV2B_BETA_RED_MASK 0x3FFF0000 +#define MCDE_OLEDCONV2B_BETA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV2B, BETA_RED, __x) +#define MCDE_OLEDCONV3A 0x0000089C +#define MCDE_OLEDCONV3A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV3A_BETA_GREEN_SHIFT 0 +#define MCDE_OLEDCONV3A_BETA_GREEN_MASK 0x00003FFF +#define MCDE_OLEDCONV3A_BETA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV3A, BETA_GREEN, __x) +#define MCDE_OLEDCONV3A_BETA_BLUE_SHIFT 16 +#define MCDE_OLEDCONV3A_BETA_BLUE_MASK 0x3FFF0000 +#define MCDE_OLEDCONV3A_BETA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV3A, BETA_BLUE, __x) +#define MCDE_OLEDCONV3B 0x00000A9C +#define MCDE_OLEDCONV3B_BETA_GREEN_SHIFT 0 +#define MCDE_OLEDCONV3B_BETA_GREEN_MASK 0x00003FFF +#define MCDE_OLEDCONV3B_BETA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV3B, BETA_GREEN, __x) +#define MCDE_OLEDCONV3B_BETA_BLUE_SHIFT 16 +#define MCDE_OLEDCONV3B_BETA_BLUE_MASK 0x3FFF0000 +#define MCDE_OLEDCONV3B_BETA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV3B, BETA_BLUE, __x) +#define MCDE_OLEDCONV4A 0x000008A0 +#define MCDE_OLEDCONV4A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV4A_GAMMA_RED_SHIFT 0 +#define MCDE_OLEDCONV4A_GAMMA_RED_MASK 0x00003FFF +#define MCDE_OLEDCONV4A_GAMMA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV4A, GAMMA_RED, __x) +#define MCDE_OLEDCONV4A_GAMMA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV4A_GAMMA_GREEN_MASK 0x3FFF0000 +#define MCDE_OLEDCONV4A_GAMMA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV4A, GAMMA_GREEN, __x) +#define MCDE_OLEDCONV4B 0x00000AA0 +#define MCDE_OLEDCONV4B_GAMMA_RED_SHIFT 0 +#define MCDE_OLEDCONV4B_GAMMA_RED_MASK 0x00003FFF +#define MCDE_OLEDCONV4B_GAMMA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV4B, GAMMA_RED, __x) +#define MCDE_OLEDCONV4B_GAMMA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV4B_GAMMA_GREEN_MASK 0x3FFF0000 +#define MCDE_OLEDCONV4B_GAMMA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV4B, GAMMA_GREEN, __x) +#define MCDE_OLEDCONV5A 0x000008A4 +#define MCDE_OLEDCONV5A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV5A_GAMMA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV5A_GAMMA_BLUE_MASK 0x00003FFF +#define MCDE_OLEDCONV5A_GAMMA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV5A, GAMMA_BLUE, __x) +#define MCDE_OLEDCONV5A_OFF_RED_SHIFT 16 +#define MCDE_OLEDCONV5A_OFF_RED_MASK 0x3FFF0000 +#define MCDE_OLEDCONV5A_OFF_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV5A, OFF_RED, __x) +#define MCDE_OLEDCONV5B 0x00000AA4 +#define MCDE_OLEDCONV5B_GAMMA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV5B_GAMMA_BLUE_MASK 0x00003FFF +#define MCDE_OLEDCONV5B_GAMMA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV5B, GAMMA_BLUE, __x) +#define MCDE_OLEDCONV5B_OFF_RED_SHIFT 16 +#define MCDE_OLEDCONV5B_OFF_RED_MASK 0x3FFF0000 +#define MCDE_OLEDCONV5B_OFF_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV5B, OFF_RED, __x) +#define MCDE_OLEDCONV6A 0x000008A8 +#define MCDE_OLEDCONV6A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV6A_OFF_GREEN_SHIFT 0 +#define MCDE_OLEDCONV6A_OFF_GREEN_MASK 0x00003FFF +#define MCDE_OLEDCONV6A_OFF_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV6A, OFF_GREEN, __x) +#define MCDE_OLEDCONV6A_OFF_BLUE_SHIFT 16 +#define MCDE_OLEDCONV6A_OFF_BLUE_MASK 0x3FFF0000 +#define MCDE_OLEDCONV6A_OFF_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV6A, OFF_BLUE, __x) +#define MCDE_OLEDCONV6B 0x00000AA8 +#define MCDE_OLEDCONV6B_OFF_GREEN_SHIFT 0 +#define MCDE_OLEDCONV6B_OFF_GREEN_MASK 0x00003FFF +#define MCDE_OLEDCONV6B_OFF_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV6B, OFF_GREEN, __x) +#define MCDE_OLEDCONV6B_OFF_BLUE_SHIFT 16 +#define MCDE_OLEDCONV6B_OFF_BLUE_MASK 0x3FFF0000 +#define MCDE_OLEDCONV6B_OFF_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV6B, OFF_BLUE, __x) +#define MCDE_CRC 0x00000C00 +#define MCDE_CRC_FLOEN_SHIFT 0 +#define MCDE_CRC_FLOEN_MASK 0x00000001 +#define MCDE_CRC_FLOEN(__x) \ + MCDE_VAL2REG(MCDE_CRC, FLOEN, __x) +#define MCDE_CRC_POWEREN_SHIFT 1 +#define MCDE_CRC_POWEREN_MASK 0x00000002 +#define MCDE_CRC_POWEREN(__x) \ + MCDE_VAL2REG(MCDE_CRC, POWEREN, __x) +#define MCDE_CRC_C1EN_SHIFT 2 +#define MCDE_CRC_C1EN_MASK 0x00000004 +#define MCDE_CRC_C1EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, C1EN, __x) +#define MCDE_CRC_C2EN_SHIFT 3 +#define MCDE_CRC_C2EN_MASK 0x00000008 +#define MCDE_CRC_C2EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, C2EN, __x) +#define MCDE_CRC_WMLVL1_SHIFT 4 +#define MCDE_CRC_WMLVL1_MASK 0x00000010 +#define MCDE_CRC_WMLVL1(__x) \ + MCDE_VAL2REG(MCDE_CRC, WMLVL1, __x) +#define MCDE_CRC_WMLVL2_SHIFT 5 +#define MCDE_CRC_WMLVL2_MASK 0x00000020 +#define MCDE_CRC_WMLVL2(__x) \ + MCDE_VAL2REG(MCDE_CRC, WMLVL2, __x) +#define MCDE_CRC_SYNCSEL_SHIFT 6 +#define MCDE_CRC_SYNCSEL_MASK 0x00000040 +#define MCDE_CRC_SYNCSEL(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYNCSEL, __x) +#define MCDE_CRC_SYCEN0_SHIFT 7 +#define MCDE_CRC_SYCEN0_MASK 0x00000080 +#define MCDE_CRC_SYCEN0(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYCEN0, __x) +#define MCDE_CRC_SYCEN1_SHIFT 8 +#define MCDE_CRC_SYCEN1_MASK 0x00000100 +#define MCDE_CRC_SYCEN1(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYCEN1, __x) +#define MCDE_CRC_SIZE1_SHIFT 9 +#define MCDE_CRC_SIZE1_MASK 0x00000200 +#define MCDE_CRC_SIZE1(__x) \ + MCDE_VAL2REG(MCDE_CRC, SIZE1, __x) +#define MCDE_CRC_SIZE2_SHIFT 10 +#define MCDE_CRC_SIZE2_MASK 0x00000400 +#define MCDE_CRC_SIZE2(__x) \ + MCDE_VAL2REG(MCDE_CRC, SIZE2, __x) +#define MCDE_CRC_INBAND1_SHIFT 11 +#define MCDE_CRC_INBAND1_MASK 0x00000800 +#define MCDE_CRC_INBAND1(__x) \ + MCDE_VAL2REG(MCDE_CRC, INBAND1, __x) +#define MCDE_CRC_INBAND2_SHIFT 12 +#define MCDE_CRC_INBAND2_MASK 0x00001000 +#define MCDE_CRC_INBAND2(__x) \ + MCDE_VAL2REG(MCDE_CRC, INBAND2, __x) +#define MCDE_CRC_CLKSEL_SHIFT 13 +#define MCDE_CRC_CLKSEL_MASK 0x00006000 +#define MCDE_CRC_CLKSEL_166MHz 0 +#define MCDE_CRC_CLKSEL_48MHz 1 +#define MCDE_CRC_CLKSEL_LCD 2 +#define MCDE_CRC_CLKSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRC, CLKSEL, MCDE_CRC_CLKSEL_##__x) +#define MCDE_CRC_CLKSEL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CLKSEL, __x) +#define MCDE_CRC_YUVCONVC1EN_SHIFT 15 +#define MCDE_CRC_YUVCONVC1EN_MASK 0x00008000 +#define MCDE_CRC_YUVCONVC1EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, YUVCONVC1EN, __x) +#define MCDE_CRC_CS1EN_SHIFT 16 +#define MCDE_CRC_CS1EN_MASK 0x00010000 +#define MCDE_CRC_CS1EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, CS1EN, __x) +#define MCDE_CRC_CS2EN_SHIFT 17 +#define MCDE_CRC_CS2EN_MASK 0x00020000 +#define MCDE_CRC_CS2EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, CS2EN, __x) +#define MCDE_CRC_RESEN_SHIFT 18 +#define MCDE_CRC_RESEN_MASK 0x00040000 +#define MCDE_CRC_RESEN(__x) \ + MCDE_VAL2REG(MCDE_CRC, RESEN, __x) +#define MCDE_CRC_CS1POL_SHIFT 19 +#define MCDE_CRC_CS1POL_MASK 0x00080000 +#define MCDE_CRC_CS1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CS1POL, __x) +#define MCDE_CRC_CS2POL_SHIFT 20 +#define MCDE_CRC_CS2POL_MASK 0x00100000 +#define MCDE_CRC_CS2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CS2POL, __x) +#define MCDE_CRC_CD1POL_SHIFT 21 +#define MCDE_CRC_CD1POL_MASK 0x00200000 +#define MCDE_CRC_CD1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CD1POL, __x) +#define MCDE_CRC_CD2POL_SHIFT 22 +#define MCDE_CRC_CD2POL_MASK 0x00400000 +#define MCDE_CRC_CD2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CD2POL, __x) +#define MCDE_CRC_WR1POL_SHIFT 23 +#define MCDE_CRC_WR1POL_MASK 0x00800000 +#define MCDE_CRC_WR1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, WR1POL, __x) +#define MCDE_CRC_WR2POL_SHIFT 24 +#define MCDE_CRC_WR2POL_MASK 0x01000000 +#define MCDE_CRC_WR2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, WR2POL, __x) +#define MCDE_CRC_RD1POL_SHIFT 25 +#define MCDE_CRC_RD1POL_MASK 0x02000000 +#define MCDE_CRC_RD1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, RD1POL, __x) +#define MCDE_CRC_RD2POL_SHIFT 26 +#define MCDE_CRC_RD2POL_MASK 0x04000000 +#define MCDE_CRC_RD2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, RD2POL, __x) +#define MCDE_CRC_RES1POL_SHIFT 27 +#define MCDE_CRC_RES1POL_MASK 0x08000000 +#define MCDE_CRC_RES1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, RES1POL, __x) +#define MCDE_CRC_RES2POL_SHIFT 28 +#define MCDE_CRC_RES2POL_MASK 0x10000000 +#define MCDE_CRC_RES2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, RES2POL, __x) +#define MCDE_CRC_SYNCCTRL_SHIFT 29 +#define MCDE_CRC_SYNCCTRL_MASK 0x60000000 +#define MCDE_CRC_SYNCCTRL_OFF 0 +#define MCDE_CRC_SYNCCTRL_C0 1 +#define MCDE_CRC_SYNCCTRL_C1 2 +#define MCDE_CRC_SYNCCTRL_PING_PONG 3 +#define MCDE_CRC_SYNCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYNCCTRL, MCDE_CRC_SYNCCTRL_##__x) +#define MCDE_CRC_SYNCCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYNCCTRL, __x) +#define MCDE_CRC_CLAMPC1EN_SHIFT 31 +#define MCDE_CRC_CLAMPC1EN_MASK 0x80000000 +#define MCDE_CRC_CLAMPC1EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, CLAMPC1EN, __x) +#define MCDE_PBCCRC0 0x00000C04 +#define MCDE_PBCCRC0_GROUPOFFSET 0x4 +#define MCDE_PBCCRC0_BSCM_SHIFT 0 +#define MCDE_PBCCRC0_BSCM_MASK 0x00000007 +#define MCDE_PBCCRC0_BSCM_1_8BIT 0 +#define MCDE_PBCCRC0_BSCM_2_8BIT 1 +#define MCDE_PBCCRC0_BSCM_3_8BIT 2 +#define MCDE_PBCCRC0_BSCM_1_16BIT 3 +#define MCDE_PBCCRC0_BSCM_2_16BIT 4 +#define MCDE_PBCCRC0_BSCM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BSCM, MCDE_PBCCRC0_BSCM_##__x) +#define MCDE_PBCCRC0_BSCM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BSCM, __x) +#define MCDE_PBCCRC0_BSDM_SHIFT 3 +#define MCDE_PBCCRC0_BSDM_MASK 0x00000038 +#define MCDE_PBCCRC0_BSDM_1_8BIT 0 +#define MCDE_PBCCRC0_BSDM_2_8BIT 1 +#define MCDE_PBCCRC0_BSDM_3_8BIT 2 +#define MCDE_PBCCRC0_BSDM_1_16BIT 3 +#define MCDE_PBCCRC0_BSDM_2_16BIT 4 +#define MCDE_PBCCRC0_BSDM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BSDM, MCDE_PBCCRC0_BSDM_##__x) +#define MCDE_PBCCRC0_BSDM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BSDM, __x) +#define MCDE_PBCCRC0_PDM_SHIFT 6 +#define MCDE_PBCCRC0_PDM_MASK 0x000000C0 +#define MCDE_PBCCRC0_PDM_NORMAL 0 +#define MCDE_PBCCRC0_PDM_16_TO_32 1 +#define MCDE_PBCCRC0_PDM_24_TO_32_RIGHT 2 +#define MCDE_PBCCRC0_PDM_24_TO_32_LEFT 3 +#define MCDE_PBCCRC0_PDM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, PDM, MCDE_PBCCRC0_PDM_##__x) +#define MCDE_PBCCRC0_PDM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, PDM, __x) +#define MCDE_PBCCRC0_PDCTRL_SHIFT 12 +#define MCDE_PBCCRC0_PDCTRL_MASK 0x00001000 +#define MCDE_PBCCRC0_PDCTRL(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, PDCTRL, __x) +#define MCDE_PBCCRC0_BPP_SHIFT 13 +#define MCDE_PBCCRC0_BPP_MASK 0x0000E000 +#define MCDE_PBCCRC0_BPP_8BPP 0 +#define MCDE_PBCCRC0_BPP_12BPP 1 +#define MCDE_PBCCRC0_BPP_15BPP 2 +#define MCDE_PBCCRC0_BPP_16BPP 3 +#define MCDE_PBCCRC0_BPP_18BPP 4 +#define MCDE_PBCCRC0_BPP_24BPP 5 +#define MCDE_PBCCRC0_BPP(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BPP, __x) +#define MCDE_PBCCRC1 0x00000C08 +#define MCDE_PBCCRC1_BSCM_SHIFT 0 +#define MCDE_PBCCRC1_BSCM_MASK 0x00000007 +#define MCDE_PBCCRC1_BSCM_1_8BIT 0 +#define MCDE_PBCCRC1_BSCM_2_8BIT 1 +#define MCDE_PBCCRC1_BSCM_3_8BIT 2 +#define MCDE_PBCCRC1_BSCM_1_16BIT 3 +#define MCDE_PBCCRC1_BSCM_2_16BIT 4 +#define MCDE_PBCCRC1_BSCM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BSCM, MCDE_PBCCRC1_BSCM_##__x) +#define MCDE_PBCCRC1_BSCM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BSCM, __x) +#define MCDE_PBCCRC1_BSDM_SHIFT 3 +#define MCDE_PBCCRC1_BSDM_MASK 0x00000038 +#define MCDE_PBCCRC1_BSDM_1_8BIT 0 +#define MCDE_PBCCRC1_BSDM_2_8BIT 1 +#define MCDE_PBCCRC1_BSDM_3_8BIT 2 +#define MCDE_PBCCRC1_BSDM_1_16BIT 3 +#define MCDE_PBCCRC1_BSDM_2_16BIT 4 +#define MCDE_PBCCRC1_BSDM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BSDM, MCDE_PBCCRC1_BSDM_##__x) +#define MCDE_PBCCRC1_BSDM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BSDM, __x) +#define MCDE_PBCCRC1_PDM_SHIFT 6 +#define MCDE_PBCCRC1_PDM_MASK 0x000000C0 +#define MCDE_PBCCRC1_PDM_NORMAL 0 +#define MCDE_PBCCRC1_PDM_16_TO_32 1 +#define MCDE_PBCCRC1_PDM_24_TO_32_RIGHT 2 +#define MCDE_PBCCRC1_PDM_24_TO_32_LEFT 3 +#define MCDE_PBCCRC1_PDM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, PDM, MCDE_PBCCRC1_PDM_##__x) +#define MCDE_PBCCRC1_PDM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, PDM, __x) +#define MCDE_PBCCRC1_PDCTRL_SHIFT 12 +#define MCDE_PBCCRC1_PDCTRL_MASK 0x00001000 +#define MCDE_PBCCRC1_PDCTRL(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, PDCTRL, __x) +#define MCDE_PBCCRC1_BPP_SHIFT 13 +#define MCDE_PBCCRC1_BPP_MASK 0x0000E000 +#define MCDE_PBCCRC1_BPP_8BPP 0 +#define MCDE_PBCCRC1_BPP_12BPP 1 +#define MCDE_PBCCRC1_BPP_15BPP 2 +#define MCDE_PBCCRC1_BPP_16BPP 3 +#define MCDE_PBCCRC1_BPP_18BPP 4 +#define MCDE_PBCCRC1_BPP_24BPP 5 +#define MCDE_PBCCRC1_BPP(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BPP, __x) +#define MCDE_PBCBMRC00 0x00000C0C +#define MCDE_PBCBMRC00_GROUPOFFSET 0x4 +#define MCDE_PBCBMRC00_MUXI_SHIFT 0 +#define MCDE_PBCBMRC00_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC00_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC00, MUXI, __x) +#define MCDE_PBCBMRC01 0x00000C10 +#define MCDE_PBCBMRC01_MUXI_SHIFT 0 +#define MCDE_PBCBMRC01_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC01_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC01, MUXI, __x) +#define MCDE_PBCBMRC02 0x00000C14 +#define MCDE_PBCBMRC02_MUXI_SHIFT 0 +#define MCDE_PBCBMRC02_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC02_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC02, MUXI, __x) +#define MCDE_PBCBMRC03 0x00000C18 +#define MCDE_PBCBMRC03_MUXI_SHIFT 0 +#define MCDE_PBCBMRC03_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC03_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC03, MUXI, __x) +#define MCDE_PBCBMRC04 0x00000C1C +#define MCDE_PBCBMRC04_MUXI_SHIFT 0 +#define MCDE_PBCBMRC04_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC04_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC04, MUXI, __x) +#define MCDE_PBCBMRC10 0x00000C20 +#define MCDE_PBCBMRC10_MUXI_SHIFT 0 +#define MCDE_PBCBMRC10_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC10_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC10, MUXI, __x) +#define MCDE_PBCBMRC11 0x00000C24 +#define MCDE_PBCBMRC11_MUXI_SHIFT 0 +#define MCDE_PBCBMRC11_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC11_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC11, MUXI, __x) +#define MCDE_PBCBMRC12 0x00000C28 +#define MCDE_PBCBMRC12_MUXI_SHIFT 0 +#define MCDE_PBCBMRC12_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC12_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC12, MUXI, __x) +#define MCDE_PBCBMRC13 0x00000C2C +#define MCDE_PBCBMRC13_MUXI_SHIFT 0 +#define MCDE_PBCBMRC13_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC13_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC13, MUXI, __x) +#define MCDE_PBCBMRC14 0x00000C30 +#define MCDE_PBCBMRC14_MUXI_SHIFT 0 +#define MCDE_PBCBMRC14_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC14_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC14, MUXI, __x) +#define MCDE_PBCBCRC00 0x00000C34 +#define MCDE_PBCBCRC00_GROUPOFFSET 0x4 +#define MCDE_PBCBCRC00_CTLI_SHIFT 0 +#define MCDE_PBCBCRC00_CTLI_MASK 0xFFFFFFFF +#define MCDE_PBCBCRC00_CTLI(__x) \ + MCDE_VAL2REG(MCDE_PBCBCRC00, CTLI, __x) +#define MCDE_PBCBCRC10 0x00000C38 +#define MCDE_PBCBCRC10_CTLI_SHIFT 0 +#define MCDE_PBCBCRC10_CTLI_MASK 0xFFFFFFFF +#define MCDE_PBCBCRC10_CTLI(__x) \ + MCDE_VAL2REG(MCDE_PBCBCRC10, CTLI, __x) +#define MCDE_PBCBCRC01 0x00000C48 +#define MCDE_PBCBCRC01_GROUPOFFSET 0x4 +#define MCDE_PBCBCRC01_CTLI_SHIFT 0 +#define MCDE_PBCBCRC01_CTLI_MASK 0xFFFFFFFF +#define MCDE_PBCBCRC01_CTLI(__x) \ + MCDE_VAL2REG(MCDE_PBCBCRC01, CTLI, __x) +#define MCDE_PBCBCRC11 0x00000C4C +#define MCDE_PBCBCRC11_CTLI_SHIFT 0 +#define MCDE_PBCBCRC11_CTLI_MASK 0xFFFFFFFF +#define MCDE_PBCBCRC11_CTLI(__x) \ + MCDE_VAL2REG(MCDE_PBCBCRC11, CTLI, __x) +#define MCDE_VSCRC0 0x00000C5C +#define MCDE_VSCRC0_GROUPOFFSET 0x4 +#define MCDE_VSCRC0_VSPMIN_SHIFT 0 +#define MCDE_VSCRC0_VSPMIN_MASK 0x00000FFF +#define MCDE_VSCRC0_VSPMIN(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPMIN, __x) +#define MCDE_VSCRC0_VSPMAX_SHIFT 12 +#define MCDE_VSCRC0_VSPMAX_MASK 0x00FFF000 +#define MCDE_VSCRC0_VSPMAX(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPMAX, __x) +#define MCDE_VSCRC0_VSPDIV_SHIFT 24 +#define MCDE_VSCRC0_VSPDIV_MASK 0x07000000 +#define MCDE_VSCRC0_VSPDIV(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPDIV, __x) +#define MCDE_VSCRC0_VSPOL_SHIFT 27 +#define MCDE_VSCRC0_VSPOL_MASK 0x08000000 +#define MCDE_VSCRC0_VSPOL_ACTIVE_HIGH 0 +#define MCDE_VSCRC0_VSPOL_ACTIVE_LOW 1 +#define MCDE_VSCRC0_VSPOL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPOL, MCDE_VSCRC0_VSPOL_##__x) +#define MCDE_VSCRC0_VSPOL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPOL, __x) +#define MCDE_VSCRC0_VSSEL_SHIFT 28 +#define MCDE_VSCRC0_VSSEL_MASK 0x10000000 +#define MCDE_VSCRC0_VSSEL_VSYNC 0 +#define MCDE_VSCRC0_VSSEL_HSYNC 1 +#define MCDE_VSCRC0_VSSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSSEL, MCDE_VSCRC0_VSSEL_##__x) +#define MCDE_VSCRC0_VSSEL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSSEL, __x) +#define MCDE_VSCRC0_VSDBL_SHIFT 29 +#define MCDE_VSCRC0_VSDBL_MASK 0xE0000000 +#define MCDE_VSCRC0_VSDBL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSDBL, __x) +#define MCDE_VSCRC1 0x00000C60 +#define MCDE_VSCRC1_VSPMIN_SHIFT 0 +#define MCDE_VSCRC1_VSPMIN_MASK 0x00000FFF +#define MCDE_VSCRC1_VSPMIN(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPMIN, __x) +#define MCDE_VSCRC1_VSPMAX_SHIFT 12 +#define MCDE_VSCRC1_VSPMAX_MASK 0x00FFF000 +#define MCDE_VSCRC1_VSPMAX(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPMAX, __x) +#define MCDE_VSCRC1_VSPDIV_SHIFT 24 +#define MCDE_VSCRC1_VSPDIV_MASK 0x07000000 +#define MCDE_VSCRC1_VSPDIV(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPDIV, __x) +#define MCDE_VSCRC1_VSPOL_SHIFT 27 +#define MCDE_VSCRC1_VSPOL_MASK 0x08000000 +#define MCDE_VSCRC1_VSPOL_ACTIVE_HIGH 0 +#define MCDE_VSCRC1_VSPOL_ACTIVE_LOW 1 +#define MCDE_VSCRC1_VSPOL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPOL, MCDE_VSCRC1_VSPOL_##__x) +#define MCDE_VSCRC1_VSPOL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPOL, __x) +#define MCDE_VSCRC1_VSSEL_SHIFT 28 +#define MCDE_VSCRC1_VSSEL_MASK 0x10000000 +#define MCDE_VSCRC1_VSSEL_VSYNC 0 +#define MCDE_VSCRC1_VSSEL_HSYNC 1 +#define MCDE_VSCRC1_VSSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSSEL, MCDE_VSCRC1_VSSEL_##__x) +#define MCDE_VSCRC1_VSSEL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSSEL, __x) +#define MCDE_VSCRC1_VSDBL_SHIFT 29 +#define MCDE_VSCRC1_VSDBL_MASK 0xE0000000 +#define MCDE_VSCRC1_VSDBL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSDBL, __x) +#define MCDE_SCTRC 0x00000C64 +#define MCDE_SCTRC_SYNCDELC0_SHIFT 0 +#define MCDE_SCTRC_SYNCDELC0_MASK 0x000000FF +#define MCDE_SCTRC_SYNCDELC0(__x) \ + MCDE_VAL2REG(MCDE_SCTRC, SYNCDELC0, __x) +#define MCDE_SCTRC_SYNCDELC1_SHIFT 8 +#define MCDE_SCTRC_SYNCDELC1_MASK 0x0000FF00 +#define MCDE_SCTRC_SYNCDELC1(__x) \ + MCDE_VAL2REG(MCDE_SCTRC, SYNCDELC1, __x) +#define MCDE_SCTRC_TRDELC_SHIFT 16 +#define MCDE_SCTRC_TRDELC_MASK 0x0FFF0000 +#define MCDE_SCTRC_TRDELC(__x) \ + MCDE_VAL2REG(MCDE_SCTRC, TRDELC, __x) +#define MCDE_SCSRC 0x00000C68 +#define MCDE_SCSRC_VSTAC0_SHIFT 0 +#define MCDE_SCSRC_VSTAC0_MASK 0x00000001 +#define MCDE_SCSRC_VSTAC0(__x) \ + MCDE_VAL2REG(MCDE_SCSRC, VSTAC0, __x) +#define MCDE_SCSRC_VSTAC1_SHIFT 1 +#define MCDE_SCSRC_VSTAC1_MASK 0x00000002 +#define MCDE_SCSRC_VSTAC1(__x) \ + MCDE_VAL2REG(MCDE_SCSRC, VSTAC1, __x) +#define MCDE_BCNR0 0x00000C6C +#define MCDE_BCNR0_GROUPOFFSET 0x4 +#define MCDE_BCNR0_BCN_SHIFT 0 +#define MCDE_BCNR0_BCN_MASK 0x000000FF +#define MCDE_BCNR0_BCN(__x) \ + MCDE_VAL2REG(MCDE_BCNR0, BCN, __x) +#define MCDE_BCNR1 0x00000C70 +#define MCDE_BCNR1_BCN_SHIFT 0 +#define MCDE_BCNR1_BCN_MASK 0x000000FF +#define MCDE_BCNR1_BCN(__x) \ + MCDE_VAL2REG(MCDE_BCNR1, BCN, __x) +#define MCDE_CSCDTR0 0x00000C74 +#define MCDE_CSCDTR0_GROUPOFFSET 0x4 +#define MCDE_CSCDTR0_CSCDACT_SHIFT 0 +#define MCDE_CSCDTR0_CSCDACT_MASK 0x000000FF +#define MCDE_CSCDTR0_CSCDACT(__x) \ + MCDE_VAL2REG(MCDE_CSCDTR0, CSCDACT, __x) +#define MCDE_CSCDTR0_CSCDDEACT_SHIFT 8 +#define MCDE_CSCDTR0_CSCDDEACT_MASK 0x0000FF00 +#define MCDE_CSCDTR0_CSCDDEACT(__x) \ + MCDE_VAL2REG(MCDE_CSCDTR0, CSCDDEACT, __x) +#define MCDE_CSCDTR1 0x00000C78 +#define MCDE_CSCDTR1_CSCDACT_SHIFT 0 +#define MCDE_CSCDTR1_CSCDACT_MASK 0x000000FF +#define MCDE_CSCDTR1_CSCDACT(__x) \ + MCDE_VAL2REG(MCDE_CSCDTR1, CSCDACT, __x) +#define MCDE_CSCDTR1_CSCDDEACT_SHIFT 8 +#define MCDE_CSCDTR1_CSCDDEACT_MASK 0x0000FF00 +#define MCDE_CSCDTR1_CSCDDEACT(__x) \ + MCDE_VAL2REG(MCDE_CSCDTR1, CSCDDEACT, __x) +#define MCDE_RDWRTR0 0x00000C7C +#define MCDE_RDWRTR0_GROUPOFFSET 0x4 +#define MCDE_RDWRTR0_RWACT_SHIFT 0 +#define MCDE_RDWRTR0_RWACT_MASK 0x000000FF +#define MCDE_RDWRTR0_RWACT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR0, RWACT, __x) +#define MCDE_RDWRTR0_RWDEACT_SHIFT 8 +#define MCDE_RDWRTR0_RWDEACT_MASK 0x0000FF00 +#define MCDE_RDWRTR0_RWDEACT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR0, RWDEACT, __x) +#define MCDE_RDWRTR0_MOTINT_SHIFT 16 +#define MCDE_RDWRTR0_MOTINT_MASK 0x00010000 +#define MCDE_RDWRTR0_MOTINT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR0, MOTINT, __x) +#define MCDE_RDWRTR1 0x00000C80 +#define MCDE_RDWRTR1_RWACT_SHIFT 0 +#define MCDE_RDWRTR1_RWACT_MASK 0x000000FF +#define MCDE_RDWRTR1_RWACT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR1, RWACT, __x) +#define MCDE_RDWRTR1_RWDEACT_SHIFT 8 +#define MCDE_RDWRTR1_RWDEACT_MASK 0x0000FF00 +#define MCDE_RDWRTR1_RWDEACT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR1, RWDEACT, __x) +#define MCDE_RDWRTR1_MOTINT_SHIFT 16 +#define MCDE_RDWRTR1_MOTINT_MASK 0x00010000 +#define MCDE_RDWRTR1_MOTINT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR1, MOTINT, __x) +#define MCDE_DOTR0 0x00000C84 +#define MCDE_DOTR0_GROUPOFFSET 0x4 +#define MCDE_DOTR0_DOACT_SHIFT 0 +#define MCDE_DOTR0_DOACT_MASK 0x000000FF +#define MCDE_DOTR0_DOACT(__x) \ + MCDE_VAL2REG(MCDE_DOTR0, DOACT, __x) +#define MCDE_DOTR0_DODEACT_SHIFT 8 +#define MCDE_DOTR0_DODEACT_MASK 0x0000FF00 +#define MCDE_DOTR0_DODEACT(__x) \ + MCDE_VAL2REG(MCDE_DOTR0, DODEACT, __x) +#define MCDE_DOTR1 0x00000C88 +#define MCDE_DOTR1_DOACT_SHIFT 0 +#define MCDE_DOTR1_DOACT_MASK 0x000000FF +#define MCDE_DOTR1_DOACT(__x) \ + MCDE_VAL2REG(MCDE_DOTR1, DOACT, __x) +#define MCDE_DOTR1_DODEACT_SHIFT 8 +#define MCDE_DOTR1_DODEACT_MASK 0x0000FF00 +#define MCDE_DOTR1_DODEACT(__x) \ + MCDE_VAL2REG(MCDE_DOTR1, DODEACT, __x) +#define MCDE_WCMDC0 0x00000C8C +#define MCDE_WCMDC0_GROUPOFFSET 0x4 +#define MCDE_WCMDC0_COMMANDVALUE_SHIFT 0 +#define MCDE_WCMDC0_COMMANDVALUE_MASK 0x00FFFFFF +#define MCDE_WCMDC0_COMMANDVALUE(__x) \ + MCDE_VAL2REG(MCDE_WCMDC0, COMMANDVALUE, __x) +#define MCDE_WCMDC1 0x00000C90 +#define MCDE_WCMDC1_COMMANDVALUE_SHIFT 0 +#define MCDE_WCMDC1_COMMANDVALUE_MASK 0x00FFFFFF +#define MCDE_WCMDC1_COMMANDVALUE(__x) \ + MCDE_VAL2REG(MCDE_WCMDC1, COMMANDVALUE, __x) +#define MCDE_WDATADC0 0x00000C94 +#define MCDE_WDATADC0_GROUPOFFSET 0x4 +#define MCDE_WDATADC0_DATAVALUE_SHIFT 0 +#define MCDE_WDATADC0_DATAVALUE_MASK 0x00FFFFFF +#define MCDE_WDATADC0_DATAVALUE(__x) \ + MCDE_VAL2REG(MCDE_WDATADC0, DATAVALUE, __x) +#define MCDE_WDATADC1 0x00000C98 +#define MCDE_WDATADC1_DATAVALUE_SHIFT 0 +#define MCDE_WDATADC1_DATAVALUE_MASK 0x00FFFFFF +#define MCDE_WDATADC1_DATAVALUE(__x) \ + MCDE_VAL2REG(MCDE_WDATADC1, DATAVALUE, __x) +#define MCDE_RDATADC0 0x00000C9C +#define MCDE_RDATADC0_GROUPOFFSET 0x4 +#define MCDE_RDATADC0_DATAREADFROMDISPLAYMODULE_SHIFT 0 +#define MCDE_RDATADC0_DATAREADFROMDISPLAYMODULE_MASK 0x0000FFFF +#define MCDE_RDATADC0_DATAREADFROMDISPLAYMODULE(__x) \ + MCDE_VAL2REG(MCDE_RDATADC0, DATAREADFROMDISPLAYMODULE, __x) +#define MCDE_RDATADC0_STARTREAD_SHIFT 16 +#define MCDE_RDATADC0_STARTREAD_MASK 0x00010000 +#define MCDE_RDATADC0_STARTREAD(__x) \ + MCDE_VAL2REG(MCDE_RDATADC0, STARTREAD, __x) +#define MCDE_RDATADC1 0x00000CA0 +#define MCDE_RDATADC1_DATAREADFROMDISPLAYMODULE_SHIFT 0 +#define MCDE_RDATADC1_DATAREADFROMDISPLAYMODULE_MASK 0x0000FFFF +#define MCDE_RDATADC1_DATAREADFROMDISPLAYMODULE(__x) \ + MCDE_VAL2REG(MCDE_RDATADC1, DATAREADFROMDISPLAYMODULE, __x) +#define MCDE_RDATADC1_STARTREAD_SHIFT 16 +#define MCDE_RDATADC1_STARTREAD_MASK 0x00010000 +#define MCDE_RDATADC1_STARTREAD(__x) \ + MCDE_VAL2REG(MCDE_RDATADC1, STARTREAD, __x) +#define MCDE_STATC 0x00000CA4 +#define MCDE_STATC_STATBUSY0_SHIFT 0 +#define MCDE_STATC_STATBUSY0_MASK 0x00000001 +#define MCDE_STATC_STATBUSY0(__x) \ + MCDE_VAL2REG(MCDE_STATC, STATBUSY0, __x) +#define MCDE_STATC_FIFOEMPTY0_SHIFT 1 +#define MCDE_STATC_FIFOEMPTY0_MASK 0x00000002 +#define MCDE_STATC_FIFOEMPTY0(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOEMPTY0, __x) +#define MCDE_STATC_FIFOFULL0_SHIFT 2 +#define MCDE_STATC_FIFOFULL0_MASK 0x00000004 +#define MCDE_STATC_FIFOFULL0(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOFULL0, __x) +#define MCDE_STATC_FIFOCMDEMPTY0_SHIFT 3 +#define MCDE_STATC_FIFOCMDEMPTY0_MASK 0x00000008 +#define MCDE_STATC_FIFOCMDEMPTY0(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOCMDEMPTY0, __x) +#define MCDE_STATC_FIFOCMDFULL0_SHIFT 4 +#define MCDE_STATC_FIFOCMDFULL0_MASK 0x00000010 +#define MCDE_STATC_FIFOCMDFULL0(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOCMDFULL0, __x) +#define MCDE_STATC_STATBUSY1_SHIFT 5 +#define MCDE_STATC_STATBUSY1_MASK 0x00000020 +#define MCDE_STATC_STATBUSY1(__x) \ + MCDE_VAL2REG(MCDE_STATC, STATBUSY1, __x) +#define MCDE_STATC_FIFOEMPTY1_SHIFT 6 +#define MCDE_STATC_FIFOEMPTY1_MASK 0x00000040 +#define MCDE_STATC_FIFOEMPTY1(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOEMPTY1, __x) +#define MCDE_STATC_FIFOFULL1_SHIFT 7 +#define MCDE_STATC_FIFOFULL1_MASK 0x00000080 +#define MCDE_STATC_FIFOFULL1(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOFULL1, __x) +#define MCDE_STATC_FIFOCMDEMPTY1_SHIFT 8 +#define MCDE_STATC_FIFOCMDEMPTY1_MASK 0x00000100 +#define MCDE_STATC_FIFOCMDEMPTY1(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOCMDEMPTY1, __x) +#define MCDE_STATC_FIFOCMDFULL1_SHIFT 9 +#define MCDE_STATC_FIFOCMDFULL1_MASK 0x00000200 +#define MCDE_STATC_FIFOCMDFULL1(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOCMDFULL1, __x) +#define MCDE_CTRLC0 0x00000CA8 +#define MCDE_CTRLC0_GROUPOFFSET 0x4 +#define MCDE_CTRLC0_FIFOWTRMRK_SHIFT 0 +#define MCDE_CTRLC0_FIFOWTRMRK_MASK 0x000000FF +#define MCDE_CTRLC0_FIFOWTRMRK(__x) \ + MCDE_VAL2REG(MCDE_CTRLC0, FIFOWTRMRK, __x) +#define MCDE_CTRLC1 0x00000CAC +#define MCDE_CTRLC1_FIFOWTRMRK_SHIFT 0 +#define MCDE_CTRLC1_FIFOWTRMRK_MASK 0x000000FF +#define MCDE_CTRLC1_FIFOWTRMRK(__x) \ + MCDE_VAL2REG(MCDE_CTRLC1, FIFOWTRMRK, __x) +#define MCDE_DSIVID0CONF0 0x00000E00 +#define MCDE_DSIVID0CONF0_GROUPOFFSET 0x20 +#define MCDE_DSIVID0CONF0_BLANKING_SHIFT 0 +#define MCDE_DSIVID0CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSIVID0CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, BLANKING, __x) +#define MCDE_DSIVID0CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSIVID0CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSIVID0CONF0_VID_MODE_CMD 0 +#define MCDE_DSIVID0CONF0_VID_MODE_VID 1 +#define MCDE_DSIVID0CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, VID_MODE, \ + MCDE_DSIVID0CONF0_VID_MODE_##__x) +#define MCDE_DSIVID0CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, VID_MODE, __x) +#define MCDE_DSIVID0CONF0_CMD8_SHIFT 13 +#define MCDE_DSIVID0CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSIVID0CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, CMD8, __x) +#define MCDE_DSIVID0CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSIVID0CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSIVID0CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, BIT_SWAP, __x) +#define MCDE_DSIVID0CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSIVID0CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSIVID0CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, BYTE_SWAP, __x) +#define MCDE_DSIVID0CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSIVID0CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSIVID0CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSIVID0CONF0_PACKING_SHIFT 20 +#define MCDE_DSIVID0CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSIVID0CONF0_PACKING_RGB565 0 +#define MCDE_DSIVID0CONF0_PACKING_RGB666 1 +#define MCDE_DSIVID0CONF0_PACKING_RGB888 2 +#define MCDE_DSIVID0CONF0_PACKING_BGR888 3 +#define MCDE_DSIVID0CONF0_PACKING_HDTV 7 +#define MCDE_DSIVID0CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, PACKING, \ + MCDE_DSIVID0CONF0_PACKING_##__x) +#define MCDE_DSIVID0CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, PACKING, __x) +#define MCDE_DSICMD0CONF0 0x00000E20 +#define MCDE_DSICMD0CONF0_BLANKING_SHIFT 0 +#define MCDE_DSICMD0CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSICMD0CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, BLANKING, __x) +#define MCDE_DSICMD0CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSICMD0CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSICMD0CONF0_VID_MODE_CMD 0 +#define MCDE_DSICMD0CONF0_VID_MODE_VID 1 +#define MCDE_DSICMD0CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, VID_MODE, \ + MCDE_DSICMD0CONF0_VID_MODE_##__x) +#define MCDE_DSICMD0CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, VID_MODE, __x) +#define MCDE_DSICMD0CONF0_CMD8_SHIFT 13 +#define MCDE_DSICMD0CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSICMD0CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, CMD8, __x) +#define MCDE_DSICMD0CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSICMD0CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSICMD0CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, BIT_SWAP, __x) +#define MCDE_DSICMD0CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSICMD0CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSICMD0CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, BYTE_SWAP, __x) +#define MCDE_DSICMD0CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSICMD0CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSICMD0CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSICMD0CONF0_PACKING_SHIFT 20 +#define MCDE_DSICMD0CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSICMD0CONF0_PACKING_RGB565 0 +#define MCDE_DSICMD0CONF0_PACKING_RGB666 1 +#define MCDE_DSICMD0CONF0_PACKING_RGB888 2 +#define MCDE_DSICMD0CONF0_PACKING_BGR888 3 +#define MCDE_DSICMD0CONF0_PACKING_HDTV 7 +#define MCDE_DSICMD0CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, PACKING, \ + MCDE_DSICMD0CONF0_PACKING_##__x) +#define MCDE_DSICMD0CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, PACKING, __x) +#define MCDE_DSIVID1CONF0 0x00000E40 +#define MCDE_DSIVID1CONF0_BLANKING_SHIFT 0 +#define MCDE_DSIVID1CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSIVID1CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, BLANKING, __x) +#define MCDE_DSIVID1CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSIVID1CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSIVID1CONF0_VID_MODE_CMD 0 +#define MCDE_DSIVID1CONF0_VID_MODE_VID 1 +#define MCDE_DSIVID1CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, VID_MODE, \ + MCDE_DSIVID1CONF0_VID_MODE_##__x) +#define MCDE_DSIVID1CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, VID_MODE, __x) +#define MCDE_DSIVID1CONF0_CMD8_SHIFT 13 +#define MCDE_DSIVID1CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSIVID1CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, CMD8, __x) +#define MCDE_DSIVID1CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSIVID1CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSIVID1CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, BIT_SWAP, __x) +#define MCDE_DSIVID1CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSIVID1CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSIVID1CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, BYTE_SWAP, __x) +#define MCDE_DSIVID1CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSIVID1CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSIVID1CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSIVID1CONF0_PACKING_SHIFT 20 +#define MCDE_DSIVID1CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSIVID1CONF0_PACKING_RGB565 0 +#define MCDE_DSIVID1CONF0_PACKING_RGB666 1 +#define MCDE_DSIVID1CONF0_PACKING_RGB888 2 +#define MCDE_DSIVID1CONF0_PACKING_BGR888 3 +#define MCDE_DSIVID1CONF0_PACKING_HDTV 7 +#define MCDE_DSIVID1CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, PACKING, \ + MCDE_DSIVID1CONF0_PACKING_##__x) +#define MCDE_DSIVID1CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, PACKING, __x) +#define MCDE_DSICMD1CONF0 0x00000E60 +#define MCDE_DSICMD1CONF0_BLANKING_SHIFT 0 +#define MCDE_DSICMD1CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSICMD1CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, BLANKING, __x) +#define MCDE_DSICMD1CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSICMD1CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSICMD1CONF0_VID_MODE_CMD 0 +#define MCDE_DSICMD1CONF0_VID_MODE_VID 1 +#define MCDE_DSICMD1CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, VID_MODE, \ + MCDE_DSICMD1CONF0_VID_MODE_##__x) +#define MCDE_DSICMD1CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, VID_MODE, __x) +#define MCDE_DSICMD1CONF0_CMD8_SHIFT 13 +#define MCDE_DSICMD1CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSICMD1CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, CMD8, __x) +#define MCDE_DSICMD1CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSICMD1CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSICMD1CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, BIT_SWAP, __x) +#define MCDE_DSICMD1CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSICMD1CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSICMD1CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, BYTE_SWAP, __x) +#define MCDE_DSICMD1CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSICMD1CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSICMD1CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSICMD1CONF0_PACKING_SHIFT 20 +#define MCDE_DSICMD1CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSICMD1CONF0_PACKING_RGB565 0 +#define MCDE_DSICMD1CONF0_PACKING_RGB666 1 +#define MCDE_DSICMD1CONF0_PACKING_RGB888 2 +#define MCDE_DSICMD1CONF0_PACKING_BGR888 3 +#define MCDE_DSICMD1CONF0_PACKING_HDTV 7 +#define MCDE_DSICMD1CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, PACKING, \ + MCDE_DSICMD1CONF0_PACKING_##__x) +#define MCDE_DSICMD1CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, PACKING, __x) +#define MCDE_DSIVID2CONF0 0x00000E80 +#define MCDE_DSIVID2CONF0_BLANKING_SHIFT 0 +#define MCDE_DSIVID2CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSIVID2CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, BLANKING, __x) +#define MCDE_DSIVID2CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSIVID2CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSIVID2CONF0_VID_MODE_CMD 0 +#define MCDE_DSIVID2CONF0_VID_MODE_VID 1 +#define MCDE_DSIVID2CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, VID_MODE, \ + MCDE_DSIVID2CONF0_VID_MODE_##__x) +#define MCDE_DSIVID2CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, VID_MODE, __x) +#define MCDE_DSIVID2CONF0_CMD8_SHIFT 13 +#define MCDE_DSIVID2CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSIVID2CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, CMD8, __x) +#define MCDE_DSIVID2CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSIVID2CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSIVID2CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, BIT_SWAP, __x) +#define MCDE_DSIVID2CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSIVID2CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSIVID2CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, BYTE_SWAP, __x) +#define MCDE_DSIVID2CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSIVID2CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSIVID2CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSIVID2CONF0_PACKING_SHIFT 20 +#define MCDE_DSIVID2CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSIVID2CONF0_PACKING_RGB565 0 +#define MCDE_DSIVID2CONF0_PACKING_RGB666 1 +#define MCDE_DSIVID2CONF0_PACKING_RGB888 2 +#define MCDE_DSIVID2CONF0_PACKING_BGR888 3 +#define MCDE_DSIVID2CONF0_PACKING_HDTV 7 +#define MCDE_DSIVID2CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, PACKING, \ + MCDE_DSIVID2CONF0_PACKING_##__x) +#define MCDE_DSIVID2CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, PACKING, __x) +#define MCDE_DSICMD2CONF0 0x00000EA0 +#define MCDE_DSICMD2CONF0_BLANKING_SHIFT 0 +#define MCDE_DSICMD2CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSICMD2CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, BLANKING, __x) +#define MCDE_DSICMD2CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSICMD2CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSICMD2CONF0_VID_MODE_CMD 0 +#define MCDE_DSICMD2CONF0_VID_MODE_VID 1 +#define MCDE_DSICMD2CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, VID_MODE, \ + MCDE_DSICMD2CONF0_VID_MODE_##__x) +#define MCDE_DSICMD2CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, VID_MODE, __x) +#define MCDE_DSICMD2CONF0_CMD8_SHIFT 13 +#define MCDE_DSICMD2CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSICMD2CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, CMD8, __x) +#define MCDE_DSICMD2CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSICMD2CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSICMD2CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, BIT_SWAP, __x) +#define MCDE_DSICMD2CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSICMD2CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSICMD2CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, BYTE_SWAP, __x) +#define MCDE_DSICMD2CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSICMD2CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSICMD2CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSICMD2CONF0_PACKING_SHIFT 20 +#define MCDE_DSICMD2CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSICMD2CONF0_PACKING_RGB565 0 +#define MCDE_DSICMD2CONF0_PACKING_RGB666 1 +#define MCDE_DSICMD2CONF0_PACKING_RGB888 2 +#define MCDE_DSICMD2CONF0_PACKING_BGR888 3 +#define MCDE_DSICMD2CONF0_PACKING_HDTV 7 +#define MCDE_DSICMD2CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, PACKING, \ + MCDE_DSICMD2CONF0_PACKING_##__x) +#define MCDE_DSICMD2CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, PACKING, __x) +#define MCDE_DSIVID0FRAME 0x00000E04 +#define MCDE_DSIVID0FRAME_GROUPOFFSET 0x20 +#define MCDE_DSIVID0FRAME_FRAME_SHIFT 0 +#define MCDE_DSIVID0FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSIVID0FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0FRAME, FRAME, __x) +#define MCDE_DSICMD0FRAME 0x00000E24 +#define MCDE_DSICMD0FRAME_FRAME_SHIFT 0 +#define MCDE_DSICMD0FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSICMD0FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0FRAME, FRAME, __x) +#define MCDE_DSIVID1FRAME 0x00000E44 +#define MCDE_DSIVID1FRAME_FRAME_SHIFT 0 +#define MCDE_DSIVID1FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSIVID1FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1FRAME, FRAME, __x) +#define MCDE_DSICMD1FRAME 0x00000E64 +#define MCDE_DSICMD1FRAME_FRAME_SHIFT 0 +#define MCDE_DSICMD1FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSICMD1FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1FRAME, FRAME, __x) +#define MCDE_DSIVID2FRAME 0x00000E84 +#define MCDE_DSIVID2FRAME_FRAME_SHIFT 0 +#define MCDE_DSIVID2FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSIVID2FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2FRAME, FRAME, __x) +#define MCDE_DSICMD2FRAME 0x00000EA4 +#define MCDE_DSICMD2FRAME_FRAME_SHIFT 0 +#define MCDE_DSICMD2FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSICMD2FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2FRAME, FRAME, __x) +#define MCDE_DSIVID0PKT 0x00000E08 +#define MCDE_DSIVID0PKT_GROUPOFFSET 0x20 +#define MCDE_DSIVID0PKT_PACKET_SHIFT 0 +#define MCDE_DSIVID0PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSIVID0PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0PKT, PACKET, __x) +#define MCDE_DSICMD0PKT 0x00000E28 +#define MCDE_DSICMD0PKT_PACKET_SHIFT 0 +#define MCDE_DSICMD0PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSICMD0PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0PKT, PACKET, __x) +#define MCDE_DSIVID1PKT 0x00000E48 +#define MCDE_DSIVID1PKT_PACKET_SHIFT 0 +#define MCDE_DSIVID1PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSIVID1PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1PKT, PACKET, __x) +#define MCDE_DSICMD1PKT 0x00000E68 +#define MCDE_DSICMD1PKT_PACKET_SHIFT 0 +#define MCDE_DSICMD1PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSICMD1PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1PKT, PACKET, __x) +#define MCDE_DSIVID2PKT 0x00000E88 +#define MCDE_DSIVID2PKT_PACKET_SHIFT 0 +#define MCDE_DSIVID2PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSIVID2PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2PKT, PACKET, __x) +#define MCDE_DSICMD2PKT 0x00000EA8 +#define MCDE_DSICMD2PKT_PACKET_SHIFT 0 +#define MCDE_DSICMD2PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSICMD2PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2PKT, PACKET, __x) +#define MCDE_DSIVID0SYNC 0x00000E0C +#define MCDE_DSIVID0SYNC_GROUPOFFSET 0x20 +#define MCDE_DSIVID0SYNC_DMA_SHIFT 0 +#define MCDE_DSIVID0SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSIVID0SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0SYNC, DMA, __x) +#define MCDE_DSIVID0SYNC_SW_SHIFT 16 +#define MCDE_DSIVID0SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSIVID0SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0SYNC, SW, __x) +#define MCDE_DSICMD0SYNC 0x00000E2C +#define MCDE_DSICMD0SYNC_DMA_SHIFT 0 +#define MCDE_DSICMD0SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSICMD0SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0SYNC, DMA, __x) +#define MCDE_DSICMD0SYNC_SW_SHIFT 16 +#define MCDE_DSICMD0SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSICMD0SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0SYNC, SW, __x) +#define MCDE_DSIVID1SYNC 0x00000E4C +#define MCDE_DSIVID1SYNC_DMA_SHIFT 0 +#define MCDE_DSIVID1SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSIVID1SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1SYNC, DMA, __x) +#define MCDE_DSIVID1SYNC_SW_SHIFT 16 +#define MCDE_DSIVID1SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSIVID1SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1SYNC, SW, __x) +#define MCDE_DSICMD1SYNC 0x00000E6C +#define MCDE_DSICMD1SYNC_DMA_SHIFT 0 +#define MCDE_DSICMD1SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSICMD1SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1SYNC, DMA, __x) +#define MCDE_DSICMD1SYNC_SW_SHIFT 16 +#define MCDE_DSICMD1SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSICMD1SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1SYNC, SW, __x) +#define MCDE_DSIVID2SYNC 0x00000E8C +#define MCDE_DSIVID2SYNC_DMA_SHIFT 0 +#define MCDE_DSIVID2SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSIVID2SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2SYNC, DMA, __x) +#define MCDE_DSIVID2SYNC_SW_SHIFT 16 +#define MCDE_DSIVID2SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSIVID2SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2SYNC, SW, __x) +#define MCDE_DSICMD2SYNC 0x00000EAC +#define MCDE_DSICMD2SYNC_DMA_SHIFT 0 +#define MCDE_DSICMD2SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSICMD2SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2SYNC, DMA, __x) +#define MCDE_DSICMD2SYNC_SW_SHIFT 16 +#define MCDE_DSICMD2SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSICMD2SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2SYNC, SW, __x) +#define MCDE_DSIVID0CMDW 0x00000E10 +#define MCDE_DSIVID0CMDW_GROUPOFFSET 0x20 +#define MCDE_DSIVID0CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSIVID0CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSIVID0CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSIVID0CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSIVID0CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSIVID0CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CMDW, CMDW_START, __x) +#define MCDE_DSICMD0CMDW 0x00000E30 +#define MCDE_DSICMD0CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSICMD0CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSICMD0CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSICMD0CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSICMD0CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSICMD0CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CMDW, CMDW_START, __x) +#define MCDE_DSIVID1CMDW 0x00000E50 +#define MCDE_DSIVID1CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSIVID1CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSIVID1CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSIVID1CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSIVID1CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSIVID1CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CMDW, CMDW_START, __x) +#define MCDE_DSICMD1CMDW 0x00000E70 +#define MCDE_DSICMD1CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSICMD1CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSICMD1CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSICMD1CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSICMD1CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSICMD1CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CMDW, CMDW_START, __x) +#define MCDE_DSIVID2CMDW 0x00000E90 +#define MCDE_DSIVID2CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSIVID2CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSIVID2CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSIVID2CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSIVID2CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSIVID2CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CMDW, CMDW_START, __x) +#define MCDE_DSICMD2CMDW 0x00000EB0 +#define MCDE_DSICMD2CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSICMD2CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSICMD2CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSICMD2CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSICMD2CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSICMD2CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CMDW, CMDW_START, __x) +#define MCDE_DSIVID0DELAY0 0x00000E14 +#define MCDE_DSIVID0DELAY0_GROUPOFFSET 0x20 +#define MCDE_DSIVID0DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSIVID0DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSIVID0DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0DELAY0, INTPKTDEL, __x) +#define MCDE_DSICMD0DELAY0 0x00000E34 +#define MCDE_DSICMD0DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSICMD0DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSICMD0DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0DELAY0, INTPKTDEL, __x) +#define MCDE_DSIVID1DELAY0 0x00000E54 +#define MCDE_DSIVID1DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSIVID1DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSIVID1DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1DELAY0, INTPKTDEL, __x) +#define MCDE_DSICMD1DELAY0 0x00000E74 +#define MCDE_DSICMD1DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSICMD1DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSICMD1DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1DELAY0, INTPKTDEL, __x) +#define MCDE_DSIVID2DELAY0 0x00000E94 +#define MCDE_DSIVID2DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSIVID2DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSIVID2DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2DELAY0, INTPKTDEL, __x) +#define MCDE_DSICMD2DELAY0 0x00000EB4 +#define MCDE_DSICMD2DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSICMD2DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSICMD2DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2DELAY0, INTPKTDEL, __x) +#define MCDE_DSIVID0DELAY1 0x00000E18 +#define MCDE_DSIVID0DELAY1_GROUPOFFSET 0x20 +#define MCDE_DSIVID0DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSIVID0DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSIVID0DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0DELAY1, TEREQDEL, __x) +#define MCDE_DSIVID0DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSIVID0DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSIVID0DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSICMD0DELAY1 0x00000E38 +#define MCDE_DSICMD0DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSICMD0DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSICMD0DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0DELAY1, TEREQDEL, __x) +#define MCDE_DSICMD0DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSICMD0DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSICMD0DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSIVID1DELAY1 0x00000E58 +#define MCDE_DSIVID1DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSIVID1DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSIVID1DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1DELAY1, TEREQDEL, __x) +#define MCDE_DSIVID1DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSIVID1DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSIVID1DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSICMD1DELAY1 0x00000E78 +#define MCDE_DSICMD1DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSICMD1DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSICMD1DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1DELAY1, TEREQDEL, __x) +#define MCDE_DSICMD1DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSICMD1DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSICMD1DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSIVID2DELAY1 0x00000E98 +#define MCDE_DSIVID2DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSIVID2DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSIVID2DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2DELAY1, TEREQDEL, __x) +#define MCDE_DSIVID2DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSIVID2DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSIVID2DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSICMD2DELAY1 0x00000EB8 +#define MCDE_DSICMD2DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSICMD2DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSICMD2DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2DELAY1, TEREQDEL, __x) +#define MCDE_DSICMD2DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSICMD2DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSICMD2DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2DELAY1, FRAMESTARTDEL, __x) + +#endif /*__MCDE_REGS_H_ */ diff --git a/board/st/u8500/u8500.c b/board/st/u8500/u8500.c index a38e9b91b..5bd11a4dc 100644 --- a/board/st/u8500/u8500.c +++ b/board/st/u8500/u8500.c @@ -13,9 +13,13 @@ #include <asm/arch/clock.h> #include <asm/arch/hardware.h> #include <asm/arch/ab8500.h> +#include <tc35892.h> #include "gpio.h" #include "common.h" +#ifdef CONFIG_VIDEO_LOGO +#include "mcde_display.h" +#endif #define NOMADIK_PER4_BASE (0x80150000) #define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000) #define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000) @@ -171,6 +175,52 @@ int dram_init(void) return 0; } +#ifdef CONFIG_VIDEO_LOGO +int dss_init(void) +{ + int ret = 0; + uchar byte; + puts("MCDE: "); + if (!cpu_is_u8500v11()) { + printf("Only HREF+ is supported \n"); + goto mcde_error; + } + (void) i2c_set_bus_num(0); + (void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1); + if (byte == 0x01) + board_id = 0; + else + board_id = 1; + + if (board_id != 0) { + ret = mcde_startup(); + if (ret) { + printf("startup failed\n"); + goto mcde_error; + } + ret = mcde_display_image(); + if (ret) { + printf("display_image failed\n"); + goto mcde_error; + } + + printf("ready \n"); + setenv("startup_graphics", "1"); + setenv("logo", "nologo"); + goto mcde_ok; + } else { + ret = 1; + printf("MOP500 is not supported \n"); + } +mcde_error: + setenv("startup_graphics", "0"); + setenv("logo", "0"); +mcde_ok: + return ret; + +} +#endif + unsigned int addr_vall_arr[] = { 0x8011F000, 0x0000FFFF, // Clocks for HSI TODO Enable reqd only 0x8011F008, 0x00001CFF, // Clocks for HSI TODO Enable reqd only @@ -305,6 +355,9 @@ int board_late_init(void) &byte_array[0], 2); } #endif /* CONFIG_MMC */ +#ifdef CONFIG_VIDEO_LOGO + dss_init(); +#endif return (0); } #endif /* BOARD_LATE_INIT */ |