diff options
| author | TsiChungLiew <Tsi-Chung.Liew@freescale.com> | 2007-07-05 23:05:31 -0500 |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2007-07-10 14:29:09 -0600 |
| commit | b9bf3de377b2bae70c983c9b97feae914999e735 (patch) | |
| tree | cb5ad5216158a854647505f29faa9c4ebd2b5c36 /cpu/mcf532x | |
| parent | 84a015b52ec820a5ae173717d78516de731c89c2 (diff) | |
Update header file and some clean up
Replaced immap_5329.h and m5329.h with immap.h. Removed whitespaces.
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'cpu/mcf532x')
| -rw-r--r-- | cpu/mcf532x/speed.c | 30 |
1 files changed, 12 insertions, 18 deletions
diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index c4ba7ec66..cf72609b4 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -28,23 +28,22 @@ #include <common.h> #include <asm/processor.h> -#include <asm/m5329.h> -#include <asm/immap_5329.h> +#include <asm/immap.h> /* PLL min/max specifications */ -#define MAX_FVCO 500000 /* KHz */ -#define MAX_FSYS 80000 /* KHz */ -#define MIN_FSYS 58333 /* KHz */ -#define FREF 16000 /* KHz */ -#define MAX_MFD 135 /* Multiplier */ -#define MIN_MFD 88 /* Multiplier */ -#define BUSDIV 6 /* Divider */ +#define MAX_FVCO 500000 /* KHz */ +#define MAX_FSYS 80000 /* KHz */ +#define MIN_FSYS 58333 /* KHz */ +#define FREF 16000 /* KHz */ +#define MAX_MFD 135 /* Multiplier */ +#define MIN_MFD 88 /* Multiplier */ +#define BUSDIV 6 /* Divider */ /* * Low Power Divider specifications */ -#define MIN_LPD (1 << 0) /* Divider (not encoded) */ -#define MAX_LPD (1 << 15) /* Divider (not encoded) */ -#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ +#define MIN_LPD (1 << 0) /* Divider (not encoded) */ +#define MAX_LPD (1 << 15) /* Divider (not encoded) */ +#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ /* * Get the value of the current system clock @@ -174,9 +173,6 @@ int clock_pll(int fsys, int flags) * If it has then the SDRAM needs to be put into self refresh * mode before reprogramming the PLL. */ - /* Put SDRAM into self refresh mode */ -/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) - MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;*/ /* * Initialize the PLL to generate the new system clock frequency. @@ -197,12 +193,10 @@ int clock_pll(int fsys, int flags) /* * Return the SDRAM to normal operation if it is in use. */ - /* Exit self refresh mode */ -/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;*/ /* software workaround for SDRAM opeartion after exiting LIMP mode errata */ *sdram_workaround = CFG_SDRAM_BASE; + /* wait for DQS logic to relock */ for (i = 0; i < 0x200; i++) ; |