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authorKumar Gala <galak@kernel.crashing.org>2009-11-13 09:04:19 -0600
committerKumar Gala <galak@kernel.crashing.org>2010-01-05 13:49:08 -0600
commit355f4f85e90ce2e6d91883012c2993be7970c8b1 (patch)
tree7380c8c9cd3d6464f0da09767b7fcd3ccf41c06a /cpu/mpc85xx/tlb.c
parent94e9411b9dda182dd63d53ba6ea640c98b35db5f (diff)
ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation
Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/tlb.c')
-rw-r--r--cpu/mpc85xx/tlb.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 234fdaa60..b3037acea 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -227,14 +227,10 @@ void init_addr_map(void)
}
#endif
-#ifndef CONFIG_SYS_DDR_TLB_START
-#define CONFIG_SYS_DDR_TLB_START 8
-#endif
-
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
+ int i;
unsigned int tlb_size;
- unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
u64 size, memsize = (u64)memsize_in_meg << 20;
@@ -244,10 +240,14 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
/* Convert (4^max) kB to (2^max) bytes */
max_cam = max_cam * 2 + 10;
- for (; size && ram_tlb_index < 16; ram_tlb_index++) {
+ for (i = 0; size && i < 8; i++) {
+ int ram_tlb_index = find_free_tlbcam();
u32 camsize = __ilog2_u64(size) & ~1U;
u32 align = __ilog2(ram_tlb_address) & ~1U;
+ if (ram_tlb_index == -1)
+ break;
+
if (align == -2) align = max_cam;
if (camsize > align)
camsize = align;