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| author | Wolfgang Denk <wd@denx.de> | 2007-04-18 17:00:09 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-04-18 17:00:09 +0200 |
| commit | 43f6226db002af1d1ff1adf35b422dcce9f76f76 (patch) | |
| tree | c2badee8575584bba24e33f62325e95d812dbc79 /cpu/ppc4xx/start.S | |
| parent | b99c1e6d8eec327c4b4dd99bf4c0d1a1eba2ce0a (diff) | |
| parent | efa013df333fb680eedfcad22283083614dad418 (diff) | |
Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xx
Diffstat (limited to 'cpu/ppc4xx/start.S')
| -rw-r--r-- | cpu/ppc4xx/start.S | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3b1586c0a..a96083caa 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1892,11 +1892,11 @@ pll_wait: #endif /* CONFIG_405EP */ #if defined(CONFIG_440) -#define function_prolog(func_name) .text; \ +#define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ func_name: -#define function_epilog(func_name) .type func_name,@function; \ +#define function_epilog(func_name) .type func_name,@function; \ .size func_name,.-func_name /*----------------------------------------------------------------------------+ @@ -1952,13 +1952,13 @@ pll_wait: +----------------------------------------------------------------------------*/ function_prolog(dcbz_area) rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 -..d_ra2:mtctr r5 -..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 +..d_ra2:mtctr r5 +..d_ag2:dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag2 sync blr function_epilog(dcbz_area) @@ -1967,26 +1967,26 @@ pll_wait: | dflush. Assume 32K at vector address is cachable. +----------------------------------------------------------------------------*/ function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 ..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 +..ag: dcbf r0,r3 + addi r3,r3,-32 + bdnz ..ag sync - mtmsr r9 + mtmsr r9 blr function_epilog(dflush) #endif /* CONFIG_440 */ |