diff options
| author | Joakim Axelsson <joakim.axelsson@stericsson.com> | 2010-12-03 15:14:19 +0800 |
|---|---|---|
| committer | Michael BRANDT <michael.brandt@stericsson.com> | 2010-12-08 16:20:16 +0100 |
| commit | c6b4e8c0340357c795f5898cf5e4141e845a2801 (patch) | |
| tree | 888b24c9c41122ef77dd66f47e1f6dcc962375c0 /cpu | |
| parent | af78cad05fbf943619f6446b12203552b02aba11 (diff) | |
db8500: Clean up PRCMU code in db8500 SoC code
Clean up of PRCMU code in db8500 SoC code. Move things from cpu.c
and clock.h to prcmu.c. Also remove duplicate #defines and have
prcmu.c use the #defines in prcmu.h.
ST-Ericsson ID: None
Signed-off-by: Joakim Axelsson <joakim.axelsson@stericsson.com>
Change-Id: Ieffb0094b3f43f0c88f3ed457c6cb296fa0ce378
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/9899
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Michael BRANDT <michael.brandt@stericsson.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa9/db8500/cpu.c | 18 | ||||
| -rw-r--r-- | cpu/arm_cortexa9/db8500/prcmu.c | 27 |
2 files changed, 27 insertions, 18 deletions
diff --git a/cpu/arm_cortexa9/db8500/cpu.c b/cpu/arm_cortexa9/db8500/cpu.c index eb25b247f..e05eaad9b 100644 --- a/cpu/arm_cortexa9/db8500/cpu.c +++ b/cpu/arm_cortexa9/db8500/cpu.c @@ -55,23 +55,7 @@ static void init_regs(void) *((volatile unsigned int *)(addr_vall_arr[2 * i])) = addr_vall_arr[(2 * i) + 1]; } else { - struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE; - - /* Enable timers */ - writel(1 << 17, &prcmu->tcr); - - u8500_prcmu_enable(&prcmu->per1clk_mgt); - u8500_prcmu_enable(&prcmu->per2clk_mgt); - u8500_prcmu_enable(&prcmu->per3clk_mgt); - u8500_prcmu_enable(&prcmu->per5clk_mgt); - u8500_prcmu_enable(&prcmu->per6clk_mgt); - u8500_prcmu_enable(&prcmu->per7clk_mgt); - - u8500_prcmu_enable(&prcmu->uartclk_mgt); - u8500_prcmu_enable(&prcmu->i2cclk_mgt); - - u8500_prcmu_enable(&prcmu->sdmmcclk_mgt); - + db8500_prcmu_init(); db8500_clocks_init(); } } diff --git a/cpu/arm_cortexa9/db8500/prcmu.c b/cpu/arm_cortexa9/db8500/prcmu.c index 1cd4a7f8e..a82379f94 100644 --- a/cpu/arm_cortexa9/db8500/prcmu.c +++ b/cpu/arm_cortexa9/db8500/prcmu.c @@ -17,7 +17,7 @@ #include <config.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> +#include <asm/arch/prcmu.h> #include <asm/types.h> #include <asm/io.h> #include <asm/errno.h> @@ -204,3 +204,28 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) return -1; } } + +static void prcmu_enable(u32 *reg) +{ + writel(readl(reg) | (1 << 8), reg); +} + +void db8500_prcmu_init(void) +{ + /* Enable timers */ + writel(1 << 17, PRCM_TCR); + + prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG); + prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG); + prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG); + /* PER4CLK does not exist */ + prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG); + prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG); + /* Only exists in ED but is always ok to write to */ + prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG); + + prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG); + prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG); + + prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG); +} |