diff options
| author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2008-03-24 20:46:24 +0300 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-03-25 19:16:45 -0500 |
| commit | 91cdaa3a9d7562b869d96774e9c9ddf142c0848d (patch) | |
| tree | 3706d31d19eda36a4a64d5839780526ea31b3854 /drivers/qe | |
| parent | aabce7fb505ffe55ebf3bf4dcafdae97a581558d (diff) | |
uec: add support for gbit mii status readings
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Diffstat (limited to 'drivers/qe')
| -rw-r--r-- | drivers/qe/uec_phy.c | 28 | ||||
| -rw-r--r-- | drivers/qe/uec_phy.h | 5 |
2 files changed, 24 insertions, 9 deletions
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index a42701c59..8c4a558d8 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -318,16 +318,26 @@ static int genmii_read_status (struct uec_mii_info *mii_info) return err; if (mii_info->autoneg) { - status = phy_read (mii_info, PHY_ANLPAR); + status = phy_read(mii_info, MII_1000BASETSTATUS); - if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) - mii_info->speed = SPEED_100; - else - mii_info->speed = SPEED_10; + if (status & (LPA_1000FULL | LPA_1000HALF)) { + mii_info->speed = SPEED_1000; + if (status & LPA_1000FULL) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + } else { + status = phy_read(mii_info, PHY_ANLPAR); + + if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) + mii_info->speed = SPEED_100; + else + mii_info->speed = SPEED_10; + } mii_info->pause = 0; } /* On non-aneg, we assume what we put in BMCR is the speed, diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index e59a940e0..6f769fb50 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -29,6 +29,11 @@ #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 +/* 1000BT status */ +#define MII_1000BASETSTATUS 0x0a +#define LPA_1000FULL 0x0400 +#define LPA_1000HALF 0x0200 + /* Cicada Extended Control Register 1 */ #define MII_CIS8201_EXT_CON1 0x17 #define MII_CIS8201_EXTCON1_INIT 0x0000 |