ColdFire: MCF52x2 Header files update

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

1 files changed, 68 insertions, 68 deletions

diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h
index 424dc1d1f..d9dc01591 100644
--- a/include/asm-m68k/immap_5271.h
+++ b/include/asm-m68k/immap_5271.h
@@ -26,73 +26,73 @@
 #ifndef __IMMAP_5271__
 #define __IMMAP_5271__
 
-/* Interrupt module registers
-*/
-typedef struct int_ctrl {
-	uint	int_icr1;
-	uint	int_icr2;
-	uint	int_icr3;
-	uint	int_icr4;
-	uint	int_isr;
-	uint	int_pitr;
-	uint	int_piwr;
-	uchar	res1[3];
-	uchar	int_pivr;
-} intctrl_t;
+#define MMAP_SCM	(CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CFG_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_MBAR + 0x00000110)
+#define MMAP_DMA2	(CFG_MBAR + 0x00000120)
+#define MMAP_DMA3	(CFG_MBAR + 0x00000130)
+#define MMAP_UART0	(CFG_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_MBAR + 0x00000F00)
+#define MMAP_FEC	(CFG_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CFG_MBAR + 0x00001400)
+#define MMAP_GPIO	(CFG_MBAR + 0x00100000)
+#define MMAP_CCM	(CFG_MBAR + 0x00110000)
+#define MMAP_PLL	(CFG_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_MBAR + 0x00180000)
+#define MMAP_MDHA	(CFG_MBAR + 0x00190000)
+#define MMAP_RNG	(CFG_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CFG_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CFG_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CFG_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CFG_MBAR + 0x001F0000)
 
-/* Timer module registers
- */
-typedef struct timer_ctrl {
-	ushort	timer_tmr;
-	ushort	res1;
-	ushort	timer_trr;
-	ushort	res2;
-	ushort	timer_tcap;
-	ushort	res3;
-	ushort	timer_tcn;
-	ushort	res4;
-	ushort	timer_ter;
-	uchar	res5[14];
-} timer_t;
-
- /* Fast ethernet controller registers
-  */
-typedef struct fec {
-	uint    res1;
-	uint    fec_ievent;
-	uint    fec_imask;
-	uint    res2;
-	uint    fec_r_des_active;
-	uint    fec_x_des_active;
-	uint    res3[3];
-	uint    fec_ecntrl;
-	uint    res4[6];
-	uint    fec_mii_data;
-	uint    fec_mii_speed;
-	uint    res5[7];
-	uint    fec_mibc;
-	uint    res6[7];
-	uint    fec_r_cntrl;
-	uint    res7[15];
-	uint    fec_x_cntrl;
-	uint    res8[7];
-	uint    fec_addr_low;
-	uint    fec_addr_high;
-	uint    fec_opd;
-	uint    res9[10];
-	uint    fec_ihash_table_high;
-	uint    fec_ihash_table_low;
-	uint    fec_ghash_table_high;
-	uint    fec_ghash_table_low;
-	uint    res10[7];
-	uint    fec_tfwr;
-	uint    res11;
-	uint    fec_r_bound;
-	uint    fec_r_fstart;
-	uint    res12[11];
-	uint    fec_r_des_start;
-	uint    fec_x_des_start;
-	uint    fec_r_buff_size;
-} fec_t;
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+	/* Interrupt Controller 0 */
+	u32 iprh0;		/* 0x00 Pending Register High */
+	u32 iprl0;		/* 0x04 Pending Register Low */
+	u32 imrh0;		/* 0x08 Mask Register High */
+	u32 imrl0;		/* 0x0C Mask Register Low */
+	u32 frch0;		/* 0x10 Force Register High */
+	u32 frcl0;		/* 0x14 Force Register Low */
+	u8 irlr;		/* 0x18 */
+	u8 iacklpr;		/* 0x19 */
+	u16 res1[19];		/* 0x1a - 0x3c */
+	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
+	u32 res3[24];		/* 0x80 - 0xDF */
+	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
+	u8 res4[3];		/* 0xE1 - 0xE3 */
+	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
+	u8 res5[3];		/* 0xE5 - 0xE7 */
+	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
+	u8 res6[3];		/* 0xE9 - 0xEB */
+	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
+	u8 res7[3];		/* 0xED - 0xEF */
+	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
+	u8 res8[3];		/* 0xF1 - 0xF3 */
+	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
+	u8 res9[3];		/* 0xF5 - 0xF7 */
+	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
+	u8 resa[3];		/* 0xF9 - 0xFB */
+	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
+	u8 resb[3];		/* 0xFD - 0xFF */
+} int0_t;
 
-#endif /* __IMMAP_5271__ */
+#endif				/* __IMMAP_5271__ */