ColdFire: Modules header files cleanup

Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
MDHA, SKHA, INTC, and FlexBus structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
SSI cleanup. Remove USB Host structure from immap_539.h.
Apply changes to use FlexBus structures in mcf52x2's
cpu_init.c and platform configuration files.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

1 files changed, 9 insertions, 82 deletions

diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
index e96463be4..dd526a119 100644
--- a/include/asm-m68k/immap_5282.h
+++ b/include/asm-m68k/immap_5282.h
@@ -62,6 +62,12 @@
 #define MMAP_CFMC	(CONFIG_SYS_MBAR + 0x001D0000)
 #define MMAP_CFMMEM	(CONFIG_SYS_MBAR + 0x04000000)
 
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/qspi.h>
+
 /* System Control Module */
 typedef struct scm_ctrl {
 	u32 ipsbar;
@@ -92,88 +98,9 @@ typedef struct scm_ctrl {
 	u16 res8;
 } scm_t;
 
-/* Flexbus module Chip select registers */
-typedef struct fbcs_ctrl {
-	u16 csar0;		/* 0x00 Chip-Select Address Register 0 */
-	u16 res0;
-	u32 csmr0;		/* 0x04 Chip-Select Mask Register 0 */
-	u16 res1;		/* 0x08 */
-	u16 cscr0;		/* 0x0A Chip-Select Control Register 0 */
-
-	u16 csar1;		/* 0x0C Chip-Select Address Register 1 */
-	u16 res2;
-	u32 csmr1;		/* 0x10 Chip-Select Mask Register 1 */
-	u16 res3;		/* 0x14 */
-	u16 cscr1;		/* 0x16 Chip-Select Control Register 1 */
-
-	u16 csar2;		/* 0x18 Chip-Select Address Register 2 */
-	u16 res4;
-	u32 csmr2;		/* 0x1C Chip-Select Mask Register 2 */
-	u16 res5;		/* 0x20 */
-	u16 cscr2;		/* 0x22 Chip-Select Control Register 2 */
-
-	u16 csar3;		/* 0x24 Chip-Select Address Register 3 */
-	u16 res6;
-	u32 csmr3;		/* 0x28 Chip-Select Mask Register 3 */
-	u16 res7;		/* 0x2C */
-	u16 cscr3;		/* 0x2E Chip-Select Control Register 3 */
-
-	u16 csar4;		/* 0x30 Chip-Select Address Register 4 */
-	u16 res8;
-	u32 csmr4;		/* 0x34 Chip-Select Mask Register 4 */
-	u16 res9;		/* 0x38 */
-	u16 cscr4;		/* 0x3A Chip-Select Control Register 4 */
-
-	u16 csar5;		/* 0x3C Chip-Select Address Register 5 */
-	u16 res10;
-	u32 csmr5;		/* 0x40 Chip-Select Mask Register 5 */
-	u16 res11;		/* 0x44 */
-	u16 cscr5;		/* 0x46 Chip-Select Control Register 5 */
-
-	u16 csar6;		/* 0x48 Chip-Select Address Register 5 */
-	u16 res12;
-	u32 csmr6;		/* 0x4C Chip-Select Mask Register 5 */
-	u16 res13;		/* 0x50 */
-	u16 cscr6;		/* 0x52 Chip-Select Control Register 5 */
-
-	u16 csar7;		/* 0x54 Chip-Select Address Register 5 */
-	u16 res14;
-	u32 csmr7;		/* 0x58 Chip-Select Mask Register 5 */
-	u16 res15;		/* 0x5C */
-	u16 cscr7;		/* 0x5E Chip-Select Control Register 5 */
-} fbcs_t;
-
-/* Interrupt module registers */
-typedef struct int0_ctrl {
-	/* Interrupt Controller 0 */
-	u32 iprh0;		/* 0x00 Pending Register High */
-	u32 iprl0;		/* 0x04 Pending Register Low */
-	u32 imrh0;		/* 0x08 Mask Register High */
-	u32 imrl0;		/* 0x0C Mask Register Low */
-	u32 frch0;		/* 0x10 Force Register High */
-	u32 frcl0;		/* 0x14 Force Register Low */
-	u8 irlr;		/* 0x18 */
-	u8 iacklpr;		/* 0x19 */
-	u16 res1[19];		/* 0x1a - 0x3c */
-	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
-	u32 res3[24];		/* 0x80 - 0xDF */
-	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res4[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res5[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE9 - 0xEB */
-	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xED - 0xEF */
-	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF9 - 0xFB */
-	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xFD - 0xFF */
-} int0_t;
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
 
 /* Clock Module registers */
 typedef struct pll_ctrl {