diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-03-27 17:02:44 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-03-30 13:33:51 -0500 |
| commit | 22b6dbc1696d927d938dd4e16f65d83c0d4fb3f4 (patch) | |
| tree | 611cd5baec5cb44cb29fc46a2d2d8f7fb8ba23e6 /include/asm-ppc/immap_qe.h | |
| parent | 2d4de6ae5be54b367a72a7ef4e0cf36a9cd4881f (diff) | |
MPC85xx: Add MPC8569 CPU support
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-ppc/immap_qe.h')
| -rw-r--r-- | include/asm-ppc/immap_qe.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 39da3771c..66a4735dd 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -20,7 +20,9 @@ typedef struct qe_iram { u32 iadd; /* I-RAM Address Register */ u32 idata; /* I-RAM Data Register */ - u8 res0[0x78]; + u8 res0[0x4]; + u32 iready; + u8 res1[0x70]; } __attribute__ ((packed)) qe_iram_t; /* QE Interrupt Controller @@ -580,7 +582,7 @@ typedef struct qe_immap { u8 res14[0x300]; u8 res15[0x3A00]; u8 res16[0x8000]; /* 0x108000 - 0x110000 */ -#if defined(CONFIG_MPC8568) +#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ #else @@ -592,7 +594,7 @@ typedef struct qe_immap { extern qe_map_t *qe_immr; -#if defined(CONFIG_MPC8568) +#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569) #define QE_MURAM_SIZE 0x10000UL #elif defined(CONFIG_MPC8360) #define QE_MURAM_SIZE 0xc000UL |