diff options
| author | Timur Tabi <timur@freescale.com> | 2006-11-03 12:00:28 -0600 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2006-11-03 19:42:23 -0600 |
| commit | d239d74b1c937984bc519083a8e7de373a390f06 (patch) | |
| tree | 1311b60e3d00017bbe694570128d08e9699a2a24 /include/configs/MPC8349EMDS.h | |
| parent | f7fb2e703ec9688541416962724adff70a7322cb (diff) | |
mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR
Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.
Signed-off-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'include/configs/MPC8349EMDS.h')
| -rw-r--r-- | include/configs/MPC8349EMDS.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index e68c41acc..4a5b4bc4a 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -73,7 +73,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ -#define CFG_IMMRBAR 0xE0000000 +#define CFG_IMMR 0xE0000000 #undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00000000 /* memtest region */ @@ -311,8 +311,8 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER @@ -345,9 +345,9 @@ /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) /* USB */ #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ @@ -641,8 +641,8 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) |