diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2007-11-14 15:52:06 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-12-11 22:34:19 -0600 |
| commit | 1563f56e0c68f6920f956382d6d13bee3f01c0f7 (patch) | |
| tree | 1ad26d09de6261fa64c06dfdac14f780e3762c58 /include/configs/MPC8568MDS.h | |
| parent | b90d25497625b90ffa3f2911a0895ca237556ff5 (diff) | |
Add PCI Express support on MPC8568MDS
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8568MDS.h')
| -rw-r--r-- | include/configs/MPC8568MDS.h | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index b9366cc99..cf79257bd 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -33,7 +33,10 @@ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ -#define CONFIG_PCI +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCI controller */ +#define CONFIG_PCIE1 1 /* PCIE controller */ +#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE @@ -87,6 +90,9 @@ extern unsigned long get_clock_freq(void); #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + /* * DDR Setup */ @@ -325,12 +331,12 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ -#define CFG_PEX_MEM_BASE 0xa0000000 -#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE -#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PEX_IO_BASE 0x00000000 -#define CFG_PEX_IO_PHYS 0xe2800000 -#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */ +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe2800000 +#define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */ #define CFG_SRIO_MEM_BASE 0xc0000000 @@ -383,6 +389,11 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + #endif /* CONFIG_PCI */ #ifndef CONFIG_NET_MULTI |