diff options
| author | wdenk <wdenk> | 2004-04-15 18:22:41 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-04-15 18:22:41 +0000 |
| commit | 04a85b3b36fdbaaac5fa95d61f59f481bbcf7520 (patch) | |
| tree | a4c6731a78805c51f43a8b195034d2036b28941b /include/configs/NETVIA.h | |
| parent | d716b126718d874f52ffb694e6c22b7235cec483 (diff) | |
* Patches by Pantelis Antoniou, 30 Mar 2004:
- add auto-complete support to the U-Boot CLI
- add support for NETTA and NETPHONE boards; fix NETVIA board
* Patch by Yuli Barcohen, 28 Mar 2004:
- Add support for MPC8272 family including MPC8247/8248/8271/8272
- Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
- Change configuration method for MPC8260ADS family
Diffstat (limited to 'include/configs/NETVIA.h')
| -rw-r--r-- | include/configs/NETVIA.h | 35 |
1 files changed, 20 insertions, 15 deletions
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index 46505b6fd..8f93a49c0 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -36,7 +36,6 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_NETVIA 1 /* ...on a NetVia board */ -#undef CONFIG_NETVIA_PLL_CLOCK /* PLL or fixed crystal clock */ #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ @@ -49,14 +48,8 @@ #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#ifdef CONFIG_NETVIA_PLL_CLOCK -/* XXX make sure that you calculate these two correctly */ -#define CFG_GCLK_MF 1350 -#define CONFIG_8xx_GCLK_FREQ 44236800 -#else -#define CFG_GCLK_MF 1 -#define CONFIG_8xx_GCLK_FREQ 50000000 -#endif +#define CONFIG_XIN 10000000 +#define CONFIG_8xx_GCLK_FREQ 80000000 #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -253,22 +246,34 @@ * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit * - */ - -#define CFG_PLPRCR ( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */ + #define SCCR_MASK SCCR_EBDF11 + +#if CONFIG_8xx_GCLK_FREQ == 50000000 + +#define CFG_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) #define CFG_SCCR (SCCR_TBS | \ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) +#elif CONFIG_8xx_GCLK_FREQ == 80000000 + +#define CFG_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) + +#endif + /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- @@ -520,6 +525,6 @@ static inline void __led_set(led_id_t mask, int state) #endif -/****************************************************************/ +/*************************************************************************************************/ #endif /* __CONFIG_H */ |