diff options
| author | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
| commit | d9b94f28a442b0013caef99de084d7b72e2d4607 (patch) | |
| tree | 1b293a551e021a4a696717231ec03206d9f172de /include/configs/SBC8540.h | |
| parent | 288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff) | |
* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'include/configs/SBC8540.h')
| -rw-r--r-- | include/configs/SBC8540.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 5bdabfee9..0451b2081 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -227,10 +227,14 @@ #if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - #define CONFIG_NET_MULTI 1 - #define CONFIG_PHY_BCM5421S /* GigaBit Ether PHY */ - #define CONFIG_MII 1 /* MII PHY management */ - #define CONFIG_PHY_ADDR 25 /* PHY address */ +# define CONFIG_NET_MULTI 1 +# define CONFIG_MPC85xx_TSEC1 +# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" +# define CONFIG_MII 1 /* MII PHY management */ +# define TSEC1_PHY_ADDR 25 +# define TSEC1_PHYIDX 0 +/* Options are: TSEC0 */ +# define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |