diff options
| author | Peter Tyser <ptyser@xes-inc.com> | 2009-10-23 15:55:48 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-10-27 09:34:58 -0500 |
| commit | 48618126f78f05042dae428811809b594f747eb9 (patch) | |
| tree | 6521b730c69328a7d90da5c1d7e4b19cb66f1345 /include/configs/XPEDITE5370.h | |
| parent | 5ccd29c3679b3669b0bde5c501c1aa0f325a7acb (diff) | |
xpedite5370: Enable multi-core support
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/XPEDITE5370.h')
| -rw-r--r-- | include/configs/XPEDITE5370.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 26b798b4d..7782df367 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -49,6 +49,13 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* + * Multicore config + */ +#define CONFIG_MP +#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ +#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ + +/* * DDR config */ #define CONFIG_FSL_DDR2 @@ -109,6 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable |