Port AT91CAP9 to the new headers

Adapt the existing AT91CAP9 code to the new headers and APIs.

Signed-off-by: Stelian Pop <stelian@popies.net>

1 files changed, 16 insertions, 45 deletions

diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index f0dfd71ae..dab21d0c0 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stelian Pop <stelian.pop <at> leadtechdesign.com>
  * Lead Tech Design <www.leadtechdesign.com>
  *
@@ -28,8 +28,8 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK	200000000	/* from 12 MHz crystal */
-#define AT91C_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
+#define AT91_MAIN_CLOCK		200000000	/* from 12 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
 #define CFG_HZ			1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
@@ -46,19 +46,9 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SKIP_RELOCATE_UBOOT
 
-#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		ROUND(CFG_ENV_SIZE + 128*1024, 0x1000)
-#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
-
-#define CONFIG_BAUDRATE		115200
-
 /*
  * Hardware drivers
  */
-
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
@@ -104,7 +94,9 @@
 #define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
 #define CFG_MAX_DATAFLASH_BANKS		1
 #define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
-#define CONFIG_NEW_PARTITION		1
+#define AT91_SPI_CLK			20000000
+#define DATAFLASH_TCSS			(0xFA << 16)
+#define DATAFLASH_TCHS			(0x8 << 24)
 
 /* NOR flash */
 #define CFG_FLASH_CFI			1
@@ -114,39 +106,11 @@
 #define CFG_MAX_FLASH_SECT		256
 #define CFG_MAX_FLASH_BANKS		1
 
-#define AT91C_FLASH_NWE_SETUP		(4 << 0)
-#define AT91C_FLASH_NCS_WR_SETUP	(2 << 8)
-#define AT91C_FLASH_NRD_SETUP		(4 << 16)
-#define AT91C_FLASH_NCS_RD_SETUP	(2 << 24)
-
-#define AT91C_FLASH_NWE_PULSE		(8 << 0)
-#define AT91C_FLASH_NCS_WR_PULSE	(10 << 8)
-#define AT91C_FLASH_NRD_PULSE		(8 << 16)
-#define AT91C_FLASH_NCS_RD_PULSE	(10 << 24)
-
-#define AT91C_FLASH_NWE_CYCLE		(16 << 0)
-#define AT91C_FLASH_NRD_CYCLE		(16 << 16)
-
 /* NAND flash */
 #define NAND_MAX_CHIPS			1
 #define CFG_MAX_NAND_DEVICE		1
 #define CFG_NAND_BASE			0x40000000
 
-#define AT91C_SM_NWE_SETUP		(2 << 0)
-#define AT91C_SM_NCS_WR_SETUP		(1 << 8)
-#define AT91C_SM_NRD_SETUP		(2 << 16)
-#define AT91C_SM_NCS_RD_SETUP		(1 << 24)
-
-#define AT91C_SM_NWE_PULSE		(4 << 0)
-#define AT91C_SM_NCS_WR_PULSE		(6 << 8)
-#define AT91C_SM_NRD_PULSE		(4 << 16)
-#define AT91C_SM_NCS_RD_PULSE		(6 << 24)
-
-#define AT91C_SM_NWE_CYCLE		(8 << 0)
-#define AT91C_SM_NRD_CYCLE		(8 << 16)
-
-#define AT91C_SM_TDF			(1 << 16)
-
 /* Ethernet */
 #define CONFIG_MACB			1
 #define CONFIG_RMII			1
@@ -159,15 +123,14 @@
 #define LITTLEENDIAN			1
 #define CONFIG_DOS_PARTITION		1
 #define CFG_USB_OHCI_CPU_INIT		1
-#define CFG_USB_OHCI_REGS_BASE		0x00700000	/* AT91C_BASE_UHP */
+#define CFG_USB_OHCI_REGS_BASE		0x00700000	/* AT91_BASE_UHP */
 #define CFG_USB_OHCI_SLOT_NAME		"at91cap9"
 #define CFG_USB_OHCI_MAX_ROOT_PORTS	2
 
-
 #define CFG_LOAD_ADDR			0x72000000	/* load address */
 
 #define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			0x73000000
+#define CFG_MEMTEST_END			0x73e00000
 
 #define CFG_USE_DATAFLASH		1
 #undef CFG_USE_NORFLASH
@@ -194,6 +157,7 @@
 
 #endif
 
+#define CONFIG_BAUDRATE		115200
 #define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
 #define CFG_PROMPT		"U-Boot> "
@@ -203,6 +167,13 @@
 #define CFG_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
+#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		ROUND(CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
 #ifdef CONFIG_USE_IRQ