* Patch by Martin Winistoerfer, 23 Mar 2003

  - Add port to MPC555/556 microcontrollers
  - Add support for cmi customer board with
    Intel 28F128J3A, 28F320J3A or 28F640J3A flash.

* Patch by Rick Bronson, 28 Mar 2003:
  - fix common/cmd_nand.c

9 files changed, 914 insertions, 4 deletions

diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h
new file mode 100644
index 000000000..ffff975c9
--- /dev/null
+++ b/include/asm-ppc/5xx_immap.h
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 
+ */
+
+/*
+ * File:		5xx_immap.h
+ * 
+ * Discription:		MPC555 Internal Memory Map
+ * 
+ */
+ 
+#ifndef __IMMAP_5XX__
+#define __IMMAP_5XX__
+
+/* System Configuration Registers.
+*/
+typedef	struct sys_conf {
+        uint sc_siumcr;
+        uint sc_sypcr;
+        char res1[6];
+        ushort sc_swsr;
+        uint sc_sipend;
+        uint sc_simask;
+        uint sc_siel;
+        uint sc_sivec;
+        uint sc_tesr;
+        uint sc_sgpiodt1;
+        uint sc_sgpiodt2;
+        uint sc_sgpiocr;
+        uint sc_emcr;
+        uint sc_res1aa;
+        uint sc_res1ab;
+        uint sc_pdmcr;
+        char res3[192];
+} sysconf5xx_t;
+
+
+/* Memory Controller Registers.
+*/
+typedef struct	mem_ctlr {
+        uint memc_br0;
+        uint memc_or0;
+        uint memc_br1;
+        uint memc_or1;
+        uint memc_br2;
+        uint memc_or2;
+        uint memc_br3;
+        uint memc_or3;
+        char res1[32];
+        uint memc_dmbr;
+        uint memc_dmor; 
+        char res2[48];        
+        ushort memc_mstat;
+        ushort memc_res4a;
+        char res3[132];
+} memctl5xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct	sys_int_timers {
+        ushort sit_tbscr;
+        char res1[2];
+        uint sit_tbref0;
+        uint sit_tbref1;
+        char res2[20];
+        ushort sit_rtcsc;
+        char res3[2];
+        uint sit_rtc;
+        uint sit_rtsec;
+        uint sit_rtcal;
+        char res4[16];
+        ushort sit_piscr;
+        char res5[2];
+        uint sit_pitc;
+        uint sit_pitr;
+        char res6[52];
+} sit5xx_t;
+
+/* Clocks and Reset
+*/
+typedef struct clk_and_reset {
+        uint car_sccr;
+        uint car_plprcr;
+        ushort car_rsr;
+        ushort car_res7a;
+        ushort car_colir;
+        ushort car_res7b;
+        ushort car_vsrmcr;
+        ushort car_res7c;
+        char res1[108];
+
+} car5xx_t;
+
+#define TBSCR_TBE		((ushort)0x0001)
+
+/* System Integration Timer Keys
+*/
+typedef struct sitk {
+        uint sitk_tbscrk;
+        uint sitk_tbref0k;
+        uint sitk_tbref1k;
+        uint sitk_tbk;
+        char res1[16];
+        uint sitk_rtcsck;
+        uint sitk_rtck;
+        uint sitk_rtseck;
+        uint sitk_rtcalk;
+        char res2[16];
+        uint sitk_piscrk;
+        uint sitk_pitck;
+        char res3[56];
+} sitk5xx_t;
+
+/* Clocks and Reset Keys.
+*/
+typedef struct cark {
+	uint	cark_sccrk;
+	uint	cark_plprcrk;
+	uint	cark_rsrk;
+	char	res1[1140];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY	((unsigned int)0x55ccaa33)
+
+/* Flash Configuration
+*/
+typedef struct fl {
+        uint fl_cmfmcr;
+        uint fl_cmftst;
+        uint fl_cmfctl;
+        char res1[52];
+} fl5xx_t;
+
+/* Dpram Control
+*/
+typedef struct dprc {		
+        ushort dprc_dptmcr;
+        ushort dprc_ramtst;
+        ushort dprc_rambar;
+        ushort dprc_misrh;
+        ushort dprc_misrl;
+        ushort dprc_miscnt;
+} dprc5xx_t;
+
+/* Time Processor Unit
+*/
+typedef struct tpu {
+        ushort tpu_tpumcr;
+        ushort tpu_tcr;
+        ushort tpu_dscr;
+        ushort tpu_dssr;
+        ushort tpu_ticr;
+        ushort tpu_cier;
+        ushort tpu_cfsr0;
+        ushort tpu_cfsr1;
+        ushort tpu_cfsr2;
+        ushort tpu_cfsr3;
+        ushort tpu_hsqr0;
+        ushort tpu_hsqr1;
+        ushort tpu_hsrr0;
+        ushort tpu_hsrr1;
+        ushort tpu_cpr0;
+        ushort tpu_cpr1;
+        ushort tpu_cisr;
+        ushort tpu_lr;
+        ushort tpu_sglr;
+        ushort tpu_dcnr;
+        ushort tpu_tpumcr2;
+        ushort tpu_tpumcr3;
+        ushort tpu_isdr;
+        ushort tpu_iscr;
+        char   res1[208];
+        char   tpu[16][16];
+        char   res2[512];
+} tpu5xx_t;
+
+/* QADC
+*/
+typedef struct qadc {
+        ushort qadc_64mcr;
+        ushort qadc_64test;
+        ushort qadc_64int;
+        u_char  qadc_portqa;
+        u_char  qadc_portqb;
+        ushort qadc_ddrqa;
+        ushort qadc_qacr0;
+        ushort qadc_qacr1;
+        ushort qadc_qacr2;
+        ushort qadc_qasr0;
+        ushort qadc_qasr1;
+        char   res1[492];
+       /* command convertion word table */
+        ushort qadc_ccw[64];
+       /* result word table, unsigned right justified */
+        ushort qadc_rjurr[64];
+       /* result word table, signed left justified */
+        ushort qadc_ljsrr[64];
+       /* result word table, unsigned left justified */
+        ushort qadc_ljurr[64];
+} qadc5xx_t;
+
+/* QSMCM
+*/
+typedef struct qsmcm {
+        ushort qsmcm_qsmcr;
+        ushort qsmcm_qtest;
+        ushort qsmcm_qdsci_il;
+        ushort qsmcm_qspi_il;
+        ushort qsmcm_scc1r0;
+        ushort qsmcm_scc1r1;
+        ushort qsmcm_sc1sr;
+        ushort qsmcm_sc1dr;
+        char   res1[2];
+        char   res2[2];
+        ushort qsmcm_portqs;
+        u_char qsmcm_pqspar;
+        u_char qsmcm_ddrqs;
+        ushort qsmcm_spcr0;
+        ushort qsmcm_spcr1;
+        ushort qsmcm_spcr2;
+        u_char qsmcm_spcr3;
+        u_char qsmcm_spsr;
+        ushort qsmcm_scc2r0;
+        ushort qsmcm_scc2r1;
+        ushort qsmcm_sc2sr;
+        ushort qsmcm_sc2dr;
+        ushort qsmcm_qsci1cr;
+        ushort qsmcm_qsci1sr;
+        ushort qsmcm_sctq[16];
+        ushort qsmcm_scrq[16];
+        char   res3[212];
+        ushort qsmcm_recram[32];
+        ushort qsmcm_tranram[32];
+        u_char qsmcm_comdram[32];
+        char   res[3616];
+} qsmcm5xx_t;
+
+
+/* MIOS
+*/
+
+typedef struct mios {
+        ushort mios_mpwmsm0perr;                 /* mpwmsm0 */
+        ushort mios_mpwmsm0pulr;
+        ushort mios_mpwmsm0cntr;
+        ushort mios_mpwmsm0scr;
+        ushort mios_mpwmsm1perr;                 /* mpwmsm1 */
+        ushort mios_mpwmsm1pulr;
+        ushort mios_mpwmsm1cntr;
+        ushort mios_mpwmsm1scr;
+        ushort mios_mpwmsm2perr;                 /* mpwmsm2 */
+        ushort mios_mpwmsm2pulr;
+        ushort mios_mpwmsm2cntr;
+        ushort mios_mpwmsm2scr;
+        ushort mios_mpwmsm3perr;                 /* mpwmsm3 */
+        ushort mios_mpwmsm3pulr;
+        ushort mios_mpwmsm3cntr;
+        ushort mios_mpwmsm3scr;
+        char res1[16];
+        ushort mios_mmcsm6cnt;                   /* mmcsm6 */
+        ushort mios_mmcsm6mlr;
+        ushort mios_mmcsm6scrd, mmcsm6scr;
+        char res2[32];
+        ushort mios_mdasm11ar;                   /* mdasm11 */
+        ushort mios_mdasm11br;
+        ushort mios_mdasm11scrd, mdasm11scr;
+        ushort mios_mdasm12ar;                   /* mdasm12 */
+        ushort mios_mdasm12br;
+        ushort mios_mdasm12scrd, mdasm12scr;
+        ushort mios_mdasm13ar;                   /* mdasm13 */
+        ushort mios_mdasm13br;
+        ushort mios_mdasm13scrd, mdasm13scr;
+        ushort mios_mdasm14ar;                   /* mdasm14 */
+        ushort mios_mdasm14br;
+        ushort mios_mdasm14scrd, mdasm14scr;
+        ushort mios_mdasm15ar;                   /* mdasm15 */
+        ushort mios_mdasm15br;
+        ushort mios_mdasm15scrd, mdasm15scr;
+        ushort mios_mpwmsm16perr;                /* mpwmsm16 */
+        ushort mios_mpwmsm16pulr;
+        ushort mios_mpwmsm16cntr;
+        ushort mios_mpwmsm16scr;
+        ushort mios_mpwmsm17perr;                /* mpwmsm17 */
+        ushort mios_mpwmsm17pulr;
+        ushort mios_mpwmsm17cntr;
+        ushort mios_mpwmsm17scr;
+        ushort mios_mpwmsm18perr;                /* mpwmsm18 */
+        ushort mios_mpwmsm18pulr;
+        ushort mios_mpwmsm18cntr;
+        ushort mios_mpwmsm18scr;
+        ushort mios_mpwmsm19perr;                /* mpwmsm19 */
+        ushort mios_mpwmsm19pulr;
+        ushort mios_mpwmsm19cntr;
+        ushort mios_mpwmsm19scr;
+        char res3[16];
+        ushort mios_mmcsm22cnt;                  /* mmcsm22 */
+        ushort mios_mmcsm22mlr;
+        ushort mios_mmcsm22scrd, mmcsm22scr;
+        char res4[32];
+        ushort mios_mdasm27ar;                   /* mdasm27 */
+        ushort mios_mdasm27br;
+        ushort mios_mdasm27scrd, mdasm27scr;
+        ushort mios_mdasm28ar;                   /*mdasm28 */
+        ushort mios_mdasm28br;
+        ushort mios_mdasm28scrd, mdasm28scr;
+        ushort mios_mdasm29ar;                   /* mdasm29 */
+        ushort mios_mdasm29br;
+        ushort mios_mdasm29scrd, mdasm29scr;
+        ushort mios_mdasm30ar;                   /* mdasm30 */
+        ushort mios_mdasm30br;
+        ushort mios_mdasm30scrd, mdasm30scr;
+        ushort mios_mdasm31ar;                   /* mdasm31 */
+        ushort mios_mdasm31br;
+        ushort mios_mdasm31scrd, mdasm31scr;
+        ushort mios_mpiosm32dr;
+        ushort mios_mpiosm32ddr;
+        char res5[1788];
+        ushort mios_mios1tpcr;
+        char mios_res13[2];
+        ushort mios_mios1vnr;
+        ushort mios_mios1mcr;
+        char res6[12];
+        ushort mios_res42z;
+        ushort mios_mcpsmscr;
+        char res7[1000];
+        ushort mios_mios1sr0;
+        char res12[2];
+        ushort mios_mios1er0;
+        ushort mios_mios1rpr0;
+        char res8[40];
+        ushort mios_mios1lvl0;
+        char res9[14];
+        ushort mios_mios1sr1;
+        char res10[2];
+        ushort mios_mios1er1;
+        ushort mios_mios1rpr1;
+        char res11[40];
+        ushort mios_mios1lvl1;
+        char res13[1038];
+} mios5xx_t;
+
+/* Toucan Module
+*/
+typedef struct tcan {
+        ushort tcan_tcnmcr;
+        ushort tcan_cantcr;
+        ushort tcan_canicr;
+        u_char tcan_canctrl0;
+        u_char tcan_canctrl1;
+        u_char tcan_presdiv;
+        u_char tcan_canctrl2;
+        ushort tcan_timer;
+        char res1[4];
+        ushort tcan_rxgmskhi;
+        ushort tcan_rxgmsklo;
+        ushort tcan_rx14mskhi;
+        ushort tcan_rx14msklo;
+        ushort tcan_rx15mskhi;
+        ushort tcan_rx15msklo;
+        char res2[4];
+        ushort tcan_estat;
+        ushort tcan_imask;
+        ushort tcan_iflag;
+        u_char tcan_rxectr;
+        u_char tcan_txectr;
+        char res3[88];
+        struct {
+               ushort scr;
+               ushort id_high;
+               ushort id_low;
+               u_char data[8];
+	           char res4[2];
+	    } tcan_mbuff[16];
+	    char res5[640];
+} tcan5xx_t;
+
+/* UIMB
+*/
+typedef struct uimb {
+        uint uimb_umcr;
+        char res1[12];
+        uint uimb_utstcreg;
+        char res2[12];
+        uint uimb_uipend;
+} uimb5xx_t;
+
+
+
+/* Internal Memory Map MPC555
+*/
+typedef struct immap {
+        char               res1[262144];       	/* CMF Flash A 256 Kbytes */
+        char               res2[196608];       	/* CMF Flash B 192 Kbytes */
+        char               res3[2670592];      	/* Reserved for Flash */
+        sysconf5xx_t       im_siu_conf;        	/* SIU Configuration */
+        memctl5xx_t	   im_memctl;		/* Memory Controller */
+        sit5xx_t           im_sit;		/* System Integration Timers */
+        car5xx_t	   im_clkrst;		/* Clocks and Reset */
+        sitk5xx_t          im_sitk;            	/* System Integration Timer Keys*/
+        cark8xx_t          im_clkrstk;         	/* Clocks and Resert Keys */
+        fl5xx_t	           im_fla;	        /* Flash Module A */
+        fl5xx_t	           im_flb;	        /* Flash Module B */
+        char               res4[14208];        	/* Reserved for SIU */
+        dprc5xx_t	   im_dprc;            	/* Dpram Control Register */
+        char               res5[8180];         	/* Reserved */
+        char               dptram[6144];       	/* Dptram */
+        char               res6[2048];         	/* Reserved */
+        tpu5xx_t	   im_tpua;		/* Time Proessing Unit A */
+        tpu5xx_t	   im_tpub;  	      	/* Time Processing Unit B */
+        qadc5xx_t	   im_qadca;           	/* QADC A */
+        qadc5xx_t	   im_qadcb;           	/* QADC B */
+        qsmcm5xx_t	   im_qsmcm;		/* SCI and SPI */
+        mios5xx_t      	   im_mios;		/* MIOS */
+        tcan5xx_t          im_tcana;           	/* Toucan A */
+        tcan5xx_t          im_tcanb;	       	/* Toucan B */
+        char               res7[1792];         	/* Reserved */
+        uimb5xx_t          im_uimb;	        /* UIMB */
+} immap_t;
+
+#endif /* __IMMAP_5XX__ */
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 78744e28f..5e8f4b577 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -38,7 +38,7 @@ typedef struct bd_info {
 	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
 	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
diff --git a/include/cmd_reginfo.h b/include/cmd_reginfo.h
index d4e995d1a..6a67b36e2 100644
--- a/include/cmd_reginfo.h
+++ b/include/cmd_reginfo.h
@@ -24,7 +24,7 @@
 #ifndef	_CMD_REGINFO_H_
 #define	_CMD_REGINFO_H_
 
-#if (defined(CONFIG_8xx) || defined(CONFIG_405GP)) && \
+#if (defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_405GP)) && \
     (CONFIG_COMMANDS & CFG_CMD_REGINFO)
 #define	CMD_TBL_REGINFO	MK_CMD_TBL_ENTRY(					\
 	"reginfo",	3,	2,	1,	do_reginfo,			\
@@ -35,6 +35,6 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 #else
 #define CMD_TBL_REGINFO
-#endif	/* CONFIG_8xx && CFG_CMD_REGINFO */
+#endif	/* CONFIG_COMMANDS && CFG_CMD_REGINFO */
 
 #endif	/* _CMD_REGINFO_H_ */
diff --git a/include/common.h b/include/common.h
index ac2a57d9a..0d7f79a44 100644
--- a/include/common.h
+++ b/include/common.h
@@ -43,6 +43,8 @@ typedef volatile unsigned char	vu_char;
 #endif
 #ifdef	CONFIG_8xx
 #include <asm/8xx_immap.h>
+#elif defined(CONFIG_5xx)
+#include <asm/5xx_immap.h>
 #elif defined(CONFIG_8260)
 #include <asm/immap_8260.h>
 #endif
@@ -241,7 +243,8 @@ int testdram(void);
 #endif /* CFG_DRAM_TEST */
 
 /* $(CPU)/start.S */
-#ifdef	CONFIG_8xx
+#if defined(CONFIG_5xx)	|| \
+    defined(CONFIG_8xx)
 uint	get_immr      (uint);
 #endif
 uint	get_pvr	      (void);
@@ -370,6 +373,7 @@ ulong	video_setmem (ulong);
 /* ppc/cache.c */
 void	flush_cache   (unsigned long, unsigned long);
 
+
 /* ppc/ticks.S */
 unsigned long long get_ticks(void);
 void	wait_ticks    (unsigned long);
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
new file mode 100644
index 000000000..e8b3eb5d8
--- /dev/null
+++ b/include/configs/cmi_mpc5xx.h
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 
+ */
+
+/*
+ * File:		cmi_mpc5xx.h
+ * 
+ * Discription:		Config header file for cmi 
+ * 			board  using an MPC5xx CPU
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
+#define CONFIG_CMI		1		/* Using the customized cmi board 	*/
+
+/* Serial Console Configuration */
+#define	CONFIG_5xx_CONS_SCI1
+#undef	CONFIG_5xx_CONS_SCI2
+
+#define CONFIG_BAUDRATE		57600
+
+#define CONFIG_COMMANDS		(CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | 		\
+				 CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV |   		\
+				 CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN |	\
+				 CFG_CMD_IMI)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if 0
+#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
+#else
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
+#endif
+#define CONFIG_BOOTCOMMAND	"go 02034004" 	/* autoboot command			*/
+
+#define CONFIG_BOOTARGS		""		/* Assuming OS Image in 4 flash sector at offset 4004 */
+
+#define CONFIG_WATCHDOG				/* turn on platform specific watchdog 	*/
+
+#define CONFIG_STATUS_LED	1		/* Enable status led */ 
+
+#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */
+
+/*
+ * Miscellaneous configurable options 
+ */
+
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	       /* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x000fa000	/* 1 MB in SRAM			*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address		*/
+
+#define	CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
+
+
+/*
+ * Low Level Configuration Settings
+ */
+
+/*
+ * Internal Memory Mapped (This is not the IMMR content)
+ */
+#define CFG_IMMR		0x01000000				/* Physical start adress of internal memory map */
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)      		/* Physical start adress of internal MPC555 writable RAM */       
+#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)       		/* Physical end adress of internal MPC555 used RAM area	*/
+#define	CFG_GBL_DATA_SIZE	64					/* Size in bytes reserved for initial global data */
+#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CFG_INIT_SP_ADDR	0x013fa000				/* Physical start adress of inital stack */
+
+/*
+ * Start addresses for the final memory configuration
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map 			*/
+#define CFG_FLASH_BASE		0x02000000	/* External flash */
+#define PLD_BASE		0x03000000	/* PLD  */
+#define ANYBUS_BASE		0x03010000	/* Anybus Module */
+
+#define CFG_RESET_ADRESS	0x01000000	/* Adress which causes reset */
+#define	CFG_MONITOR_BASE	CFG_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file. 	*/
+						/* This adress is given to the linker with -Ttext to 	*/
+						/* locate the text section at this adress. 		*/
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
+#define	CFG_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization 
+ *-----------------------------------------------------------------------
+ * 
+ */
+
+#define CFG_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors on one chip 	*/
+#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms) 	*/
+#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms) 	*/
+#define CFG_FLASH_PROTECTION    1		/* Physically section protection on	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_OFFSET		0x00020000		/* Environment starts at this adress 	*/
+#define	CFG_ENV_SIZE		0x00010000		/* Set whole sector as env 		*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control			
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWP)		
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+			 SCCR_COM00   | SCCR_DFNL000 | SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration
+ *-----------------------------------------------------------------------
+ * Data show cycle
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle 	*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ *-----------------------------------------------------------------------
+ * Set all bits to 40 Mhz
+ * 
+ */
+#define CFG_OSC_CLK   	((uint)4000000) 	/* Oscillator clock is 4MHz 	*/
+#define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
+	
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ *-----------------------------------------------------------------------
+ * 
+ */
+#define CFG_UMCR	(UMCR_FSPEED) 		/* IMB clock same as U-bus 	*/
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define CFG_ICTRL	(ICTRL_ISCT_SER_7) 	/* Take out of serialized mode 	*/ 
+
+/*-----------------------------------------------------------------------
+ * USIU - Memory Controller Register
+ *----------------------------------------------------------------------- 
+ */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)		
+#define CFG_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
+#define CFG_BR1_PRELIM		(ANYBUS_BASE)
+#define CFG_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
+#define CFG_BR2_PRELIM		(CFG_SDRAM_BASE | BR_V | BR_PS_32)
+#define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
+#define CFG_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
+#define CFG_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
+			 	 OR_ACS_10 | OR_ETHR | OR_CSNT)
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
+
+/*-----------------------------------------------------------------------
+ * DER - Timer Decrementer 
+ *-----------------------------------------------------------------------
+ * Initialise to zero
+ */
+#define CFG_DER			0x00000000
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01			/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02			/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
new file mode 100644
index 000000000..8541ef6f7
--- /dev/null
+++ b/include/mpc5xx.h
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * File:		mpc5xx.h
+ * 
+ * Discription:		mpc5xx specific definitions
+ *
+ */
+
+#ifndef __MPC5XX_H__
+#define __MPC5XX_H__
+
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+
+/*-----------------------------------------------------------------------
+ * ISB bit in IMMR to set internal memory map
+ */
+
+#define CFG_ISB			((CFG_IMMR / 0x00400000) << 1)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register
+ */
+#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count	*/
+#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing			*/
+#define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
+#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
+#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
+#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
+#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register
+ */
+#define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
+#define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
+#define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
+#define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
+#define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
+#define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
+#define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
+#define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
+#define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
+#define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
+#define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
+#define SIUMCR_DBGC01	0x00200000	/* - " -				*/
+#define SIUMCR_DBGC10	0x00400000	/* - " -				*/
+#define SIUMCR_DBGC11	0x00600000	/* - " -				*/
+#define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
+#define SIUMCR_DBPC01	0x00080000	/* - " -				*/
+#define SIUMCR_DBPC10	0x00100000	/* - " -				*/
+#define SIUMCR_DBPC11	0x00180000	/* - " -				*/
+#define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
+#define SIUMCR_SC00	0x00000000	/* Multi Chip 32 bit			*/
+#define SIUMCR_SC01	0x00004000	/* Muilt Chip 16 bit			*/
+#define SIUMCR_SC10	0x00004000	/* Single adress show			*/
+#define SIUMCR_SC11	0x00006000	/* Single adress			*/
+#define SIUMCR_RCTX	0x00001000	/* Data Parity pins Config.		*/
+#define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
+#define SIUMCR_MLRC01	0x00000400	/* - " -				*/
+#define SIUMCR_MLRC10	0x00000800	/* - " -				*/
+#define SIUMCR_MLRC11	0x00000c00	/* - " -				*/
+#define SIUMCR_MTSC	0x00000100	/* Memory transfer      		*/
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control Register		
+ */
+#define TBSCR_REFA	((ushort)0x0080)	/* Reference Interrupt Status A	*/
+#define TBSCR_REFB	((ushort)0x0040)	/* Reference Interrupt Status B */
+#define TBSCR_TBF	((ushort)0x0002)	/* Time Base stops while FREEZE */
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register
+ */
+#define PISCR_PITF	((ushort)0x0002)	/* PIT stops when FREEZE	*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ */
+#define PLPRCR_MF_MSK	0xfff00000	/* MF mask				*/
+#define PLPRCR_DIVF_MSK	0x0000001f	/* DIVF mask				*/
+#define PLPRCR_CSRC_MSK 0x00000400	/* CSRC mask				*/
+#define PLPRCR_MF_SHIFT 0x00000014	/* Multiplication factor shift value	*/
+#define PLPRCR_DIVF_0   0x00900000	/* Division factor 0			*/
+#define PLPRCR_MF_9     0x00000000	/* Mulitipliaction factor 9		*/
+#define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
+#define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status		*/
+#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register	
+ */
+#define SCCR_DFNL_MSK	0x00000070	/* DFNL mask				*/
+#define SCCR_DFNH_MSK	0x00000007  	/* DFNH mask				*/
+#define SCCR_DFNL_SHIFT 0x0000004	/* DFNL shift value			*/
+#define SCCR_RTSEL	0x00100000	/* RTC circuit input source select	*/
+#define SCCR_EBDF00	0x00000000	/* Division factor 1. CLKOUT is GCLK2   */		
+#define SCCR_EBDF11	0x00060000	/* reserved				*/
+#define SCCR_TBS	0x02000000	/* Time Base Source			*/
+#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide 			*/
+#define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
+#define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
+#define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
+
+/*-----------------------------------------------------------------------
+ * MC - Memory Controller
+ */
+#define BR_V		0x00000001	/* Bank valid 				*/
+#define BR_BI		0x00000002	/* Burst inhibit 			*/
+#define BR_PS_8		0x00000400	/* 8 bit port size 			*/
+#define BR_PS_16	0x00000800	/* 16 bit port size 			*/
+#define BR_PS_32	0x00000000	/* 32 bit port size 			*/
+#define BR_LBDIR	0x00000008	/* Late burst data in progess		*/
+#define OR_SCY_3	0x00000030	/* 3 clock cycles wait states		*/
+#define OR_SCY_1	0x00000000	/* 1 clock cycle wait state		*/
+#define OR_SCY_8	0x00000080	/* 8 clock cycles wait states		*/
+#define OR_TRLX		0x00000001	/* Timing relaxed			*/
+#define OR_BSCY		0x00000060	/* Burst beats length in clocks		*/
+#define OR_ACS_10	0x00000600	/* Adress to chip-select setup		*/
+#define OR_CSNT		0x00000800	/* Chip-select negotation time		*/
+#define OR_ETHR		0x00000000	/* Extended hold time on read		*/
+#define OR_ADDR_MK_FF	0xFF000000
+#define OR_ADDR_MK_FFFF	0xFFFF0000
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ */
+#define UMCR_FSPEED 	0x00000000	/* Full speed. Opposit of UMCR_HSPEED	*/
+#define UMCR_HSPEED 	0x10000000	/* Half speed				*/
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define ICTRL_ISCT_SER_7 0x00000007	/* All indirect change of flow		*/
+
+
+#define NR_IRQS		0		/* Place this later in a separate file */
+
+/*-----------------------------------------------------------------------
+ * SCI - Serial communication interface
+ */
+
+#define SCI_TDRE	0x0100		/* Transmit data register empty 	*/
+#define SCI_TE		0x0008		/* Transmitter enabled 			*/
+#define SCI_RE		0x0004		/* Receiver enabled			*/
+#define SCI_RDRF	0x0040		/* Receive data register full 		*/
+#define SCI_PE		0x0400		/* Parity enable 			*/
+#define SCI_SCXBR_MK	0x1fff		/* Baudrate mask 			*/
+#define SCI_SCXDR_MK	0x00ff		/* Data register mask 			*/
+#define SCI_M_11	0x0200		/* Frame size is 11 bit			*/
+#define SCI_M_10	0x0000		/* Frame size is 10 bit			*/
+#define SCI_PORT_1	((int)1)	/* Place this later somewhere better 	*/
+#define SCI_PORT_2	((int)2)
+
+#endif	/* __MPC5XX_H__ */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 931950967..f99d7b2fb 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -110,6 +110,18 @@
 
 #endif	/* CONFIG_8xx, CONFIG_MPC824X */
 
+
+#if  defined(CONFIG_5xx)
+/* Some special purpose registers */
+#define DER	149		/* Debug Enable Register	    	*/
+#define COUNTA	150		/* Breakpoint Counter	    	 	*/
+#define COUNTB	151		/* Breakpoint Counter	    	 	*/
+#define LCTRL1	156		/* Load/Store Support	    	 	*/
+#define LCTRL2	157		/* Load/Store Support	    	 	*/
+#define ICTRL	158		/* I-Bus Support Control Register	*/
+#define EID	81
+#endif	/* CONFIG_5xx */
+
 #if defined(CONFIG_8xx)
 
 /* Registers in the processor's internal memory map that we use.
diff --git a/include/status_led.h b/include/status_led.h
index 79d9fb475..773573d47 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -253,6 +253,19 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
 
 
+/*****  CMI   ********************************************************/
+#elif defined(CONFIG_CMI)
+# define STATUS_LED_DIR		im_mios.mios_mpiosm32ddr 
+# define STATUS_LED_DAT		im_mios.mios_mpiosm32dr 
+
+# define STATUS_LED_BIT		0x2000		/* Select one of the 16 possible*/
+						/* MIOS outputs */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)	/* Blinking periode is 500 ms */
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 0	*/
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
 /*****  KUP4K  ********************************************************/
 #elif defined(CONFIG_KUP4K)
 
diff --git a/include/watchdog.h b/include/watchdog.h
index 6a64409e5..dc26e6ad0 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -75,6 +75,11 @@
 	void reset_8xx_watchdog(volatile immap_t *immr);
 #endif
 
+/* MPC 5xx */
+#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__)
+	void reset_5xx_watchdog(volatile immap_t *immr);
+#endif
+
 /* IBM 4xx */
 #if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
 	void reset_4xx_watchdog(void);