ppc4xx: Replace 4xx lowercase SPR references

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>

3 files changed, 46 insertions, 148 deletions

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 65546adbc..2c0c0cee4 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -96,6 +96,10 @@
 #define CONFIG_BOOKE
 #endif
 
+#define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
+#ifdef CONFIG_BOOKE
+#define SPRN_CCR1	0x378	/* Core Configuration Register for 440 only */
+#endif
 #define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
 #define SPRN_CTR	0x009	/* Count Register */
 #define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
@@ -166,6 +170,9 @@
 #define SPRN_DBSR	0x3F0	/* Debug Status Register */
 #else
 #define SPRN_DBCR1	0x135		/* Book E Debug Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define	SPRN_DBDR	0x3f3		/* Debug Data Register */
+#endif
 #define SPRN_DBSR	0x130		/* Book E Debug Status Register */
 #define   DBSR_IC	    0x08000000	/* Book E Instruction Completion  */
 #define   DBSR_TIE	    0x01000000	/* Book E Trap Instruction Event */
@@ -173,6 +180,10 @@
 #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
 #define   DCCR_NOCACHE		0	/* Noncacheable */
 #define   DCCR_CACHE		1	/* Cacheable */
+#ifndef CONFIG_BOOKE
+#define	SPRN_DCDBTRL	0x39c	/* Data Cache Debug Tag Register Low */
+#define	SPRN_DCDBTRH	0x39d	/* Data Cache Debug Tag Register High */
+#endif
 #define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
 #define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
 #define   DCWR_COPY		0	/* Copy-back */
@@ -184,7 +195,20 @@
 #endif /* CONFIG_BOOKE */
 #define SPRN_DEC	0x016	/* Decrement Register */
 #define SPRN_DMISS	0x3D0	/* Data TLB Miss Register */
+#ifdef CONFIG_BOOKE
+#define	SPRN_DNV0	0x390	/* Data Cache Normal Victim 0 */
+#define	SPRN_DNV1	0x391	/* Data Cache Normal Victim 1 */
+#define	SPRN_DNV2	0x392	/* Data Cache Normal Victim 2 */
+#define	SPRN_DNV3	0x393	/* Data Cache Normal Victim 3 */
+#endif
 #define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
+#ifdef CONFIG_BOOKE
+#define	SPRN_DTV0	0x394	/* Data Cache Transient Victim 0 */
+#define	SPRN_DTV1	0x395	/* Data Cache Transient Victim 1 */
+#define	SPRN_DTV2	0x396	/* Data Cache Transient Victim 2 */
+#define	SPRN_DTV3	0x397	/* Data Cache Transient Victim 3 */
+#define	SPRN_DVLIM	0x398	/* Data Cache Victim Limit */
+#endif
 #define SPRN_EAR	0x11A	/* External Address Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
@@ -269,16 +293,34 @@
 #define   ICCR_NOCACHE		0	/* Noncacheable */
 #define   ICCR_CACHE		1	/* Cacheable */
 #define SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_ICDBTRL	0x39e	/* instruction cache debug tag register low */
+#define	SPRN_ICDBTRH	0x39f	/* instruction cache debug tag register high */
+#endif
 #define SPRN_ICMP	0x3D5	/* Instruction TLB Compare Register */
 #define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
 #define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
 #define SPRN_IMMR	0x27E	/* Internal Memory Map Register */
+#ifdef CONFIG_BOOKE
+#define	SPRN_INV0	0x370	/* Instruction Cache Normal Victim 0 */
+#define	SPRN_INV1	0x371	/* Instruction Cache Normal Victim 1 */
+#define	SPRN_INV2	0x372	/* Instruction Cache Normal Victim 2 */
+#define	SPRN_INV3	0x373	/* Instruction Cache Normal Victim 3 */
+#define	SPRN_ITV0	0x374	/* Instruction Cache Transient Victim 0 */
+#define	SPRN_ITV1	0x375	/* Instruction Cache Transient Victim 1 */
+#define	SPRN_ITV2	0x376	/* Instruction Cache Transient Victim 2 */
+#define	SPRN_ITV3	0x377	/* Instruction Cache Transient Victim 3 */
+#define	SPRN_IVLIM	0x399	/* Instruction Cache Victim Limit */
+#endif
 #define SPRN_LDSTCR	0x3F8	/* Load/Store Control Register */
 #define SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */
 #define SPRN_LR		0x008	/* Link Register */
 #define SPRN_MBAR	0x137	/* System memory base address */
 #define SPRN_MMCR0	0x3B8	/* Monitor Mode Control Register 0 */
 #define SPRN_MMCR1	0x3BC	/* Monitor Mode Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define	SPRN_MMUCR	0x3b2	/* MMU Control Register */
+#endif
 #define SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */
 #define SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */
 #define SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */
@@ -297,6 +339,9 @@
 #define SPRN_PMC4	0x3BE	/* Performance Counter Register 4 */
 #define SPRN_PVR	0x11F	/* Processor Version Register */
 #define SPRN_RPA	0x3D6	/* Required Physical Address Register */
+#ifdef CONFIG_BOOKE
+#define	SPRN_RSTCFG	0x39b	/* Reset Configuration */
+#endif
 #define SPRN_SDA	0x3BF	/* Sampled Data Address Register */
 #define SPRN_SDR1	0x019	/* MMU Hash Base Register */
 #define SPRN_SGR	0x3B9	/* Storage Guarded Register */
@@ -315,6 +360,7 @@
 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
 #define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
 #define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
+
 #ifdef CONFIG_BOOKE
 #define SPRN_SVR	0x3FF	/* System Version Register */
 #else
diff --git a/include/ppc405.h b/include/ppc405.h
index 917afecfa..a17dd3595 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -32,61 +32,6 @@
 #define CONFIG_SYS_DCACHE_SIZE		(2 << 10)	/* For PLX IOP480 (403)	*/
 #endif
 
-/*--------------------------------------------------------------------- */
-/* Special Purpose Registers						*/
-/*--------------------------------------------------------------------- */
-	#define  srr2  0x3de	  /* save/restore register 2 */
-	#define  srr3  0x3df	  /* save/restore register 3 */
-
-	/*
-	 * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
-	 * exception for the exact same purposes - let's alias them and have a
-	 * common handling in crit_return() and CRIT_EXCEPTION
-	 */
-	#define  csrr0 srr2
-	#define  csrr1 srr3
-
-	#define  dbsr  0x3f0	  /* debug status register */
-	#define  dbcr0 0x3f2	  /* debug control register 0 */
-	#define  dbcr1 0x3bd	  /* debug control register 1 */
-	#define  iac1  0x3f4	  /* instruction address comparator 1 */
-	#define  iac2  0x3f5	  /* instruction address comparator 2 */
-	#define  iac3  0x3b4	  /* instruction address comparator 3 */
-	#define  iac4  0x3b5	  /* instruction address comparator 4 */
-	#define  dac1  0x3f6	  /* data address comparator 1 */
-	#define  dac2  0x3f7	  /* data address comparator 2 */
-	#define  dccr  0x3fa	  /* data cache control register */
-	#define  iccr  0x3fb	  /* instruction cache control register */
-	#define  esr   0x3d4	  /* execption syndrome register */
-	#define  dear  0x3d5	  /* data exeption address register */
-	#define  evpr  0x3d6	  /* exeption vector prefix register */
-	#define  tsr   0x3d8	  /* timer status register */
-	#define  tcr   0x3da	  /* timer control register */
-	#define  pit   0x3db	  /* programmable interval timer */
-	#define  sgr   0x3b9	  /* storage guarded reg      */
-	#define  dcwr  0x3ba	  /* data cache write-thru reg*/
-	#define  sler  0x3bb	  /* storage little-endian reg */
-	#define  cdbcr 0x3d7	  /* cache debug cntrl reg    */
-	#define  icdbdr 0x3d3	  /* instr cache dbug data reg*/
-	#define  ccr0  0x3b3	  /* core configuration register */
-	#define  dvc1  0x3b6	  /* data value compare register 1 */
-	#define  dvc2  0x3b7	  /* data value compare register 2 */
-	#define  pid   0x3b1	  /* process ID */
-	#define  su0r  0x3bc	  /* storage user-defined register 0 */
-	#define  zpr   0x3b0	  /* zone protection regsiter */
-
-	#define  tbl   0x11c	  /* time base lower - privileged write */
-	#define  tbu   0x11d	  /* time base upper - privileged write */
-
-	#define  sprg4r 0x104	  /* Special purpose general 4 - read only */
-	#define  sprg5r 0x105	  /* Special purpose general 5 - read only */
-	#define  sprg6r 0x106	  /* Special purpose general 6 - read only */
-	#define  sprg7r 0x107	  /* Special purpose general 7 - read only */
-	#define  sprg4w 0x114	  /* Special purpose general 4 - write only */
-	#define  sprg5w 0x115	  /* Special purpose general 5 - write only */
-	#define  sprg6w 0x116	  /* Special purpose general 6 - write only */
-	#define  sprg7w 0x117	  /* Special purpose general 7 - write only */
-
 /******************************************************************************
  * Special for PPC405GP
  ******************************************************************************/
diff --git a/include/ppc440.h b/include/ppc440.h
index 01f6eaf35..6ce53a6ef 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -48,99 +48,6 @@
 
 #define CONFIG_SYS_DCACHE_SIZE		(32 << 10)	/* For AMCC 440 CPUs	*/
 
-/*--------------------------------------------------------------------- */
-/* Special Purpose Registers						*/
-/*--------------------------------------------------------------------- */
-#define	 xer_reg 0x001
-#define	 lr_reg	0x008
-#define	 dec	0x016	/* decrementer */
-#define	 srr0	0x01a	/* save/restore register 0 */
-#define	 srr1	0x01b	/* save/restore register 1 */
-#define	 pid	0x030	/* process id */
-#define	 decar	0x036	/* decrementer auto-reload */
-#define	 csrr0	0x03a	/* critical save/restore register 0 */
-#define	 csrr1	0x03b	/* critical save/restore register 1 */
-#define	 dear	0x03d	/* data exception address register */
-#define	 esr	0x03e	/* exception syndrome register */
-#define	 ivpr	0x03f	/* interrupt prefix register */
-#define	 usprg0 0x100	/* user special purpose register general 0 */
-#define	 usprg1 0x110	/* user special purpose register general 1 */
-#define	 tblr	0x10c	/* time base lower, read only */
-#define	 tbur	0x10d	/* time base upper, read only */
-#define	 sprg1	0x111	/* special purpose register general 1 */
-#define	 sprg2	0x112	/* special purpose register general 2 */
-#define	 sprg3	0x113	/* special purpose register general 3 */
-#define	 sprg4	0x114	/* special purpose register general 4 */
-#define	 sprg5	0x115	/* special purpose register general 5 */
-#define	 sprg6	0x116	/* special purpose register general 6 */
-#define	 sprg7	0x117	/* special purpose register general 7 */
-#define	 tbl	0x11c	/* time base lower (supervisor)*/
-#define	 tbu	0x11d	/* time base upper (supervisor)*/
-#define	 pir	0x11e	/* processor id register */
-#define	 dbsr	0x130	/* debug status register */
-#define	 dbcr0	0x134	/* debug control register 0 */
-#define	 dbcr1	0x135	/* debug control register 1 */
-#define	 dbcr2	0x136	/* debug control register 2 */
-#define	 iac1	0x138	/* instruction address compare 1 */
-#define	 iac2	0x139	/* instruction address compare 2 */
-#define	 iac3	0x13a	/* instruction address compare 3 */
-#define	 iac4	0x13b	/* instruction address compare 4 */
-#define	 dac1	0x13c	/* data address compare 1 */
-#define	 dac2	0x13d	/* data address compare 2 */
-#define	 dvc1	0x13e	/* data value compare 1 */
-#define	 dvc2	0x13f	/* data value compare 2 */
-#define	 tsr	0x150	/* timer status register */
-#define	 tcr	0x154	/* timer control register */
-#define	 ivor0	0x190	/* interrupt vector offset register 0 */
-#define	 ivor1	0x191	/* interrupt vector offset register 1 */
-#define	 ivor2	0x192	/* interrupt vector offset register 2 */
-#define	 ivor3	0x193	/* interrupt vector offset register 3 */
-#define	 ivor4	0x194	/* interrupt vector offset register 4 */
-#define	 ivor5	0x195	/* interrupt vector offset register 5 */
-#define	 ivor6	0x196	/* interrupt vector offset register 6 */
-#define	 ivor7	0x197	/* interrupt vector offset register 7 */
-#define	 ivor8	0x198	/* interrupt vector offset register 8 */
-#define	 ivor9	0x199	/* interrupt vector offset register 9 */
-#define	 ivor10 0x19a	/* interrupt vector offset register 10 */
-#define	 ivor11 0x19b	/* interrupt vector offset register 11 */
-#define	 ivor12 0x19c	/* interrupt vector offset register 12 */
-#define	 ivor13 0x19d	/* interrupt vector offset register 13 */
-#define	 ivor14 0x19e	/* interrupt vector offset register 14 */
-#define	 ivor15 0x19f	/* interrupt vector offset register 15 */
-#if defined(CONFIG_440)
-#define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
-#define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
-#define	 mcsr	0x23c	/* machine check status register */
-#endif
-#define	 inv0	0x370	/* instruction cache normal victim 0 */
-#define	 inv1	0x371	/* instruction cache normal victim 1 */
-#define	 inv2	0x372	/* instruction cache normal victim 2 */
-#define	 inv3	0x373	/* instruction cache normal victim 3 */
-#define	 itv0	0x374	/* instruction cache transient victim 0 */
-#define	 itv1	0x375	/* instruction cache transient victim 1 */
-#define	 itv2	0x376	/* instruction cache transient victim 2 */
-#define	 itv3	0x377	/* instruction cache transient victim 3 */
-#define	 dnv0	0x390	/* data cache normal victim 0 */
-#define	 dnv1	0x391	/* data cache normal victim 1 */
-#define	 dnv2	0x392	/* data cache normal victim 2 */
-#define	 dnv3	0x393	/* data cache normal victim 3 */
-#define	 dtv0	0x394	/* data cache transient victim 0 */
-#define	 dtv1	0x395	/* data cache transient victim 1 */
-#define	 dtv2	0x396	/* data cache transient victim 2 */
-#define	 dtv3	0x397	/* data cache transient victim 3 */
-#define	 dvlim	0x398	/* data cache victim limit */
-#define	 ivlim	0x399	/* instruction cache victim limit */
-#define	 rstcfg 0x39b	/* reset configuration */
-#define	 dcdbtrl 0x39c	/* data cache debug tag register low */
-#define	 dcdbtrh 0x39d	/* data cache debug tag register high */
-#define	 icdbtrl 0x39e	/* instruction cache debug tag register low */
-#define	 icdbtrh 0x39f	/* instruction cache debug tag register high */
-#define	 mmucr	0x3b2	/* mmu control register */
-#define	 ccr0	0x3b3	/* core configuration register 0 */
-#define  ccr1	0x378	/* core configuration for 440x5 only */
-#define	 icdbdr 0x3d3	/* instruction cache debug data register */
-#define	 dbdr	0x3f3	/* debug data register */
-
 /******************************************************************************
  * DCRs & Related
  ******************************************************************************/