diff options
| author | wdenk <wdenk> | 2004-04-15 21:31:56 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-04-15 21:31:56 +0000 |
| commit | a6ab4bf978a3d5a52a47bbd259b7eb4c860ebd0c (patch) | |
| tree | 7b9b794995dc1b3251a43fdc94a5190c955a5dd2 /include | |
| parent | 5a8c51cd5ef87195e05cdd9aaf2f1dcc753c9792 (diff) | |
Patches by Pantelis Antoniou, 30 Mar 2004:
Improve and fix various things in the MPC8xx FEC driver:
1. The new 87x and 88x series of processors have two FECs,
and the new driver supports them both.
2. Another change in the 87x/88x series is support for
the RMII (Reduced MII) interface. However numerous
changes are needed to make it work since the PHYs
are connected to the same lines. That means that
you have to address them correctly over the MII
interface.
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/8xx_immap.h | 6 | ||||
| -rw-r--r-- | include/mpc8xx.h | 6 |
2 files changed, 11 insertions, 1 deletions
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h index 469edb34f..2288115a6 100644 --- a/include/asm-ppc/8xx_immap.h +++ b/include/asm-ppc/8xx_immap.h @@ -473,7 +473,11 @@ typedef struct comm_proc { union fec_lcd fl_un; #define cp_fec fl_un.fl_un_fec #define lcd_cmap fl_un.fl_un_cmap - char res18[0x1000]; + char res18[0xE00]; + + /* The DUET family has a second FEC here */ + fec_t cp_fec2; +#define cp_fec1 cp_fec /* consistency macro */ /* Dual Ported RAM follows. * There are many different formats for this memory area diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 3976125bf..29117589b 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -208,6 +208,12 @@ #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ +#define SCCR_DFNL001 0x00000100 /* Division by 4 */ +#define SCCR_DFNL010 0x00000200 /* Division by 8 */ +#define SCCR_DFNL011 0x00000300 /* Division by 16 */ +#define SCCR_DFNL100 0x00000400 /* Division by 32 */ +#define SCCR_DFNL101 0x00000500 /* Division by 64 */ +#define SCCR_DFNL110 0x00000600 /* Division by 128 */ #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ |