* Patch by Eran Liberty

  Add support for the Freescale MPC8349ADS board.

10 files changed, 2364 insertions, 5 deletions

diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
new file mode 100644
index 000000000..3096a26a1
--- /dev/null
+++ b/include/asm-ppc/e300.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ * Liberty Eran (liberty@freescale.com)
+ */
+
+#ifndef	__E300_H__
+#define __E300_H__
+
+/*
+ * e300 Processor Version & Revision Numbers 
+ */
+#define PVR_83xx 0x80830000
+#define PVR_8349_REV10 (PVR_83xx | 0x0010)
+#define PVR_8349_REV11 (PVR_83xx | 0x0011)
+
+/*
+ * Hardware Implementation-Dependent Register 0 (HID0)
+ */
+ 
+/* #define HID0 1008 already defined in processor.h */
+#define HID0_MASK_MACHINE_CHECK              0x00000000
+#define HID0_ENABLE_MACHINE_CHECK            0x80000000
+
+#define HID0_DISABLE_CACHE_PARITY            0x00000000
+#define HID0_ENABLE_CACHE_PARITY             0x40000000
+
+#define HID0_DISABLE_ADDRESS_PARITY          0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY           0x20000000
+
+#define HID0_DISABLE_DATA_PARITY             0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY              0x10000000
+
+#define HID0_CORE_CLK_OUT                    0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2              0x08000000
+
+#define HID0_ENABLE_ARTRY_OUT_PRECHARGE      0x00000000 /* on mpc8349ads must be enabled */
+#define HID0_DISABLE_ARTRY_OUT_PRECHARGE     0x01000000
+
+#define HID0_DISABLE_DOSE_MODE               0x00000000
+#define HID0_ENABLE_DOSE_MODE                0x00800000
+
+#define HID0_DISABLE_NAP_MODE                0x00000000
+#define HID0_ENABLE_NAP_MODE                 0x00400000
+
+#define HID0_DISABLE_SLEEP_MODE              0x00000000
+#define HID0_ENABLE_SLEEP_MODE               0x00200000
+
+#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
+#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT  0x00100000
+
+#define HID0_SOFT_RESET                      0x00010000
+
+#define HID0_DISABLE_INSTRUCTION_CACHE       0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE        0x00008000
+
+#define HID0_DISABLE_DATA_CACHE              0x00000000
+#define HID0_ENABLE_DATA_CACHE               0x00004000
+
+#define HID0_LOCK_INSTRUCTION_CACHE          0x00002000
+
+#define HID0_LOCK_DATA_CACHE                 0x00001000
+
+#define HID0_INVALIDATE_INSTRUCTION_CACHE    0x00000800
+
+#define HID0_INVALIDATE_DATA_CACHE           0x00000400
+
+#define HID0_DISABLE_M_BIT                   0x00000000
+#define HID0_ENABLE_M_BIT                    0x00000080
+
+#define HID0_FBIOB                           0x00000010
+
+#define HID0_DISABLE_ADDRESS_BROADCAST       0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST        0x00000008
+
+#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION  0x00000000
+#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
+
+/*
+ * Hardware Implementation-Dependent Register 2 (HID2)
+ */
+#define HID2		1011
+
+#define HID2_LET       0x08000000
+#define HID2_HBE       0x00040000
+#define HID2_IWLCK_000 0x00000000 /* no ways locked */
+#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
+#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
+#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
+#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
+#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
+#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
+
+
+/* BAT (block address translation */
+#define BATU_BEPI_MSK	    0xfffe0000
+#define BATU_BL_MSK         0x00001ffc
+
+#define BATU_BL_128K        0x00000000
+#define BATU_BL_256K        0x00000004
+#define BATU_BL_512K        0x0000000c
+#define BATU_BL_1M          0x0000001c
+#define BATU_BL_2M          0x0000003c
+#define BATU_BL_4M          0x0000007c
+#define BATU_BL_8M          0x000000fc
+#define BATU_BL_16M         0x000001fc
+#define BATU_BL_32M         0x000003fc
+#define BATU_BL_64M         0x000007fc
+#define BATU_BL_128M        0x00000ffc
+#define BATU_BL_256M        0x00001ffc
+
+#define BATU_VS             0x00000002
+#define BATU_VP             0x00000001
+
+#define BATL_BRPN_MSK       0xfffe0000
+#define BATL_WIMG_MSK       0x00000078
+
+#define BATL_WRITETHROUGH   0x00000040
+#define BATL_CACHEINHIBIT   0x00000020
+#define BATL_MEMCOHERENCE   0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+
+#define BATL_PP_MSK         0x00000003
+#define BATL_PP_00          0x00000000 /* No access */
+#define BATL_PP_01          0x00000001 /* Read-only */
+#define BATL_PP_10          0x00000002 /* Read-write */
+#define BATL_PP_11        	0x00000003
+
+#endif	/* __E300_H__ */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 2b57a8bf1..9681a74b5 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -23,6 +23,9 @@
 
 #ifndef	__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
+
+#include "asm/types.h"
+
 /*
  * The following data structure is placed in some memory wich is
  * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
@@ -46,6 +49,20 @@ typedef	struct	global_data {
 	unsigned long	scc_clk;
 	unsigned long	brg_clk;
 #endif
+#if defined(CONFIG_MPC83XX)
+	/* There are other clocks in the MPC83XX */
+	u32 csb_clk;
+	u32 tsec1_clk;
+	u32 tsec2_clk;
+	u32 core_clk;
+	u32 usbmph_clk;
+	u32 usbdr_clk;
+	u32 i2c_clk;
+	u32 enc_clk;
+	u32 lbiu_clk;
+	u32 lclk_clk;
+	u32 ddr_clk;
+#endif
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	ipb_clk;
 	unsigned long	pci_clk;
diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h
new file mode 100644
index 000000000..e7ec9aa6b
--- /dev/null
+++ b/include/asm-ppc/i2c.h
@@ -0,0 +1,104 @@
+/*
+ * Freescale I2C Controller
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003, Motorola, Inc.
+ * author: Eran Liberty (liberty@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_I2C_H_
+#define _ASM_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct i2c
+{
+    u8 adr;          /**< I2C slave address              */
+#define I2C_ADR	      0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES   ~(I2C_ADR)
+    u8 res0[3];     
+    u8 fdr;          /**< I2C frequency divider register */
+    
+#define IC2_FDR       0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES   ~(IC2_FDR)
+    u8 res1[3];     
+    u8 cr;           /**< I2C control redister           */
+#define I2C_CR_MEN	  0x80
+#define I2C_CR_MIEN	  0x40
+#define I2C_CR_MSTA   0x20
+#define I2C_CR_MTX    0x10
+#define I2C_CR_TXAK   0x08
+#define I2C_CR_RSTA   0x04
+#define I2C_CR_BCST   0x01
+    u8 res2[3];     
+    u8 sr;           /**< I2C status register            */
+#define I2C_SR_MCF    0x80
+#define I2C_SR_MAAS   0x40
+#define I2C_SR_MBB    0x20
+#define I2C_SR_MAL    0x10
+#define I2C_SR_BCSTM  0x08
+#define I2C_SR_SRW    0x04
+#define I2C_SR_MIF    0x02
+#define I2C_SR_RXAK   0x01
+    u8 res3[3];     
+    u8 dr;           /**< I2C data register              */
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+    u8 res4[3];     
+    u8 dfsrr;        /**< I2C digital filter sampling rate register */
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+    u8 res5[3];
+    u8 res6[0xE8];     
+} i2c_t;
+
+#ifndef CFG_HZ
+#error CFG_HZ is not defined in /include/configs/${BOARD}.h
+#endif
+#define I2C_TIMEOUT (CFG_HZ/4)
+
+#ifndef CFG_IMMRBAR
+#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h
+#endif
+
+#ifndef CFG_I2C_OFFSET
+#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
+#endif
+
+#ifdef CONFIG_MPC8349ADS
+/* 
+ * MPC8349 have two i2c bus 
+ */
+extern i2c_t * mpc8349_i2c;
+#define I2C mpc8349_i2c
+#else
+#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET))
+#endif
+
+#define I2C_READ  1
+#define I2C_WRITE 0
+
+#endif	/* _ASM_I2C_H_ */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
new file mode 100644
index 000000000..e894cda64
--- /dev/null
+++ b/include/asm-ppc/immap_83xx.h
@@ -0,0 +1,1032 @@
+/*
+ * MPC8349 Internal Memory Map
+ * Copyright (c) 2004 Freescale Semiconductor.
+ * Eran Liberty (liberty@freescale.com)
+ * 
+ * based on:
+ * - MPC8260 Internal Memory Map
+ *   Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ * - MPC85xx Internal Memory Map
+ *   Copyright(c) 2002,2003 Motorola Inc.
+ *   Xianghua Xiao (x.xiao@motorola.com)
+ */
+#ifndef __IMMAP_8349__
+#define __IMMAP_8349__
+
+#include <asm/types.h>
+#include <asm/i2c.h>
+
+/* 
+ * Local Access Window.
+ */
+typedef struct law8349 {
+	u32 bar; /* LBIU local access window base address register */
+#define LAWBAR_BAR         0xFFFFF000 /* Identifies the 20 most-significant address bits of the base of local access window n. The specified base address should be aligned to the window size, as defined by LBLAWARn[SIZE]. */
+#define LAWBAR_RES	     ~(LAWBAR_BAR)
+	u32 ar; /* LBIU local access window attribute register */
+/*
+ * This Macro were moved into mmu.h
+ */
+#if 0    
+#define LAWAR_EN           0x80000000 /* 0 The local bus local access window n is disabled. 1 The local bus local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields combine to identify an address range for this window. */
+#define LAWAR_SIZE         0x0000003F /* Identifies the size of the window from the starting address. Window size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is undefined. */
+#define	LAWAR_SIZE_4K	0x0000000B
+#define	LAWAR_SIZE_8K	0x0000000C
+#define	LAWAR_SIZE_16K	0x0000000D
+#define	LAWAR_SIZE_32K	0x0000000E
+#define	LAWAR_SIZE_64K	0x0000000F
+#define	LAWAR_SIZE_128K	0x00000010
+#define	LAWAR_SIZE_256K	0x00000011
+#define	LAWAR_SIZE_512K	0x00000012
+#define	LAWAR_SIZE_1M	0x00000013
+#define	LAWAR_SIZE_2M	0x00000014
+#define	LAWAR_SIZE_4M	0x00000015
+#define	LAWAR_SIZE_8M	0x00000016
+#define	LAWAR_SIZE_16M	0x00000017
+#define	LAWAR_SIZE_32M	0x00000018
+#define	LAWAR_SIZE_64M	0x00000019
+#define	LAWAR_SIZE_128M	0x0000001A
+#define	LAWAR_SIZE_256M	0x0000001B
+#define	LAWAR_SIZE_512M	0x0000001C
+#define	LAWAR_SIZE_1G	0x0000001D
+#define	LAWAR_SIZE_2G	0x0000001E
+#define LAWAR_RES          ~(LAWAR_EN|LAWAR_SIZE)
+#endif
+
+} law8349_t;
+
+/* 
+ * System configuration registers.
+ */
+typedef struct sysconf8349 {
+	u32 immrbar; /* Internal memory map base address register */
+	u8 res0[0x04];
+	u32 altcbar; /* Alternate configuration base address register */
+#define ALTCBAR_BASE_ADDR     0xFFF00000 /* Identifies the12 most significant address bits of an alternate base address used for boot sequencer configuration accesses. */
+#define ALTCBAR_RES           ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
+	u8 res1[0x14];
+	law8349_t lblaw[4]; /* LBIU local access window */
+	u8 res2[0x20];
+	law8349_t pcilaw[2]; /* PCI local access window */
+	u8 res3[0x30];
+	law8349_t ddrlaw[2]; /* DDR local access window */
+	u8 res4[0x50];
+	u32 sgprl; /* System General Purpose Register Low */
+	u32 sgprh; /* System General Purpose Register High */
+	u32 spridr; /* System Part and Revision ID Register */
+#define SPRIDR_PARTID         0xFFFF0000 /* Part Identification. */
+#define SPRIDR_REVID          0x0000FFFF /* Revision Identification. */
+	u8 res5[0x04];
+	u32 spcr; /* System Priority Configuration Register */ 
+#define SPCR_PCIHPE   0x10000000 /* PCI Highest Priority Enable. */
+#define SPCR_PCIPR    0x03000000 /* PCI bridge system bus request priority. */
+#define SPCR_TBEN     0x00400000 /* E300 PowerPC core time base unit enable. */
+#define SPCR_COREPR   0x00300000 /* E300 PowerPC Core system bus request priority. */
+#define SPCR_TSEC1DP  0x00003000 /* TSEC1 data priority. */
+#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
+#define SPCR_TSEC1EP  0x00000300 /* TSEC1 emergency priority. */
+#define SPCR_TSEC2DP  0x00000030 /* TSEC2 data priority. */
+#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
+#define SPCR_TSEC2EP  0x00000003 /* TSEC2 emergency priority. */
+#define SPCR_RES      ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_TBEN|SPCR_COREPR|SPCR_TSEC1DP \
+                       |SPCR_TSEC1BDP|SPCR_TSEC1EP|SPCR_TSEC2DP|SPCR_TSEC2BDP|SPCR_TSEC2EP)
+	u32 sicrl; /* System General Purpose Register Low */
+#define SICRL_LDP_A   0x80000000
+#define SICRL_USB0    0x40000000
+#define SICRL_USB1    0x20000000
+#define SICRL_UART    0x0C000000
+#define SICRL_GPIO1_A 0x02000000
+#define SICRL_GPIO1_B 0x01000000
+#define SICRL_GPIO1_C 0x00800000
+#define SICRL_GPIO1_D 0x00400000
+#define SICRL_GPIO1_E 0x00200000
+#define SICRL_GPIO1_F 0x00180000
+#define SICRL_GPIO1_G 0x00040000
+#define SICRL_GPIO1_H 0x00020000
+#define SICRL_GPIO1_I 0x00010000
+#define SICRL_GPIO1_J 0x00008000
+#define SICRL_GPIO1_K 0x00004000
+#define SICRL_GPIO1_L 0x00003000
+#define SICRL_RES ~(SICRL_LDP_A|SICRL_USB0|SICRL_USB1|SICRL_UART|SICRL_GPIO1_A \
+                    |SICRL_GPIO1_B|SICRL_GPIO1_C|SICRL_GPIO1_D|SICRL_GPIO1_E \
+                    |SICRL_GPIO1_F|SICRL_GPIO1_G|SICRL_GPIO1_H|SICRL_GPIO1_I \
+                    |SICRL_GPIO1_J|SICRL_GPIO1_K|SICRL_GPIO1_L )
+	u32 sicrh; /* System General Purpose Register High */
+#define SICRH_DDR     0x80000000
+#define SICRH_TSEC1_A 0x10000000
+#define SICRH_TSEC1_B 0x08000000
+#define SICRH_TSEC1_C 0x04000000
+#define SICRH_TSEC1_D 0x02000000
+#define SICRH_TSEC1_E 0x01000000
+#define SICRH_TSEC1_F 0x00800000
+#define SICRH_TSEC2_A 0x00400000
+#define SICRH_TSEC2_B 0x00200000
+#define SICRH_TSEC2_C 0x00100000
+#define SICRH_TSEC2_D 0x00080000
+#define SICRH_TSEC2_E 0x00040000
+#define SICRH_TSEC2_F 0x00020000
+#define SICRH_TSEC2_G 0x00010000
+#define SICRH_TSEC2_H 0x00008000
+#define SICRH_GPIO2_A 0x00004000
+#define SICRH_GPIO2_B 0x00002000
+#define SICRH_GPIO2_C 0x00001000
+#define SICRH_GPIO2_D 0x00000800
+#define SICRH_GPIO2_E 0x00000400
+#define SICRH_GPIO2_F 0x00000200
+#define SICRH_GPIO2_G 0x00000180
+#define SICRH_GPIO2_H 0x00000060
+#define SICRH_TSOBI1  0x00000002
+#define SICRH_TSOBI2  0x00000001
+#define SICRh_RES     ~(SICRH_DDR|SICRH_TSEC1_A|SICRH_TSEC1_B|SICRH_TSEC1_C \
+                        |SICRH_TSEC1_D|SICRH_TSEC1_E|SICRH_TSEC1_F|SICRH_TSEC2_A \
+                        |SICRH_TSEC2_B|SICRH_TSEC2_C|SICRH_TSEC2_D|SICRH_TSEC2_E \
+                        |SICRH_TSEC2_F|SICRH_TSEC2_G|SICRH_TSEC2_H|SICRH_GPIO2_A \
+                        |SICRH_GPIO2_B|SICRH_GPIO2_C|SICRH_GPIO2_D|SICRH_GPIO2_E \
+                        |SICRH_GPIO2_F|SICRH_GPIO2_G|SICRH_GPIO2_H|SICRH_TSOBI1  \
+                        |SICRH_TSOBI2)
+	u8 res6[0xE4];
+} sysconf8349_t;
+
+/* 
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt8349 {
+	u8 res0[4]; 
+	u32 swcrr; /* System watchdog control register */
+	u32 swcnr; /* System watchdog count register */
+#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
+#define SWCNR_RES  ~(SWCNR_SWCN)
+	u8 res1[2]; 
+	u16 swsrr; /* System watchdog service register */
+	u8 res2[0xF0];
+} wdt8349_t;
+ 
+/*
+ * RTC/PIT Module Registers
+ */
+typedef struct rtclk8349 {
+	u32 cnr; /* control register */
+#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit  */
+#define CNR_CLIN 0x00000040 /* Input Clock Control Bit  */
+#define CNR_AIM  0x00000002 /* Alarm Interrupt Mask Bit  */
+#define CNR_SIM  0x00000001 /* Second Interrupt Mask Bit  */
+#define CNR_RES  ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
+	u32 ldr; /* load register */
+	u32 psr; /* prescale register */
+	u32 ctr; /* register */ 
+	u32 evr; /* event register */
+#define RTEVR_SIF  0x00000001 /* Second Interrupt Flag Bit  */
+#define RTEVR_AIF  0x00000002 /* Alarm Interrupt Flag Bit  */
+#define RTEVR_RES  ~(EVR_SIF | EVR_AIF)
+	u32 alr; /* alarm register */
+	u8 res0[0xE8];
+} rtclk8349_t;
+
+/*
+ * Global timper module
+ */
+
+typedef struct gtm8349 {
+    u8    cfr1; /* Timer1/2 Configuration  */
+#define CFR1_PCAS 0x80 /* Pair Cascade mode  */
+#define CFR1_BCM  0x40  /* Backward compatible mode  */
+#define CFR1_STP2 0x20 /* Stop timer  */
+#define CFR1_RST2 0x10 /* Reset timer  */
+#define CFR1_GM2  0x08 /* Gate mode for pin 2  */
+#define CFR1_GM1  0x04 /* Gate mode for pin 1  */
+#define CFR1_STP1 0x02 /* Stop timer  */
+#define CFR1_RST1 0x01 /* Reset timer  */
+    u8    res0[3];
+    u8    cfr2; /* Timer3/4 Configuration  */
+#define CFR2_PCAS 0x80 /* Pair Cascade mode  */
+#define CFR2_SCAS 0x40 /* Super Cascade mode  */
+#define CFR2_STP4 0x20 /* Stop timer  */
+#define CFR2_RST4 0x10 /* Reset timer  */
+#define CFR2_GM4  0x08 /* Gate mode for pin 4  */
+#define CFR2_GM3  0x04 /* Gate mode for pin 3  */
+#define CFR2_STP3 0x02 /* Stop timer  */
+#define CFR2_RST3 0x01 /* Reset timer  */
+    u8    res1[10];
+    u16   mdr1; /* Timer1 Mode Register  */
+#define MDR_SPS  0xff00 /* Secondary Prescaler value  */
+#define MDR_CE   0x00c0 /* Capture edge and enable interrupt  */
+#define MDR_OM   0x0020 /* Output mode  */
+#define MDR_ORI  0x0010 /* Output reference interrupt enable  */
+#define MDR_FRR  0x0008 /* Free run/restart  */
+#define MDR_ICLK 0x0006 /* Input clock source for the timer  */
+#define MDR_GE   0x0001 /* Gate enable  */
+    u16   mdr2; /* Timer2 Mode Register  */
+	u16   rfr1; /* Timer1 Reference Register  */
+    u16   rfr2; /* Timer2 Reference Register  */
+    u16   cpr1; /* Timer1 Capture Register  */
+    u16   cpr2; /* Timer2 Capture Register  */
+    u16   cnr1; /* Timer1 Counter Register  */
+    u16   cnr2; /* Timer2 Counter Register  */
+    u16   mdr3; /* Timer3 Mode Register  */
+    u16   mdr4; /* Timer4 Mode Register  */
+    u16   rfr3; /* Timer3 Reference Register  */
+    u16   rfr4; /* Timer4 Reference Register  */
+    u16   cpr3; /* Timer3 Capture Register  */
+    u16   cpr4; /* Timer4 Capture Register  */
+    u16   cnr3; /* Timer3 Counter Register  */
+    u16   cnr4; /* Timer4 Counter Register  */
+    u16   evr1; /* Timer1 Event Register  */
+    u16   evr2; /* Timer2 Event Register  */
+    u16   evr3; /* Timer3 Event Register  */
+    u16   evr4; /* Timer4 Event Register  */
+#define GTEVR_REF 0x0002 /* Output reference event  */
+#define GTEVR_CAP 0x0001 /* Counter Capture event   */
+#define GTEVR_RES ~(EVR_CAP|EVR_REF)
+    u16   psr1; /* Timer1 Prescaler Register  */
+    u16   psr2; /* Timer2 Prescaler Register  */
+    u16   psr3; /* Timer3 Prescaler Register  */
+    u16   psr4; /* Timer4 Prescaler Register  */
+    u8    res[0xC0];
+} gtm8349_t; 
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic8349 {
+    u32    sicfr; /*  System Global Interrupt Configuration Register (SICFR)  */
+#define SICFR_HPI  0x7f000000 /*  Highest Priority Interrupt  */
+#define SICFR_MPSB 0x00400000 /*  Mixed interrupts Priority Scheme for group B  */
+#define SICFR_MPSA 0x00200000 /*  Mixed interrupts Priority Scheme for group A  */
+#define SICFR_IPSD 0x00080000 /*  Internal interrupts Priority Scheme for group D  */
+#define SICFR_IPSA 0x00010000 /*  Internal interrupts Priority Scheme for group A  */
+#define SICFR_HPIT 0x00000300 /*  HPI priority position IPIC output interrupt Type  */
+#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
+    u32    sivcr; /*  System Global Interrupt Vector Register (SIVCR)  */
+#define SICVR_IVECX 0xfc000000 /*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
+#define SICVR_IVEC  0x0000007f /*  Interrupt vector  */
+#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
+    u32    sipnr_h; /*  System Internal Interrupt Pending Register - High (SIPNR_H)  */
+#define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt  */
+#define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt  */
+#define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
+#define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt  */
+#define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt  */
+#define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
+#define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
+#define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt  */
+#define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
+#define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
+#define SIIH_SEC     0x00000020 /*  SEC interrupt  */
+#define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
+#define SIIH_I2C2    0x00000002 /*  I2C1 interrupt  */
+#define SIIH_SPI     0x00000001 /*  SPI interrupt  */
+#define SIIH_RES ~(SIIH_TSEC1TX|SIIH_TSEC1RX|SIIH_TSEC1ER|SIIH_TSEC2TX \
+                    |SIIH_TSEC2RX|SIIH_TSEC2ER|SIIH_USB2DR|SIIH_USB2MPH \
+                    |SIIH_UART1  |SIIH_UART2  |SIIH_SEC   |SIIH_I2C1    \
+                    |SIIH_I2C2   |SIIH_SPI)
+    u32    sipnr_l; /*  System Internal Interrupt Pending Register - Low (SIPNR_L)  */
+#define SIIL_RTCS  0x80000000 /*  RTC SECOND interrupt  */
+#define SIIL_PIT   0x40000000 /*  PIT interrupt  */
+#define SIIL_PCI1  0x20000000 /*  PCI1 interrupt  */
+#define SIIL_PCI2  0x10000000 /*  PCI2 interrupt  */
+#define SIIL_RTCA  0x08000000 /*  RTC ALARM interrupt  */
+#define SIIL_MU    0x04000000 /*  Message Unit interrupt  */
+#define SIIL_SBA   0x02000000 /*  System Bus Arbiter interrupt  */
+#define SIIL_DMA   0x01000000 /*  DMA interrupt  */
+#define SIIL_GTM4  0x00800000 /*  GTM4 interrupt  */
+#define SIIL_GTM8  0x00400000 /*  GTM8 interrupt  */
+#define SIIL_GPIO1 0x00200000 /*  GPIO1 interrupt  */
+#define SIIL_GPIO2 0x00100000 /*  GPIO2 interrupt  */
+#define SIIL_DDR   0x00080000 /*  DDR interrupt  */
+#define SIIL_LBC   0x00040000 /*  LBC interrupt  */
+#define SIIL_GTM2  0x00020000 /*  GTM2 interrupt  */
+#define SIIL_GTM6  0x00010000 /*  GTM6 interrupt  */
+#define SIIL_PMC   0x00008000 /*  PMC interrupt  */
+#define SIIL_GTM3  0x00000800 /*  GTM3 interrupt  */
+#define SIIL_GTM7  0x00000400 /*  GTM7 interrupt  */
+#define SIIL_GTM1  0x00000020 /*  GTM1 interrupt  */
+#define SIIL_GTM5  0x00000010 /*  GTM5 interrupt  */
+#define SIIL_DPTC  0x00000001 /*  DPTC interrupt (!!! Invisible for user !!!)  */
+#define SIIL_RES ~(SIIL_RTCS  |SIIL_PIT  |SIIL_PCI1 |SIIL_PCI2 |SIIL_RTCA \
+                   |SIIL_MU   |SIIL_SBA  |SIIL_DMA  |SIIL_GTM4 |SIIL_GTM8 \
+                   |SIIL_GPIO1|SIIL_GPIO2|SIIL_DDR  |SIIL_LBC  |SIIL_GTM2 \
+                   |SIIL_GTM6 |SIIL_PMC  |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \
+                   |SIIL_GTM5 |SIIL_DPTC )
+    u32    siprr_a; /*  System Internal Interrupt Group A Priority Register (PRR)  */
+    u8     res0[8];
+    u32    siprr_d; /*  System Internal Interrupt Group D Priority Register (PRR)  */
+    u32    simsr_h; /*  System Internal Interrupt Mask Register - High (SIIH)  */
+    u32    simsr_l; /*  System Internal Interrupt Mask Register - Low (SIIL)  */
+    u8     res1[4];
+    u32    sepnr;   /*  System External Interrupt Pending Register (SEI)  */
+    u32    smprr_a; /*  System Mixed Interrupt Group A Priority Register (PRR)  */
+    u32    smprr_b; /*  System Mixed Interrupt Group B Priority Register (PRR)  */
+#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
+#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
+#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
+#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
+#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
+#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
+#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
+#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
+#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
+    u32    semsr; /*  System External Interrupt Mask Register (SEI)  */
+#define SEI_IRQ0  0x80000000 /*  IRQ0 external interrupt  */
+#define SEI_IRQ1  0x40000000 /*  IRQ1 external interrupt  */
+#define SEI_IRQ2  0x20000000 /*  IRQ2 external interrupt  */
+#define SEI_IRQ3  0x10000000 /*  IRQ3 external interrupt  */
+#define SEI_IRQ4  0x08000000 /*  IRQ4 external interrupt  */
+#define SEI_IRQ5  0x04000000 /*  IRQ5 external interrupt  */
+#define SEI_IRQ6  0x02000000 /*  IRQ6 external interrupt  */
+#define SEI_IRQ7  0x01000000 /*  IRQ7 external interrupt  */
+#define SEI_SIRQ0 0x00008000 /*  SIRQ0 external interrupt  */
+#define SEI_RES ~( SEI_IRQ0 |SEI_IRQ1 |SEI_IRQ2 |SEI_IRQ3 |SEI_IRQ4 \
+                  |SEI_IRQ5 |SEI_IRQ6 |SEI_IRQ7 |SEI_SIRQ0)
+    u32    secnr; /*  System External Interrupt Control Register (SECNR)  */
+#define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type  */
+#define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type  */
+#define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type  */
+#define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type  */
+#define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
+#define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
+#define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
+#define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
+#define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
+#define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
+#define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
+#define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
+#define SECNR_RES ~( SECNR_MIXB0T|SECNR_MIXB1T|SECNR_MIXA0T|SECNR_SYSA1T \
+                    |SECNR_EDI0  |SECNR_EDI1  |SECNR_EDI2  |SECNR_EDI3   \
+                    |SECNR_EDI4  |SECNR_EDI5  |SECNR_EDI6  |SECNR_EDI7)
+    u32   sersr; /*  System Error Status Register (SERR)  */
+    u32   sermr; /*  System Error Mask Register (SERR)  */
+#define SERR_IRQ0 0x80000000 /*  IRQ0 MCP request  */
+#define SERR_WDT  0x40000000 /*  WDT MCP request  */
+#define SERR_SBA  0x20000000 /*  SBA MCP request  */
+#define SERR_DDR  0x10000000 /*  DDR MCP request  */
+#define SERR_LBC  0x08000000 /*  LBC MCP request  */
+#define SERR_PCI1 0x04000000 /*  PCI1 MCP request  */
+#define SERR_PCI2 0x02000000 /*  PCI2 MCP request  */
+#define SERR_MU   0x01000000 /*  MU MCP request  */
+#define SERR_RNC  0x00010000 /*  MU MCP request (!!! Non-visible for users !!!)  */
+#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_DDR |SERR_LBC \
+                   |SERR_PCI1|SERR_PCI2|SERR_MU  |SERR_RNC )
+    u32    sercr; /*  System Error Control Register  (SERCR)  */
+#define SERCR_MCPR 0x00000001 /*  MCP Route  */
+#define SERCR_RES ~(SERCR_MCPR)
+    u8    res2[4];
+    u32   sifcr_h; /*  System Internal Interrupt Force Register - High (SIIH)  */
+    u32   sifcr_l; /*  System Internal Interrupt Force Register - Low (SIIL)  */
+    u32   sefcr;   /*  System External Interrupt Force Register (SEI)  */
+    u32   serfr;   /*  System Error Force Register (SERR)  */
+    u8    res3[0xA0];
+} ipic8349_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter8349 {
+	u32 acr; /* Arbiter Configuration Register */
+#define ACR_COREDIS    0x10000000 /* Core disable. */    
+#define ACR_PIPE_DEP   0x00070000 /* Pipeline depth (number of outstanding transactions). */
+#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
+#define ACR_RPTCNT     0x00000700 /* Repeat count. */ 
+#define ACR_APARK      0x00000030 /* Address parking. */
+#define ACR_PARKM	   0x0000000F /* Parking master. */
+#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
+	u32 atr; /* Arbiter Timers Register */
+#define ATR_DTO 0x00FF0000 /* Data time out. */
+#define ATR_ATO	0x000000FF /* Address time out. */
+#define ATR_RES ~(ATR_DTO|ATR_ATO)
+	u8 res[4];
+	u32 aer; /* Arbiter Event Register (AE)*/
+	u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
+	u32 amr; /* Arbiter Mask Register (AE) */
+	u32 aeatr; /* Arbiter Event Attributes Register */
+#define AEATR_EVENT   0x07000000 /* Event type. */
+#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
+#define AEATR_TBST    0x00000800 /* Transfer burst. */
+#define AEATR_TSIZE   0x00000700 /* Transfer Size. */
+#define AEATR_TTYPE	  0x0000001F /* Transfer Type. */
+#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
+	u32 aeadr; /* Arbiter Event Address Register */
+	u32 aerr; /* Arbiter Event Response Register (AE)*/
+#define AE_ETEA 0x00000020 /* Transfer error. */
+#define AE_RES_ 0x00000010 /* Reserved transfer type. */
+#define AE_ECW  0x00000008 /* External control word transfer type. */
+#define AE_AO   0x00000004 /* Address Only transfer type. */
+#define AE_DTO  0x00000002 /* Data time out. */
+#define AE_ATO	0x00000001 /* Address time out. */
+#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
+	u8 res1[0xDC];
+} arbiter8349_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset8349 {
+    u32    rcwl; /* RCWL Register  */
+#define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
+#define RCWL_LBIUCM_SHIFT    31
+#define RCWL_DDRCM   0x40000000 /* DDRCM  */
+#define RCWL_DDRCM_SHIFT     30
+#define RCWL_SVCOD   0x30000000 /* SVCOD  */
+#define RCWL_SPMF    0x0f000000 /* SPMF  */
+#define RCWL_SPMF_SHIFT      24
+#define RCWL_COREPLL 0x007F0000 /* COREPLL  */
+#define RCWL_COREPLL_SHIFT   16
+#define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
+#define RCWL_CEPDF   0x00000020 /* CEPDF  */
+#define RCWL_CEPMF   0x0000001F /* CEPMF  */
+#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)  
+    u32    rcwh; /* RCHL Register  */
+#define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+#define RCWH_PCIHOST_SHIFT   31
+#define RCWH_PCI64   0x40000000 /* PCI64  */
+#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
+#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
+#define RCWH_COREDIS 0x08000000 /* COREDIS  */
+#define RCWH_BMS     0x04000000 /* BMS  */
+#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
+#define RCWH_SWEN    0x00800000 /* SWEN  */
+#define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
+#define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
+#define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
+#define RCWH_TPR     0x00000100 /* TPR  */
+#define RCWH_TLE     0x00000008 /* TLE  */
+#define RCWH_LALE    0x00000004 /* LALE  */
+#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCI64|RCWH_PCI1ARB|RCWH_PCI2ARB \
+                    |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN|RCWH_ROMLOC \
+                    |RCWH_TSEC1M|RCWH_TSEC2M|RCWH_TPR|RCWH_TLE|RCWH_LALE)
+    u8     res0[8];
+    u32    rsr; /* Reset status Register  */
+#define RSR_RSTSRC 0xE0000000 /* Reset source  */
+#define RSR_RSTSRC_SHIFT   29
+#define RSR_BSF    0x00010000 /* Boot seq. fail  */
+#define RSR_BSF_SHIFT      16
+#define RSR_SWSR   0x00002000 /* software soft reset  */
+#define RSR_SWSR_SHIFT     13
+#define RSR_SWHR   0x00001000 /* software hard reset  */
+#define RSR_SWHR_SHIFT     12
+#define RSR_JHRS   0x00000200 /* jtag hreset  */
+#define RSR_JHRS_SHIFT      9
+#define RSR_JSRS   0x00000100 /* jtag sreset status  */
+#define RSR_JSRS_SHIFT      8
+#define RSR_CSHR   0x00000010 /* checkstop reset status  */
+#define RSR_CSHR_SHIFT      4
+#define RSR_SWRS   0x00000008 /* software watchdog reset status  */
+#define RSR_SWRS_SHIFT      3
+#define RSR_BMRS   0x00000004 /* bus monitop reset status  */
+#define RSR_BMRS_SHIFT      2
+#define RSR_SRS    0x00000002 /* soft reset status  */
+#define RSR_SRS_SHIFT       1
+#define RSR_HRS    0x00000001 /* hard reset status  */
+#define RSR_HRS_SHIFT       0
+#define RSR_RES ~(RSR_RSTSRC|RSR_BSF|RSR_SWSR|RSR_SWHR|RSR_JHRS|RSR_JSRS|RSR_CSHR|RSR_SWRS|RSR_BMRS|RSR_SRS|RSR_HRS)
+    u32    rmr; /* Reset mode Register  */
+#define RMR_CSRE   0x00000001 /* checkstop reset enable  */
+#define RMR_CSRE_SHIFT      0
+#define RMR_RES ~(RMR_CSRE)
+    u32    rpr; /* Reset protection Register  */
+    u32    rcr; /* Reset Control Register  */
+#define RCR_SWHR 0x00000002 /* software hard reset  */
+#define RCR_SWSR 0x00000001 /* software soft reset  */
+#define RCR_RES ~(RCR_SWHR|RCR_SWSR)
+    u32    rcer; /* Reset Control Enable Register  */
+#define RCER_CRE 0x00000001 /* software hard reset  */
+#define RCER_RES ~(RCER_CRE)
+	u8     res1[0xDC];
+} reset8349_t;
+ 
+typedef struct clk8349 {
+    u32    spmr; /* system PLL mode Register  */
+#define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
+#define SPMR_DDRCM   0x40000000 /* DDRCM  */
+#define SPMR_SVCOD   0x30000000 /* SVCOD  */
+#define SPMR_SPMF    0x0F000000 /* SPMF  */
+#define SPMR_CKID    0x00800000 /* CKID  */
+#define SPMR_CKID_SHIFT 23 
+#define SPMR_COREPLL 0x007F0000 /* COREPLL  */
+#define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
+#define SPMR_CEPDF   0x00000020 /* CEPDF  */
+#define SPMR_CEPMF   0x0000001F /* CEPMF  */
+#define SPMR_RES ~(SPMR_LBIUCM|SPMR_DDRCM|SPMR_SVCOD|SPMR_SPMF|SPMR_CKID \
+                   |SPMR_COREPLL|SPMR_CEVCOD|SPMR_CEPDF|SPMR_CEPMF)
+    u32    occr; /* output clock control Register  */
+#define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
+#define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
+#define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
+#define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
+#define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
+#define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
+#define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
+#define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
+#define OCCR_PCICD0  0x00800000 /* PCICD0  */
+#define OCCR_PCICD1  0x00400000 /* PCICD1  */
+#define OCCR_PCICD2  0x00200000 /* PCICD2  */
+#define OCCR_PCICD3  0x00100000 /* PCICD3  */
+#define OCCR_PCICD4  0x00080000 /* PCICD4  */
+#define OCCR_PCICD5  0x00040000 /* PCICD5  */
+#define OCCR_PCICD6  0x00020000 /* PCICD6  */
+#define OCCR_PCICD7  0x00010000 /* PCICD7  */
+#define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
+#define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
+#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2|OCCR_PCICOE3|OCCR_PCICOE4 \
+                   |OCCR_PCICOE5|OCCR_PCICOE6|OCCR_PCICOE7|OCCR_PCICD0|OCCR_PCICD1  \
+                   |OCCR_PCICD2 |OCCR_PCICD3 |OCCR_PCICD4 |OCCR_PCICD5|OCCR_PCICD6  \
+                   |OCCR_PCICD7 |OCCR_PCI1CR |OCCR_PCI2CR )
+    u32    sccr; /* system clock control Register  */
+#define SCCR_TSEC1CM  0xc0000000 /* TSEC1CM  */
+#define SCCR_TSEC1CM_SHIFT 30
+#define SCCR_TSEC2CM  0x30000000 /* TSEC2CM  */
+#define SCCR_TSEC2CM_SHIFT 28
+#define SCCR_ENCCM    0x03000000 /* ENCCM  */
+#define SCCR_ENCCM_SHIFT 24
+#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM  */
+#define SCCR_USBMPHCM_SHIFT 22
+#define SCCR_USBDRCM  0x00300000 /* USBDRCM  */
+#define SCCR_USBDRCM_SHIFT 20
+#define SCCR_PCICM    0x00010000 /* PCICM  */
+#define SCCR_RES ~( SCCR_TSEC1CM|SCCR_TSEC2CM|SCCR_ENCCM|SCCR_USBMPHCM \
+                   |SCCR_USBDRCM|SCCR_PCICM)
+	u8     res0[0xF4];
+} clk8349_t; 
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc8349 {
+    u32    pmccr; /* PMC Configuration Register  */
+#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable  */
+#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable  */
+#define PMCCR_RES ~(PMCCR_SLPEN|PMCCR_DLPEN)
+    u32    pmcer; /* PMC Event Register  */
+#define PMCER_PMCI  0x00000001 /* PMC Interrupt  */
+#define PMCER_RES ~(PMCER_PMCI)
+    u32    pmcmr; /* PMC Mask Register  */
+#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable  */
+#define PMCMR_RES ~(PMCMR_PMCIE)
+	u8 res0[0xF4];
+} pmc8349_t;
+
+
+/*
+ * general purpose I/O module
+ */
+typedef struct gpio8349 {
+	u32 dir; /* direction register */
+	u32 odr; /* open drain register */ 
+	u32 dat; /* data register */
+	u32 ier; /* interrupt event register */
+	u32 imr; /* interrupt mask register */
+	u32 icr; /* external interrupt control register */
+	u8 res0[0xE8];
+} gpio8349_t;
+
+/* 
+ * DDR Memory Controller Memory Map
+ */
+typedef struct ddr_cs_bnds{
+    u32 csbnds;
+#define CSBNDS_SA 0x00FF0000
+#define CSBNDS_SA_SHIFT   16
+#define CSBNDS_EA 0x000000FF
+#define CSBNDS_EA_SHIFT    0
+    u8  res0[4];
+} ddr_cs_bnds_t;
+
+typedef struct ddr8349{
+    ddr_cs_bnds_t csbnds[4];            /**< Chip Select x Memory Bounds */ 
+    u8 res0[0x60];
+    u32 cs_config[4];       /**< Chip Select x Configuration */ 
+#define CSCONFIG_EN         0x80000000
+#define CSCONFIG_AP         0x00800000
+#define CSCONFIG_ROW_BIT    0x00000700
+#define CSCONFIG_ROW_BIT_12 0x00000000
+#define CSCONFIG_ROW_BIT_13 0x00000100
+#define CSCONFIG_ROW_BIT_14 0x00000200
+#define CSCONFIG_COL_BIT    0x00000007
+#define CSCONFIG_COL_BIT_8  0x00000000
+#define CSCONFIG_COL_BIT_9  0x00000001
+#define CSCONFIG_COL_BIT_10 0x00000002
+#define CSCONFIG_COL_BIT_11 0x00000003
+    u8 res1[0x78];
+    u32 timing_cfg_1;       /**< SDRAM Timing Configuration 1 */
+#define TIMING_CFG1_PRETOACT 0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT   28
+#define TIMING_CFG1_ACTTOPRE 0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT   24
+#define TIMING_CFG1_ACTTORW  0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT    20
+#define TIMING_CFG1_CASLAT   0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT     16
+#define TIMING_CFG1_REFREC   0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT     12
+#define TIMING_CFG1_WRREC    0x00000700
+#define TIMING_CFG1_WRREC_SHIFT       8
+#define TIMING_CFG1_ACTTOACT 0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT    4   
+#define TIMING_CFG1_WRTORD   0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT      0
+
+    u32 timing_cfg_2;       /**< SDRAM Timing Configuration 2 */
+#define TIMING_CFG2_CPO           0x0F000000
+#define TIMING_CFG2_CPO_SHIFT             24
+#define TIMING_CFG2_ACSM          0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00   
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT   10
+
+    u32 sdram_cfg;          /**< SDRAM Control Configuration */
+#define SDRAM_CFG_MEM_EN     0x80000000
+#define SDRAM_CFG_SREN       0x40000000
+#define SDRAM_CFG_ECC_EN     0x20000000
+#define SDRAM_CFG_RD_EN      0x10000000
+#define SDRAM_CFG_SDRAM_TYPE 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
+#define SDRAM_CFG_DYN_PWR    0x00200000
+#define SDRAM_CFG_32_BE      0x00080000
+#define SDRAM_CFG_8_BE       0x00040000
+#define SDRAM_CFG_NCAP       0x00020000
+#define SDRAM_CFG_2T_EN      0x00008000
+
+    u8 res2[4];
+    u32 sdram_mode;         /**< SDRAM Mode Configuration */ 
+#define SDRAM_MODE_ESD 0xFFFF0000   
+#define SDRAM_MODE_ESD_SHIFT   16              
+#define SDRAM_MODE_SD  0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT     0
+
+    u8 res3[8];
+    u32 sdram_interval;     /**< SDRAM Interval Configuration */
+#define SDRAM_INTERVAL_REFINT  0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT    16
+#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
+    u8   res9[8];
+    u32  sdram_clk_cntl;
+    u8 res4[0xCCC];
+    u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
+    u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
+    u32 ecc_err_inject;     /**< Memory Data Path Error Injection Mask ECC */
+    u8 res5[0x14];
+    u32 capture_data_hi;    /**< Memory Data Path Read Capture High */
+    u32 capture_data_lo;    /**< Memory Data Path Read Capture Low */
+    u32 capture_ecc;        /**< Memory Data Path Read Capture ECC */
+    u8 res6[0x14];
+    u32 err_detect;         /**< Memory Error Detect */ 
+    u32 err_disable;        /**< Memory Error Disable */
+    u32 err_int_en;         /**< Memory Error Interrupt Enable */
+    u32 capture_attributes; /**< Memory Error Attributes Capture */
+    u32 capture_address;    /**< Memory Error Address Capture */
+    u32 capture_ext_address;/**< Memory Error Extended Address Capture */
+    u32 err_sbe;            /**< Memory Single-Bit ECC Error Management */
+    u8 res7[0xA4];
+	u32 debug_reg;
+    u8 res8[0xFC];
+} ddr8349_t;
+
+/*
+ * I2C1 Controller
+ */ 
+
+
+/*
+ * DUART
+ */
+typedef struct duart8349{
+    u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
+    u8 uier_udmb;      /**< combined register for UIER and UDMB */
+    u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
+    u8 ulcr;        /**< line control register */
+    u8 umcr;        /**< MODEM control register */
+    u8 ulsr;        /**< line status register */
+    u8 umsr;        /**< MODEM status register */
+    u8 uscr;        /**< scratch register */
+    u8 res0[8];
+    u8 udsr;        /**< DMA status register */
+    u8 res1[3];
+    u8 res2[0xEC];
+    
+} duart8349_t;
+
+/*
+ * Local Bus Controller Registers
+ */
+typedef struct lbus_bank{
+    u32 br;             /**< Base Register  */
+    u32 or;             /**< Base Register  */
+} lbus_bank_t;
+
+typedef struct lbus8349 {
+    lbus_bank_t bank[8];
+    u8 res0[0x28];
+    u32 mar;                /**< UPM Address Register */
+    u8 res1[0x4];
+    u32 mamr;               /**< UPMA Mode Register */
+    u32 mbmr;               /**< UPMB Mode Register */
+    u32 mcmr;               /**< UPMC Mode Register */
+    u8 res2[0x8];
+    u32 mrtpr;              /**< Memory Refresh Timer Prescaler Register */
+    u32 mdr;                /**< UPM Data Register */
+    u8 res3[0x8];
+    u32 lsdmr;              /**< SDRAM Mode Register */
+    u8 res4[0x8];
+    u32 lurt;               /**< UPM Refresh Timer */
+    u32 lsrt;               /**< SDRAM Refresh Timer */
+    u8 res5[0x8];
+    u32 ltesr;              /**< Transfer Error Status Register */
+    u32 ltedr;              /**< Transfer Error Disable Register */
+    u32 lteir;              /**< Transfer Error Interrupt Register */
+    u32 lteatr;             /**< Transfer Error Attributes Register */
+    u32 ltear;              /**< Transfer Error Address Register */
+    u8 res6[0xC];
+    u32 lbcr;               /**< Configuration Register */
+#define LBCR_LDIS  0x80000000
+#define LBCR_LDIS_SHIFT    31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT   22
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT   17  
+#define LBCR_EPAR  0x00010000
+#define LBCR_EPAR_SHIFT    16
+#define LBCR_BMT   0x0000FF00
+#define LBCR_BMT_SHIFT      8
+    u32 lcrr;               /**< Clock Ratio Register */
+#define LCRR_DBYP    0x80000000
+#define LCRR_DBYP_SHIFT      31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT   28
+#define LCRR_ECL     0x03000000
+#define LCRR_ECL_SHIFT       24
+#define LCRR_EADC    0x00030000
+#define LCRR_EADC_SHIFT      16
+#define LCRR_CLKDIV  0x0000000F
+#define LCRR_CLKDIV_SHIFT     0
+
+
+    u8 res7[0x28];
+    u8 res8[0xF00];
+} lbus8349_t;
+
+/*
+ * Serial Peripheral Interface
+ */
+typedef struct spi8349
+{
+    u32 mode;     /**< mode register  */
+    u32 event;    /**< event register */
+    u32 mask;     /**< mask register  */
+    u32 com;      /**< command register */
+    u8 res0[0x10];
+    u32 tx;       /**< transmit register */
+    u32 rx;       /**< receive register */
+    u8 res1[0xD8];
+} spi8349_t;
+ 
+typedef struct dma8349 {
+	u8 fixme[0x300];
+} dma8349_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf8349 {
+	u32	config_address;
+#define PCI_CONFIG_ADDRESS_EN	0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
+#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
+#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
+#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
+#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
+	u32 config_data;
+	u32 int_ack;
+	u8	res[116];
+} pciconf8349_t;
+
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+	u32	potar;
+	u8	res0[4];
+	u32	pobar;
+	u8	res1[4];
+	u32	pocmr;
+	u8	res2[4];
+} pot8349_t;
+/*
+ * Sequencer
+ */ 
+typedef struct ios8349 {
+	pot8349_t	pot[6];
+#define POTAR_TA_MASK	0x000fffff
+#define	POBAR_BA_MASK	0x000fffff
+#define	POCMR_EN	0x80000000
+#define	POCMR_IO	0x40000000	/* 0--memory space 1--I/O space */
+#define	POCMR_SE	0x20000000	/* streaming enable */
+#define	POCMR_DST	0x10000000	/* 0--PCI1 1--PCI2*/
+#define	POCMR_CM_MASK	0x000fffff
+#define	POCMR_CM_4G	0x00000000
+#define	POCMR_CM_2G	0x00080000
+#define	POCMR_CM_1G	0x000C0000
+#define	POCMR_CM_512M	0x000E0000
+#define	POCMR_CM_256M	0x000F0000
+#define	POCMR_CM_128M	0x000F8000
+#define	POCMR_CM_64M	0x000FC000
+#define	POCMR_CM_32M	0x000FE000
+#define	POCMR_CM_16M	0x000FF000
+#define	POCMR_CM_8M	0x000FF800
+#define	POCMR_CM_4M	0x000FFC00
+#define	POCMR_CM_2M	0x000FFE00
+#define	POCMR_CM_1M	0x000FFF00
+#define	POCMR_CM_512K	0x000FFF80
+#define	POCMR_CM_256K	0x000FFFC0
+#define	POCMR_CM_128K	0x000FFFE0
+#define	POCMR_CM_64K	0x000FFFF0
+#define	POCMR_CM_32K	0x000FFFF8
+#define	POCMR_CM_16K	0x000FFFFC
+#define	POCMR_CM_8K	0x000FFFFE
+#define	POCMR_CM_4K	0x000FFFFF
+	u8	res0[0x60];
+	u32	pmcr;
+	u8	res1[4];
+	u32	dtcr;
+	u8	res2[4];
+} ios8349_t;
+
+/*
+ * PCI Controller Control and Status Registers
+ */
+typedef struct pcictrl8349 {
+	u32	esr;
+#define ESR_MERR	0x80000000
+#define ESR_APAR	0x00000400
+#define	ESR_PCISERR	0x00000200
+#define	ESR_MPERR	0x00000100
+#define	ESR_TPERR	0x00000080
+#define	ESR_NORSP	0x00000040
+#define	ESR_TABT	0x00000020
+	u32	ecdr;
+#define ECDR_APAR	0x00000400
+#define	ECDR_PCISERR	0x00000200
+#define	ECDR_MPERR	0x00000100
+#define	ECDR_TPERR	0x00000080
+#define	ECDR_NORSP	0x00000040
+#define	ECDR_TABT	0x00000020
+	u32 eer;
+#define EER_APAR	0x00000400
+#define	EER_PCISERR	0x00000200
+#define	EER_MPERR	0x00000100
+#define	EER_TPERR	0x00000080
+#define	EER_NORSP	0x00000040
+#define	EER_TABT	0x00000020
+	u32	eatcr;
+#define	EATCR_ERRTYPR_MASK	0x70000000
+#define	EATCR_ERRTYPR_APR	0x00000000	/* address parity error */
+#define	EATCR_ERRTYPR_WDPR	0x10000000	/* write data parity error */
+#define	EATCR_ERRTYPR_RDPR	0x20000000	/* read data parity error */
+#define	EATCR_ERRTYPR_MA	0x30000000	/* master abort */
+#define	EATCR_ERRTYPR_TA	0x40000000	/* target abort */
+#define	EATCR_ERRTYPR_SE	0x50000000	/* system error indication received */
+#define	EATCR_ERRTYPR_PEA	0x60000000	/* parity error indication received on a read */
+#define	EATCR_ERRTYPR_PEW	0x70000000	/* parity error indication received on a write */
+#define EATCR_BN_MASK		0x0f000000	/* beat number */
+#define	EATCR_BN_1st		0x00000000
+#define	EATCR_BN_2ed		0x01000000
+#define	EATCR_BN_3rd		0x02000000
+#define	EATCR_BN_4th		0x03000000
+#define	EATCR_BN_5th		0x0400000
+#define	EATCR_BN_6th		0x05000000
+#define	EATCR_BN_7th		0x06000000
+#define	EATCR_BN_8th		0x07000000
+#define	EATCR_BN_9th		0x08000000
+#define EATCR_TS_MASK		0x00300000	/* transaction size */
+#define	EATCR_TS_4		0x00000000
+#define	EATCR_TS_1		0x00100000
+#define	EATCR_TS_2		0x00200000
+#define	EATCR_TS_3		0x00300000
+#define	EATCR_ES_MASK		0x000f0000	/* error source */
+#define	EATCR_ES_EM		0x00000000	/* external master */
+#define	EATCR_ES_DMA		0x00050000	
+#define	EATCR_CMD_MASK		0x0000f000
+#define	EATCR_HBE_MASK		0x00000f00	/* PCI high byte enable*/
+#define	EATCR_BE_MASK		0x000000f0	/* PCI byte enable */
+#define	EATCR_HPB		0x00000004	/* high parity bit */
+#define	EATCR_PB		0x00000002	/* parity bit*/
+#define	EATCR_VI		0x00000001	/* error information valid */
+	u32	eacr;
+	u32	eeacr;
+	u32	edlcr;
+	u32	edhcr;
+	u32	gcr;
+	u32	ecr;
+	u32	gsr;
+	u8	res0[12];
+	u32	pitar2;
+	u8	res1[4];
+	u32	pibar2;
+	u32	piebar2;
+	u32	piwar2;
+	u8	res2[4];
+	u32	pitar1;
+	u8	res3[4];
+	u32	pibar1;
+	u32	piebar1;
+	u32	piwar1;
+	u8	res4[4];
+	u32	pitar0;
+	u8	res5[4];
+	u32	pibar0;
+	u8	res6[4];
+	u32	piwar0;
+	u8	res7[132];
+#define PITAR_TA_MASK		0x000fffff
+#define PIBAR_MASK		0xffffffff
+#define PIEBAR_EBA_MASK		0x000fffff
+#define PIWAR_EN		0x80000000
+#define PIWAR_PF		0x20000000
+#define	PIWAR_RTT_MASK		0x000f0000
+#define	PIWAR_RTT_NO_SNOOP	0x00040000
+#define PIWAR_RTT_SNOOP		0x00050000
+#define	PIWAR_WTT_MASK		0x0000f000
+#define	PIWAR_WTT_NO_SNOOP	0x00004000
+#define PIWAR_WTT_SNOOP		0x00005000	
+#define	PIWAR_IWS_MASK	0x0000003F
+#define	PIWAR_IWS_4K	0x0000000B
+#define	PIWAR_IWS_8K	0x0000000C
+#define	PIWAR_IWS_16K	0x0000000D
+#define	PIWAR_IWS_32K	0x0000000E
+#define	PIWAR_IWS_64K	0x0000000F
+#define	PIWAR_IWS_128K	0x00000010
+#define	PIWAR_IWS_256K	0x00000011
+#define	PIWAR_IWS_512K	0x00000012
+#define	PIWAR_IWS_1M	0x00000013
+#define	PIWAR_IWS_2M	0x00000014
+#define	PIWAR_IWS_4M	0x00000015
+#define	PIWAR_IWS_8M	0x00000016
+#define	PIWAR_IWS_16M	0x00000017
+#define	PIWAR_IWS_32M	0x00000018
+#define	PIWAR_IWS_64M	0x00000019
+#define	PIWAR_IWS_128M	0x0000001A
+#define	PIWAR_IWS_256M	0x0000001B
+#define	PIWAR_IWS_512M	0x0000001C
+#define	PIWAR_IWS_1G	0x0000001D
+#define	PIWAR_IWS_2G	0x0000001E
+} pcictrl8349_t;
+
+/*
+ * USB 
+ */
+typedef struct usb8349 {
+	u8 fixme[0x2000];
+} usb8349_t;
+
+/*
+ * TSEC
+ */
+typedef struct tsec8349 {
+	u8 fixme[0x1000];
+} tsec8349_t;
+
+/*
+ * Security
+ */
+typedef struct security8349 {
+	u8 fixme[0x10000];
+} security8349_t;
+
+typedef struct immap {
+	sysconf8349_t sysconf; /* System configuration */
+	wdt8349_t     wdt;     /* Watch Dog Timer (WDT) Registers */
+	rtclk8349_t   rtc;     /* Real Time Clock Module Registers */
+	rtclk8349_t   pit;     /* Periodic Interval Timer */
+	gtm8349_t     gtm[2];  /* Global Timers Module */
+	ipic8349_t    ipic;    /* Integrated Programmable Interrupt Controller */
+	arbiter8349_t arbiter; /* System Arbiter Registers */ 
+	reset8349_t   reset;   /* Reset Module */
+	clk8349_t     clk;     /* System Clock Module */ 
+	pmc8349_t     pmc;     /* Power Management Control Module */
+	gpio8349_t    pgio[2]; /* general purpose I/O module */
+	u8 res0[0x200];
+	u8 DDL_DDR[0x100];
+	u8 DDL_LBIU[0x100];
+	u8 res1[0xE00];
+	ddr8349_t     ddr;     /* DDR Memory Controller Memory */
+	i2c_t     i2c[2];      /* I2C1 Controller */
+	u8 res2[0x1300];
+	duart8349_t   duart[2];/* DUART */
+	u8 res3[0x900];
+	lbus8349_t    lbus;    /* Local Bus Controller Registers */
+	u8 res4[0x1000];
+	spi8349_t     spi;     /* Serial Peripheral Interface */
+	u8 res5[0xF00];
+	dma8349_t     dma;     /* DMA */
+	pciconf8349_t pci_conf[2];  /* PCI Software Configuration Registers */
+	ios8349_t     ios;     /* Sequencer */
+	pcictrl8349_t pci_ctrl[2];  /* PCI Controller Control and Status Registers */
+	u8 res6[0x19900];
+	usb8349_t     usb;
+	tsec8349_t    tsec[2];
+	u8 res7[0xA000];
+	security8349_t security; 
+} immap_t;
+
+#endif /* __IMMAP_8349__ */
diff --git a/include/asm-ppc/mpc8349_pci.h b/include/asm-ppc/mpc8349_pci.h
new file mode 100644
index 000000000..48255a34f
--- /dev/null
+++ b/include/asm-ppc/mpc8349_pci.h
@@ -0,0 +1,167 @@
+#ifndef _PPC_KERNEL_MPC8349_PCI_H
+#define _PPC_KERNEL_MPC8349_PCI_H
+
+
+#define M8265_PCIBR0	0x101ac
+#define M8265_PCIBR1	0x101b0
+#define M8265_PCIMSK0	0x101c4
+#define M8265_PCIMSK1	0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE        0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KB         0xFFFF8000  /* Size of window, smallest */
+#define PCIMSK_64KB         0xFFFF0000
+#define PCIMSK_128KB        0xFFFE0000
+#define PCIMSK_256KB        0xFFFC0000
+#define PCIMSK_512KB        0xFFF80000
+#define PCIMSK_1MB          0xFFF00000
+#define PCIMSK_2MB          0xFFE00000
+#define PCIMSK_4MB          0xFFC00000
+#define PCIMSK_8MB          0xFF800000
+#define PCIMSK_16MB         0xFF000000
+#define PCIMSK_32MB         0xFE000000
+#define PCIMSK_64MB         0xFC000000
+#define PCIMSK_128MB        0xF8000000
+#define PCIMSK_256MB        0xF0000000
+#define PCIMSK_512MB        0xE0000000
+#define PCIMSK_1GB          0xC0000000  /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus
+ * (local) addresses are translated to PCI addresses when the MPC826x is
+ * a PCI bus master (initiator).
+ */
+
+#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1          0x10818
+#define POTAR_REG2          0x10830
+
+#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
+#define POBAR_REG1          0x10820
+#define POBAR_REG2          0x10838
+
+#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1          0x10828
+#define POCMR_REG2          0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KB      0x000FFFFF
+#define POCMR_MASK_8KB      0x000FFFFE
+#define POCMR_MASK_16KB     0x000FFFFC
+#define POCMR_MASK_32KB     0x000FFFF8
+#define POCMR_MASK_64KB     0x000FFFF0
+#define POCMR_MASK_128KB    0x000FFFE0
+#define POCMR_MASK_256KB    0x000FFFC0
+#define POCMR_MASK_512KB    0x000FFF80
+#define POCMR_MASK_1MB      0x000FFF00
+#define POCMR_MASK_2MB      0x000FFE00
+#define POCMR_MASK_4MB      0x000FFC00
+#define POCMR_MASK_8MB      0x000FF800
+#define POCMR_MASK_16MB     0x000FF000
+#define POCMR_MASK_32MB     0x000FE000
+#define POCMR_MASK_64MB     0x000FC000
+#define POCMR_MASK_128MB    0x000F8000
+#define POCMR_MASK_256MB    0x000F0000
+#define POCMR_MASK_512MB    0x000E0000
+#define POCMR_MASK_1GB      0x000C0000
+
+#define POCMR_ENABLE        0x80000000
+#define POCMR_PCI_IO        0x40000000
+#define POCMR_PREFETCH_EN   0x20000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG         0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN   0x1
+
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI
+ * addresses are translated to 60x bus (local) addresses when the
+ * MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1          0x108D0
+#define PIBAR_REG1          0x108D8
+#define PICMR_REG1          0x108E0
+#define PITAR_REG0          0x108E8
+#define PIBAR_REG0          0x108F0
+#define PICMR_REG0          0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KB       0x000FFFFF
+#define PICMR_MASK_8KB       0x000FFFFE
+#define PICMR_MASK_16KB      0x000FFFFC
+#define PICMR_MASK_32KB      0x000FFFF8
+#define PICMR_MASK_64KB      0x000FFFF0
+#define PICMR_MASK_128KB     0x000FFFE0
+#define PICMR_MASK_256KB     0x000FFFC0
+#define PICMR_MASK_512KB     0x000FFF80
+#define PICMR_MASK_1MB       0x000FFF00
+#define PICMR_MASK_2MB       0x000FFE00
+#define PICMR_MASK_4MB       0x000FFC00
+#define PICMR_MASK_8MB       0x000FF800
+#define PICMR_MASK_16MB      0x000FF000
+#define PICMR_MASK_32MB      0x000FE000
+#define PICMR_MASK_64MB      0x000FC000
+#define PICMR_MASK_128MB     0x000F8000
+#define PICMR_MASK_256MB     0x000F0000
+#define PICMR_MASK_512MB     0x000E0000
+#define PICMR_MASK_1GB       0x000C0000
+
+#define PICMR_ENABLE         0x80000000
+#define PICMR_NO_SNOOP_EN    0x40000000
+#define PICMR_PREFETCH_EN    0x20000000
+
+/* PCI error Registers */
+
+#define	PCI_ERROR_STATUS_REG		0x10884
+#define	PCI_ERROR_MASK_REG		0x10888
+#define	PCI_ERROR_CONTROL_REG		0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
+
+/* PCI error Register bit defines */
+
+#define	PCI_ERROR_PCI_ADDR_PAR			0x00000001
+#define	PCI_ERROR_PCI_DATA_PAR_WR		0x00000002
+#define	PCI_ERROR_PCI_DATA_PAR_RD		0x00000004
+#define	PCI_ERROR_PCI_NO_RSP			0x00000008
+#define	PCI_ERROR_PCI_TAR_ABT			0x00000010
+#define	PCI_ERROR_PCI_SERR			0x00000020
+#define	PCI_ERROR_PCI_PERR_RD			0x00000040
+#define	PCI_ERROR_PCI_PERR_WR			0x00000080
+#define	PCI_ERROR_I2O_OFQO			0x00000100
+#define	PCI_ERROR_I2O_IPQO			0x00000200
+#define	PCI_ERROR_IRA				0x00000400
+#define	PCI_ERROR_NMI				0x00000800
+#define	PCI_ERROR_I2O_DBMC			0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG     0x10900
+#define PCI_CFG_DATA_REG     0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI  0x3
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 20949dcc3..d4404c129 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -200,6 +200,11 @@
 #define SPRN_HASH1	0x3D2	/* Primary Hash Address Register */
 #define SPRN_HASH2	0x3D3	/* Secondary Hash Address Resgister */
 #define SPRN_HID0	0x3F0	/* Hardware Implementation Register 0 */
+
+#define HID0_ICE_SHIFT		15
+#define HID0_DCE_SHIFT		14
+#define HID0_DLOCK_SHIFT	12
+
 #define   HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
 #define   HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
 #define   HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
@@ -211,10 +216,10 @@
 #define   HID0_NAP	(1<<22)
 #define   HID0_SLEEP	(1<<21)
 #define   HID0_DPM	(1<<20)
-#define   HID0_ICE	(1<<15)		/* Instruction Cache Enable */
-#define   HID0_DCE	(1<<14)		/* Data Cache Enable */
+#define   HID0_ICE	(1<<HID0_ICE_SHIFT)	/* Instruction Cache Enable */
+#define   HID0_DCE	(1<<HID0_DCE_SHIFT)	/* Data Cache Enable */
 #define   HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */
-#define   HID0_DLOCK	(1<<12)		/* Data Cache Lock */
+#define   HID0_DLOCK	(1<<HID0_DLOCK_SHIFT)	/* Data Cache Lock */
 #define   HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */
 #define   HID0_DCFI	(1<<10)		/* Data Cache Flash Invalidate */
 #define   HID0_DCI	HID0_DCFI
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 5da0e68ba..e821e91ec 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -45,6 +45,9 @@ typedef struct bd_info {
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	bi_mbar_base;	/* base of internal registers */
 #endif
+#if defined(CONFIG_MPC83XX)
+	unsigned long	bi_immrbar;
+#endif
 #if defined(CONFIG_MPC8220)
 	unsigned long	bi_mbar_base;	/* base of internal registers */
 	unsigned long   bi_inpfreq;     /* Input Freq, In MHz */
diff --git a/include/common.h b/include/common.h
index 625c38989..efc638d88 100644
--- a/include/common.h
+++ b/include/common.h
@@ -83,6 +83,10 @@ typedef volatile unsigned char	vu_char;
 #include <mpc85xx.h>
 #include <asm/immap_85xx.h>
 #endif
+#ifdef CONFIG_MPC83XX
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
 #ifdef	CONFIG_4xx
 #include <ppc4xx.h>
 #endif
@@ -409,8 +413,9 @@ int	sdram_adjust_866 (void);
 int	adjust_sdram_tbs_8xx (void);
 #if defined(CONFIG_8260)
 int	prt_8260_clks (void);
-#endif
-#if defined(CONFIG_MPC5xxx)
+#elif defined(CONFIG_MPC83XX)
+int print_clock_conf(void);
+#elif defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
 #endif
 #if defined(CONFIG_MPC8220)
diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h
new file mode 100644
index 000000000..4f4a99bef
--- /dev/null
+++ b/include/configs/MPC8349ADS.h
@@ -0,0 +1,609 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8349ads board configuration file
+ *
+ * Please refer to doc/README.mpc83xxads for more info.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_MII
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_MPC8349ADS	1	/* MPC8349ADS board specific */
+
+#define CONFIG_PCI
+
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66000000
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
+
+#define CFG_IMMRBAR		0xE0000000
+
+#undef CFG_DRAM_TEST                   /* memory test, takes time */
+#define CFG_MEMTEST_START       0x00000000      /* memtest region */
+#define CFG_MEMTEST_END         0x00100000
+
+
+
+/*
+ * DDR Setup
+ */
+
+#define CFG_DDR_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#undef  CONFIG_DDR_2T_TIMING
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR parameters
+     */
+    #define CFG_DDR_SIZE	    256		/* Mb */
+    #define CFG_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+    #define CFG_DDR_TIMING_1	0x37344321
+    #define CFG_DDR_TIMING_2	0x00000800  /* P9-45,may need tuning */
+    #define CFG_DDR_CONTROL 	0xc2000000  /* unbuffered,no DYN_PWR */
+    #define CFG_DDR_MODE    	0x00000062  /* DLL,normal,seq,4/2.5 */
+    #define CFG_DDR_INTERVAL	0x05200100  /* autocharge,no open page */
+#endif
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI			/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* FLASH size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
+			(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+			BR_V)			/* valid */
+#define CFG_OR0_PRELIM		0xff806ff7	/* 16Mb Flash size*/
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE	/* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM  0x80000016		/* 16Mb window size */
+
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP      0x7F000000
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for ADS config reg
+ */
+#define CFG_BCSR             0xF8000000
+#define CFG_LBLAWBAR1_PRELIM CFG_BCSR	/* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM  0x8000000E		/* Access window size 32K */
+#define CFG_BR1_PRELIM	  (CFG_BCSR|0x00000801)	/* Port-size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM		0xFFFFE8f0	/* length 32K */
+
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000   /* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x1000	     /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE  	0x100     /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR	0x00000000
+
+#define CFG_LB_SDRAM	/* if board has SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM		0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/
+
+#define CFG_LBLAWBAR2_PRELIM 0xF0000000
+
+#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/
+
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM	0xfc006901
+
+#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
+                                | CFG_LBC_LSDMR_BSMA1516	\
+				| CFG_LBC_LSDMR_RFCR8		\
+				| CFG_LBC_LSDMR_PRETOACT6	\
+				| CFG_LBC_LSDMR_ACTTORW3	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC3		\
+				| CFG_LBC_LSDMR_CL3		\
+				)
+
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+
+#endif
+
+
+
+
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_IMMRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET      0x3000
+#define CFG_I2C2_OFFSET      0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+
+
+/* IO Configuration */
+#define CFG_IO_CONF (\
+	IO_CONF_UART |\
+	IO_CONF_TSEC1 |\
+	IO_CONF_IRQ0 |\
+	IO_CONF_IRQ1 |\
+	IO_CONF_IRQ2 |\
+	IO_CONF_IRQ3 |\
+	IO_CONF_IRQ4 |\
+	IO_CONF_IRQ5 |\
+	IO_CONF_IRQ6 |\
+	IO_CONF_IRQ7 )
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+
+#define CFG_PCI2_MEM_BASE	0xA0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe3000000
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#if defined(CONFIG_PCI)
+
+//#define PCI_64BIT
+#define PCI_ALL_PCI1
+//#define PCI_ONE_PCI1
+//#define PCI_TWO_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xFIXME
+    #define PCI_ENET0_MEMADDR	0xFIXME
+    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_GMII		1	/* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1	1
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2	1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+  #define CFG_ENV_IS_IN_FLASH	1
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CFG_ENV_SIZE		0x2000
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #else
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #else
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C       \
+				| CFG_CMD_MII       \
+				)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#endif
+
+
+#define CFG_HID0_INIT 0x000000000
+
+#define CFG_HID0_FINAL CFG_HID0_INIT
+
+/* #define CFG_HID0_FINAL		(\
+	HID0_ENABLE_INSTRUCTION_CACHE |\
+	HID0_ENABLE_M_BIT |\
+	HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+#define CFG_HID2 0x000000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:04:9f:11:22:33
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:7D:01
+#endif
+
+#define CONFIG_IPADDR    10.193.20.150
+
+#define CONFIG_HOSTNAME	 unknown
+#define CONFIG_ROOTPATH	 /tftpboot/10.193.20.150
+#define CONFIG_BOOTFILE	 /tftpboot/vmlinux.150
+
+#define CONFIG_SERVERIP  10.193.20.58
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 115200
+
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		                        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=400000\0"			                        \
+   "ramdiskfile=ramfs.83xx\0"						\
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+   "nfsroot=$serverip:$rootpath "                                       \
+   "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "    \
+   "console=$consoledev,$baudrate $othbootargs;"                        \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+   "console=$consoledev,$baudrate $othbootargs;"                        \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
new file mode 100644
index 000000000..5161df89e
--- /dev/null
+++ b/include/mpc83xx.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc83xx.h
+ *
+ * MPC83xx specific definitions
+ */
+
+#ifndef __MPC83XX_H__
+#define __MPC83XX_H__
+
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/*
+ * MPC83xx cpu provide RCR register to do reset thing specially. easier
+ * to implement
+ */
+
+#define MPC83xx_RESET
+
+/*
+ * System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define CONFIG_DEFAULT_IMMR 0xFF400000
+
+/*
+ * Watchdog
+ */
+#define SWCRR      0x0204 
+#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
+#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
+#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ 
+#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
+#define SWCRR_RES  ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+#define SWCNR      0x0208
+#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
+#define SWCNR_RES  ~(SWCNR_SWCN)
+
+#define SWSRR      0x020E
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define IMMRBAR 0x0000
+#define IMMRBAR_BASE_ADDR     0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */
+#define IMMRBAR_RES           ~(IMMRBAR_BASE_ADDR)
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define LBLAWBAR0 0x0020
+#define LBLAWAR0  0x0024
+#define LBLAWBAR1 0x0028
+#define LBLAWAR1  0x002C
+#define LBLAWBAR2 0x0030
+#define LBLAWAR2  0x0034
+#define LBLAWBAR3 0x0038
+#define LBLAWAR3  0x003C
+
+
+/*
+ * Base Registers & Option Registers
+ */
+#define BR0 0x5000
+#define BR1 0x5008
+#define BR2 0x5010
+#define BR3 0x5018
+#define BR4 0x5020
+#define BR5 0x5028
+#define BR6 0x5030
+#define BR7 0x5038
+
+#define BR_BA   0xFFFF8000
+#define BR_BA_SHIFT     15
+#define BR_PS   0x00001800
+#define BR_PS_SHIFT     11
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT    9
+#define BR_WP   0x00000100
+#define BR_WP_SHIFT      8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT    5
+#define BR_V    0x00000001
+#define BR_V_SHIFT       0
+#define BR_RES  ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_GPCM_AM    0xFFFF8000
+#define OR_GPCM_AM_SHIFT      15
+#define OR_GPCM_BCTLD 0x00001000
+#define OR_GPCM_BCTLD_SHIFT   12
+#define OR_GPCM_CSNT  0x00000800
+#define OR_GPCM_CSNT_SHIFT    11
+#define OR_GPCM_ACS   0x00000600
+#define OR_GPCM_ACS_SHIFT      9
+#define OR_GPCM_XACS  0x00000100
+#define OR_GPCM_XACS_SHIFT     8
+#define OR_GPCM_SCY   0x000000F0
+#define OR_GPCM_SCY_SHIFT      4
+#define OR_GPCM_SETA  0x00000008
+#define OR_GPCM_SETA_SHIFT     3
+#define OR_GPCM_TRLX  0x00000004
+#define OR_GPCM_TRLX_SHIFT     2
+#define OR_GPCM_EHTR  0x00000002
+#define OR_GPCM_EHTR_SHIFT     1
+#define OR_GPCM_EAD   0x00000001
+#define OR_GPCM_EAD_SHIFT      0
+
+#define OR_UPM_AM    0xFFFF8000
+#define OR_UPM_AM_SHIFT      15
+#define OR_UPM_XAM   0x00006000
+#define OR_UPM_XAM_SHIFT     13
+#define OR_UPM_BCTLD 0x00001000
+#define OR_UPM_BCTLD_SHIFT   12
+#define OR_UPM_BI    0x00000100
+#define OR_UPM_BI_SHIFT       8
+#define OR_UPM_TRLX  0x00000004
+#define OR_UPM_TRLX_SHIFT     2
+#define OR_UPM_EHTR  0x00000002
+#define OR_UPM_EHTR_SHIFT     1
+#define OR_UPM_EAD   0x00000001
+#define OR_UPM_EAD_SHIFT      0
+
+#define OR_SDRAM_AM    0xFFFF8000
+#define OR_SDRAM_AM_SHIFT      15
+#define OR_SDRAM_XAM   0x00006000
+#define OR_SDRAM_XAM_SHIFT     13
+#define OR_SDRAM_COLS  0x00001C00
+#define OR_SDRAM_COLS_SHIFT    10
+#define OR_SDRAM_ROWS  0x000001C0
+#define OR_SDRAM_ROWS_SHIFT     6
+#define OR_SDRAM_PMSEL 0x00000020
+#define OR_SDRAM_PMSEL_SHIFT    5
+#define OR_SDRAM_EAD   0x00000001
+#define OR_SDRAM_EAD_SHIFT      0
+
+/*
+ * Hard Reset Configration Word - High
+ */	
+#define HRCWH_PCI_AGENT              0x00000000
+#define HRCWH_PCI_HOST               0x80000000
+
+#define HRCWH_32_BIT_PCI             0x00000000
+#define HRCWH_64_BIT_PCI             0x40000000
+
+#define HRCWH_PCI1_ARBITER_DISABLE   0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE    0x20000000
+
+#define HRCWH_PCI2_ARBITER_DISABLE   0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE    0x10000000
+
+#define HRCWH_CORE_DISABLE           0x08000000
+#define HRCWH_CORE_ENABLE            0x00000000
+
+#define HRCWH_FROM_0X00000100        0x00000000
+#define HRCWH_FROM_0XFFF00100        0x04000000
+
+#define HRCWH_BOOTSEQ_DISABLE        0x00000000
+#define HRCWH_BOOTSEQ_NORMAL         0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED       0x02000000
+
+#define HRCWH_SW_WATCHDOG_DISABLE    0x00000000 
+#define HRCWH_SW_WATCHDOG_ENABLE     0x00800000 
+
+#define HRCWH_ROM_LOC_DDR_SDRAM      0x00000000
+#define HRCWH_ROM_LOC_PCI1           0x00100000
+#define HRCWH_ROM_LOC_PCI2           0x00200000
+#define HRCWH_ROM_LOC_LOCAL_8BIT     0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT    0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT    0x00700000
+
+#define HRCWH_TSEC1M_IN_RGMII        0x00000000
+#define HRCWH_TSEC1M_IN_RTBI         0x00004000
+#define HRCWH_TSEC1M_IN_GMII         0x00008000
+#define HRCWH_TSEC1M_IN_TBI          0x0000C000
+
+#define HRCWH_TSEC2M_IN_RGMII        0x00000000
+#define HRCWH_TSEC2M_IN_RTBI         0x00001000
+#define HRCWH_TSEC2M_IN_GMII         0x00002000
+#define HRCWH_TSEC2M_IN_TBI          0x00003000
+
+#define HRCWH_BIG_ENDIAN             0x00000000
+#define HRCWH_LITTLE_ENDIAN          0x00000008
+
+/*
+ * Hard Reset Configration Word - Low
+ */
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
+
+#define HRCWL_DDR_TO_SCB_CLK_1X1     0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1     0x40000000
+
+#define HRCWL_CSB_TO_CLKIN_16X1      0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1       0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1       0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1       0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1       0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1       0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1       0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1       0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1       0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1       0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1      0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1      0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1      0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1      0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1      0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1      0x0F000000
+
+#define HRCWL_VCO_BYPASS             0x00000000
+#define HRCWL_VCO_1X2                0x00000000
+#define HRCWL_VCO_1X4                0x00200000
+#define HRCWL_VCO_1X8                0x00400000
+
+#define HRCWL_CORE_TO_CSB_BYPASS     0x00000000
+#define HRCWL_CORE_TO_CSB_1X1        0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1      0x00030000
+#define HRCWL_CORE_TO_CSB_2X1        0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1      0x00050000
+#define HRCWL_CORE_TO_CSB_3X1        0x00060000
+
+/*
+ * LCRR - Clock Ratio Register (10.3.1.16) 
+ */
+#define LCRR_DBYP      0x80000000
+#define LCRR_DBYP_SHIFT        31
+#define LCRR_BUFCMDC   0x30000000
+#define LCRR_BUFCMDC_1 0x10000000
+#define LCRR_BUFCMDC_2 0x20000000
+#define LCRR_BUFCMDC_3 0x30000000
+#define LCRR_BUFCMDC_4 0x00000000
+#define LCRR_BUFCMDC_SHIFT     28
+#define LCRR_ECL       0x03000000
+#define LCRR_ECL_4     0x00000000
+#define LCRR_ECL_5     0x01000000
+#define LCRR_ECL_6     0x02000000
+#define LCRR_ECL_7     0x03000000
+#define LCRR_ECL_SHIFT         24
+#define LCRR_EADC      0x00030000
+#define LCRR_EADC_1    0x00010000
+#define LCRR_EADC_2    0x00020000
+#define LCRR_EADC_3    0x00030000
+#define LCRR_EADC_4    0x00000000
+#define LCRR_EADC_SHIFT        16
+#define LCRR_CLKDIV    0x0000000F
+#define LCRR_CLKDIV_2  0x00000002
+#define LCRR_CLKDIV_4  0x00000004
+#define LCRR_CLKDIV_8  0x00000008
+#define LCRR_CLKDIV_SHIFT       0
+ 
+
+#endif	/* __MPC83XX_H__ */