diff options
| -rw-r--r-- | board/st/u8500/Makefile | 2 | ||||
| -rw-r--r-- | board/st/u8500/db8500_pins.h | 745 | ||||
| -rw-r--r-- | board/st/u8500/gpio.c | 272 | ||||
| -rw-r--r-- | board/st/u8500/mcde_display.c | 1 | ||||
| -rw-r--r-- | board/st/u8500/mcde_hw.c | 3 | ||||
| -rw-r--r-- | board/st/u8500/mmc_host.c | 62 | ||||
| -rw-r--r-- | board/st/u8500/u8500.c | 133 | ||||
| -rw-r--r-- | board/st/u8500/u8500_i2c.c | 14 | ||||
| -rw-r--r-- | drivers/gpio/Makefile | 1 | ||||
| -rw-r--r-- | drivers/gpio/db8500_gpio.c | 226 | ||||
| -rw-r--r-- | drivers/spi/u8500_spi.c | 76 | ||||
| -rwxr-xr-x | drivers/usb/gadget/u8500_udc.c | 3 | ||||
| -rw-r--r-- | include/asm-arm/arch-db8500/common.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-db8500/gpio.h | 526 | ||||
| -rw-r--r-- | include/configs/u8500.h | 1 | ||||
| -rw-r--r-- | include/db8500_gpio.h | 43 | ||||
| -rw-r--r-- | include/db8500_pincfg.h | 173 |
17 files changed, 1286 insertions, 997 deletions
diff --git a/board/st/u8500/Makefile b/board/st/u8500/Makefile index 5fe10cce4..713f57d0e 100644 --- a/board/st/u8500/Makefile +++ b/board/st/u8500/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := u8500.o gpio.o u8500_i2c.o mmc_host.o mmc_utils.o mcde_display.o mcde_hw.o ab8500vibra.o cmd_cdump.o +COBJS := u8500.o u8500_i2c.o mmc_host.o mmc_utils.o mcde_display.o mcde_hw.o ab8500vibra.o cmd_cdump.o SOBJS := mmc_fifo.o COBJS-$(CONFIG_ITP_LOAD) += itp.o cspsa_fp.o diff --git a/board/st/u8500/db8500_pins.h b/board/st/u8500/db8500_pins.h new file mode 100644 index 000000000..9cbaff648 --- /dev/null +++ b/board/st/u8500/db8500_pins.h @@ -0,0 +1,745 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + ** + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + */ + +#ifndef __DB8500_PINS_H +#define __DB8500_PINS_H + +#include <db8500_pincfg.h> + +#define GPIO0_GPIO PIN_CFG(0, GPIO) +#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) +#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) +#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) + +#define GPIO1_GPIO PIN_CFG(1, GPIO) +#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) +#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) +#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) + +#define GPIO2_GPIO PIN_CFG(2, GPIO) +#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) +#define GPIO2_NONE PIN_CFG(2, ALT_B) +#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) + +#define GPIO3_GPIO PIN_CFG(3, GPIO) +#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) +#define GPIO3_NONE PIN_CFG(3, ALT_B) +#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) + +#define GPIO4_GPIO PIN_CFG(4, GPIO) +#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) +#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) +#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) + +#define GPIO5_GPIO PIN_CFG(5, GPIO) +#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) +#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) +#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) + +#define GPIO6_GPIO PIN_CFG(6, GPIO) +#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) +#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) +#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) + +#define GPIO7_GPIO PIN_CFG(7, GPIO) +#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) +#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) +#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) + +#define GPIO8_GPIO PIN_CFG(8, GPIO) +#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) +#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) + +#define GPIO9_GPIO PIN_CFG(9, GPIO) +#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) +#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) + +#define GPIO10_GPIO PIN_CFG(10, GPIO) +#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) +#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) +#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) + +#define GPIO11_GPIO PIN_CFG(11, GPIO) +#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) +#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) +#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) + +#define GPIO12_GPIO PIN_CFG(12, GPIO) +#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) +#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) + +#define GPIO13_GPIO PIN_CFG(13, GPIO) +#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) + +#define GPIO14_GPIO PIN_CFG(14, GPIO) +#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) + +#define GPIO15_GPIO PIN_CFG(15, GPIO) +#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) +#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) + +#define GPIO16_GPIO PIN_CFG(16, GPIO) +#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) +#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) +#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) + +#define GPIO17_GPIO PIN_CFG(17, GPIO) +#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) +#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) +#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) + +#define GPIO18_GPIO PIN_CFG(18, GPIO) +#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) +#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) +#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) + +#define GPIO19_GPIO PIN_CFG(19, GPIO) +#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) +#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) +#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) + +#define GPIO20_GPIO PIN_CFG(20, GPIO) +#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) +#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) +#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) + +#define GPIO21_GPIO PIN_CFG(21, GPIO) +#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) +#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) +#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) + +#define GPIO22_GPIO PIN_CFG(22, GPIO) +#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) +#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) +#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) + +#define GPIO23_GPIO PIN_CFG(23, GPIO) +#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) +#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) +#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) + +#define GPIO24_GPIO PIN_CFG(24, GPIO) +#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) +#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) +#define GPIO24_MS_BS PIN_CFG(24, ALT_C) + +#define GPIO25_GPIO PIN_CFG(25, GPIO) +#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) +#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) +#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) + +#define GPIO26_GPIO PIN_CFG(26, GPIO) +#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) +#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) +#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) + +#define GPIO27_GPIO PIN_CFG(27, GPIO) +#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) +#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) +#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) + +#define GPIO28_GPIO PIN_CFG(28, GPIO) +#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) +#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) +#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) + +#define GPIO29_GPIO PIN_CFG(29, GPIO) +#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) +#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) +#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) + +#define GPIO30_GPIO PIN_CFG(30, GPIO) +#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) +#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) +#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) + +#define GPIO31_GPIO PIN_CFG(31, GPIO) +#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) +#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) +#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) + +#define GPIO32_GPIO PIN_CFG(32, GPIO) +#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) +#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) +#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) + +#define GPIO33_GPIO PIN_CFG(33, GPIO) +#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) +#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) +#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) + +#define GPIO34_GPIO PIN_CFG(34, GPIO) +#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) +#define GPIO34_NONE PIN_CFG(34, ALT_B) +#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) + +#define GPIO35_GPIO PIN_CFG(35, GPIO) +#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) +#define GPIO35_NONE PIN_CFG(35, ALT_B) +#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) + +#define GPIO36_GPIO PIN_CFG(36, GPIO) +#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) +#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) +#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) + +#define GPIO64_GPIO PIN_CFG(64, GPIO) +#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) +#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) +#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) + +#define GPIO65_GPIO PIN_CFG(65, GPIO) +#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) +#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) +#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) + +#define GPIO66_GPIO PIN_CFG(66, GPIO) +#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) +#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) +#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) + +#define GPIO67_GPIO PIN_CFG(67, GPIO) +#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) +#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) +#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) + +#define GPIO68_GPIO PIN_CFG(68, GPIO) +#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) +#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) +#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) + +#define GPIO69_GPIO PIN_CFG(69, GPIO) +#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) +#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) +#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) + +#define GPIO70_GPIO PIN_CFG(70, GPIO) +#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) +#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) +#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) + +#define GPIO71_GPIO PIN_CFG(71, GPIO) +#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) +#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) +#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) + +#define GPIO72_GPIO PIN_CFG(72, GPIO) +#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) +#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) +#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) + +#define GPIO73_GPIO PIN_CFG(73, GPIO) +#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) +#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) +#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) + +#define GPIO74_GPIO PIN_CFG(74, GPIO) +#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) +#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) +#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) + +#define GPIO75_GPIO PIN_CFG(75, GPIO) +#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) +#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) +#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) + +#define GPIO76_GPIO PIN_CFG(76, GPIO) +#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) +#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) +#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) + +#define GPIO77_GPIO PIN_CFG(77, GPIO) +#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) +#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) +#define GPIO77_NONE PIN_CFG(77, ALT_C) + +#define GPIO78_GPIO PIN_CFG(78, GPIO) +#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) +#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) +#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) + +#define GPIO79_GPIO PIN_CFG(79, GPIO) +#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) +#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) +#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) + +#define GPIO80_GPIO PIN_CFG(80, GPIO) +#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) +#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) +#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) + +#define GPIO81_GPIO PIN_CFG(81, GPIO) +#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) +#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) +#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) + +#define GPIO82_GPIO PIN_CFG(82, GPIO) +#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) +#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) + +#define GPIO83_GPIO PIN_CFG(83, GPIO) +#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) +#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) + +#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP) +#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) +#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) + +#define GPIO85_GPIO PIN_CFG(85, GPIO) +#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) +#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) + +#define GPIO86_GPIO PIN_CFG(86, GPIO) +#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) +#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) +#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) + +#define GPIO87_GPIO PIN_CFG(87, GPIO) +#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) +#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) +#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) + +#define GPIO88_GPIO PIN_CFG(88, GPIO) +#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) +#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) +#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) + +#define GPIO89_GPIO PIN_CFG(89, GPIO) +#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) +#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) +#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) + +#define GPIO90_GPIO PIN_CFG(90, GPIO) +#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) +#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) +#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) + +#define GPIO91_GPIO PIN_CFG(91, GPIO) +#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) +#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) +#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) + +#define GPIO92_GPIO PIN_CFG(92, GPIO) +#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) +#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) +#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) + +#define GPIO93_GPIO PIN_CFG(93, GPIO) +#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) +#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) +#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) + +#define GPIO94_GPIO PIN_CFG(94, GPIO) +#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) +#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) +#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) + +#define GPIO95_GPIO PIN_CFG(95, GPIO) +#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) +#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) +#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) + +#define GPIO96_GPIO PIN_CFG(96, GPIO) +#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) +#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) +#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) + +#define GPIO97_GPIO PIN_CFG(97, GPIO) +#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) +#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) +#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) + +#define GPIO128_GPIO PIN_CFG(128, GPIO) +#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) +#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) + +#define GPIO129_GPIO PIN_CFG(129, GPIO) +#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) +#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) + +#define GPIO130_GPIO PIN_CFG(130, GPIO) +#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) +#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) +#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) + +#define GPIO131_GPIO PIN_CFG(131, GPIO) +#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) +#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) + +#define GPIO132_GPIO PIN_CFG(132, GPIO) +#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) +#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) + +#define GPIO133_GPIO PIN_CFG(133, GPIO) +#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) +#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) + +#define GPIO134_GPIO PIN_CFG(134, GPIO) +#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) +#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) + +#define GPIO135_GPIO PIN_CFG(135, GPIO) +#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) +#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) + +#define GPIO136_GPIO PIN_CFG(136, GPIO) +#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) +#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) + +#define GPIO137_GPIO PIN_CFG(137, GPIO) +#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) +#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) + +#define GPIO138_GPIO PIN_CFG(138, GPIO) +#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) +#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) + +#define GPIO139_GPIO PIN_CFG(139, GPIO) +#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) +#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) +#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) + +#define GPIO140_GPIO PIN_CFG(140, GPIO) +#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) +#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) +#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) + +#define GPIO141_GPIO PIN_CFG(141, GPIO) +#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) +#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) +#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) + +#define GPIO142_GPIO PIN_CFG(142, GPIO) +#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) +#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) +#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) + +#define GPIO143_GPIO PIN_CFG(143, GPIO) +#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) + +#define GPIO144_GPIO PIN_CFG(144, GPIO) +#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) + +#define GPIO145_GPIO PIN_CFG(145, GPIO) +#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) + +#define GPIO146_GPIO PIN_CFG(146, GPIO) +#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) + +#define GPIO147_GPIO PIN_CFG(147, GPIO) +#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) + +#define GPIO148_GPIO PIN_CFG(148, GPIO) +#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) + +#define GPIO149_GPIO PIN_CFG(149, GPIO) +#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) +#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) +#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) + +#define GPIO150_GPIO PIN_CFG(150, GPIO) +#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) +#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) + +#define GPIO151_GPIO PIN_CFG(151, GPIO) +#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) +#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) +#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) + +#define GPIO152_GPIO PIN_CFG(152, GPIO) +#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) +#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) +#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) + +#define GPIO153_GPIO PIN_CFG(153, GPIO) +#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) +#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) +#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) + +#define GPIO154_GPIO PIN_CFG(154, GPIO) +#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) +#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) +#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) + +#define GPIO155_GPIO PIN_CFG(155, GPIO) +#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) +#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) +#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) + +#define GPIO156_GPIO PIN_CFG(156, GPIO) +#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) +#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) +#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) + +#define GPIO157_GPIO PIN_CFG(157, GPIO) +#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) +#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) +#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) + +#define GPIO158_GPIO PIN_CFG(158, GPIO) +#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) +#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) +#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) + +#define GPIO159_GPIO PIN_CFG(159, GPIO) +#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) +#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) +#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) + +#define GPIO160_GPIO PIN_CFG(160, GPIO) +#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) +#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) +#define GPIO160_NONE PIN_CFG(160, ALT_C) + +#define GPIO161_GPIO PIN_CFG(161, GPIO) +#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) +#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) +#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) + +#define GPIO162_GPIO PIN_CFG(162, GPIO) +#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) +#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) +#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) + +#define GPIO163_GPIO PIN_CFG(163, GPIO) +#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) +#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) +#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) + +#define GPIO164_GPIO PIN_CFG(164, GPIO) +#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) +#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) +#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) + +#define GPIO165_GPIO PIN_CFG(165, GPIO) +#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) +#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) +#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) + +#define GPIO166_GPIO PIN_CFG(166, GPIO) +#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) +#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) +#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) + +#define GPIO167_GPIO PIN_CFG(167, GPIO) +#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) +#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) +#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) + +#define GPIO168_GPIO PIN_CFG(168, GPIO) +#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) +#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) +#define GPIO168_NONE PIN_CFG(168, ALT_C) + +#define GPIO169_GPIO PIN_CFG(169, GPIO) +#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) +#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) +#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) + +#define GPIO170_GPIO PIN_CFG(170, GPIO) +#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) +#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) +#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) + +#define GPIO171_GPIO PIN_CFG(171, GPIO) +#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) +#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) +#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) + +#define GPIO192_GPIO PIN_CFG(192, GPIO) +#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) + +#define GPIO193_GPIO PIN_CFG(193, GPIO) +#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) + +#define GPIO194_GPIO PIN_CFG(194, GPIO) +#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) + +#define GPIO195_GPIO PIN_CFG(195, GPIO) +#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) + +#define GPIO196_GPIO PIN_CFG(196, GPIO) +#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) + +#define GPIO197_GPIO PIN_CFG(197, GPIO) +#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) + +#define GPIO198_GPIO PIN_CFG(198, GPIO) +#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) + +#define GPIO199_GPIO PIN_CFG(199, GPIO) +#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) + +#define GPIO200_GPIO PIN_CFG(200, GPIO) +#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) + +#define GPIO201_GPIO PIN_CFG(201, GPIO) +#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) + +#define GPIO202_GPIO PIN_CFG(202, GPIO) +#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) +#define GPIO202_PWL PIN_CFG(202, ALT_B) +#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) + +#define GPIO203_GPIO PIN_CFG(203, GPIO) +#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) + +#define GPIO204_GPIO PIN_CFG(204, GPIO) +#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) + +#define GPIO205_GPIO PIN_CFG(205, GPIO) +#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) + +#define GPIO206_GPIO PIN_CFG(206, GPIO) +#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) + +#define GPIO207_GPIO PIN_CFG(207, GPIO) +#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) + +#define GPIO208_GPIO PIN_CFG(208, GPIO) +#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) + +#define GPIO209_GPIO PIN_CFG(209, GPIO) +#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) +#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) + +#define GPIO210_GPIO PIN_CFG(210, GPIO) +#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) + +#define GPIO211_GPIO PIN_CFG(211, GPIO) +#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) + +#define GPIO212_GPIO PIN_CFG(212, GPIO) +#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) +#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) + +#define GPIO213_GPIO PIN_CFG(213, GPIO) +#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) +#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) + +#define GPIO214_GPIO PIN_CFG(214, GPIO) +#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) +#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) + +#define GPIO215_GPIO PIN_CFG(215, GPIO) +#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) +#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) +#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) + +#define GPIO216_GPIO PIN_CFG(216, GPIO) +#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) +#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) +#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) + +#define GPIO217_GPIO PIN_CFG(217, GPIO) +#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) +#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) +#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) + +#define GPIO218_GPIO PIN_CFG(218, GPIO) +#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) +#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) +#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) + +#define GPIO219_GPIO PIN_CFG(219, GPIO) +#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) +#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) + +#define GPIO220_GPIO PIN_CFG(220, GPIO) +#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) +#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) +#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) + +#define GPIO221_GPIO PIN_CFG(221, GPIO) +#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) +#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) + +#define GPIO222_GPIO PIN_CFG(222, GPIO) +#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) +#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) + +#define GPIO223_GPIO PIN_CFG(223, GPIO) +#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) +#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) +#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) + +#define GPIO224_GPIO PIN_CFG(224, GPIO) +#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) +#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) +#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) + +#define GPIO225_GPIO PIN_CFG(225, GPIO) +#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) +#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) +#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) + +#define GPIO226_GPIO PIN_CFG(226, GPIO) +#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) +#define GPIO226_PWL PIN_CFG(226, ALT_B) +#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) + +#define GPIO227_GPIO PIN_CFG(227, GPIO) +#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) + +#define GPIO228_GPIO PIN_CFG(228, GPIO) +#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) + +#define GPIO229_GPIO PIN_CFG(229, GPIO) +#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) +#define GPIO229_PWL PIN_CFG(229, ALT_B) +#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) + +#define GPIO230_GPIO PIN_CFG(230, GPIO) +#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) +#define GPIO230_PWL PIN_CFG(230, ALT_B) +#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) + +#define GPIO256_GPIO PIN_CFG(256, GPIO) +#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) + +#define GPIO257_GPIO PIN_CFG(257, GPIO) +#define GPIO257_USB_STP PIN_CFG(257, ALT_A) + +#define GPIO258_GPIO PIN_CFG(258, GPIO) +#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) +#define GPIO258_NONE PIN_CFG(258, ALT_B) +#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) + +#define GPIO259_GPIO PIN_CFG(259, GPIO) +#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) + +#define GPIO260_GPIO PIN_CFG(260, GPIO) +#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) + +#define GPIO261_GPIO PIN_CFG(261, GPIO) +#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) + +#define GPIO262_GPIO PIN_CFG(262, GPIO) +#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) + +#define GPIO263_GPIO PIN_CFG(263, GPIO) +#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) + +#define GPIO264_GPIO PIN_CFG(264, GPIO) +#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) + +#define GPIO265_GPIO PIN_CFG(265, GPIO) +#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) + +#define GPIO266_GPIO PIN_CFG(266, GPIO) +#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) + +#define GPIO267_GPIO PIN_CFG(267, GPIO) +#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) + +#endif diff --git a/board/st/u8500/gpio.c b/board/st/u8500/gpio.c deleted file mode 100644 index 88e868532..000000000 --- a/board/st/u8500/gpio.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* --- includes ----------------------------------------------------------- */ - -#include <asm/arch/gpio.h> - -static struct gpio_register *addr_gpio_register[GPIO_BLOCKS_COUNT]; - -int sz_altfun_tbl; - -struct gpio_altfun_data altfun_table[] = { - {.altfun = GPIO_ALT_I2C_0,.start = 147,.end = 148,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_I2C_1,.start = 16,.end = 17,.cont = 0,.type = - GPIO_ALTF_B,}, - {.altfun = GPIO_ALT_I2C_2,.start = 10,.end = 11,.cont = 0,.type = - GPIO_ALTF_B,}, - {.altfun = GPIO_ALT_I2C_3,.start = 229,.end = 230,.cont = 0,.type = - GPIO_ALTF_C,}, - {.altfun = GPIO_ALT_UART_0_MODEM,.start = 0,.end = 3,.cont = 1,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_UART_0_MODEM,.start = 33,.end = 36,.cont = 0,.type = - GPIO_ALTF_C,}, - {.altfun = GPIO_ALT_UART_1,.start = 4,.end = 7,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_UART_2,.start = 18,.end = 19,.cont = 1,.type = - GPIO_ALTF_B,}, - {.altfun = GPIO_ALT_UART_2,.start = 29,.end = 32,.cont = 0,.type = - GPIO_ALTF_C,}, - {.altfun = GPIO_ALT_MSP_0,.start = 12,.end = 17,.cont = 1,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_MSP_0,.start = 21,.end = 21,.cont = 0,.type = - GPIO_ALTF_B,}, - {.altfun = GPIO_ALT_MSP_1,.start = 33,.end = 36,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_MSP_2,.start = 192,.end = 196,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_LCD_PANEL,.start = 64,.end = 93,.cont = 1,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_LCD_PANEL,.start = 150,.end = 171,.cont = 0,.type = - GPIO_ALTF_B,}, - {.altfun = GPIO_ALT_SD_CARD0,.start = 18,.end = 28,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_MM_CARD0,.start = 18,.end = 32,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_USB_OTG,.start = 256,.end = 267,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_EMMC,.start = 197,.end = 207,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_POP_EMMC,.start = 128,.end = 138,.cont = 0,.type = - GPIO_ALTF_A,}, - {.altfun = GPIO_ALT_SPI_0,.start = 220,.end = 220,.cont = 1,.type = - GPIO_ALTF_C,}, - {.altfun = GPIO_ALT_SPI_0,.start = 223,.end = 225,.cont = 0,.type = - GPIO_ALTF_C,}, - {.altfun = GPIO_ALT_SPI_1,.start = 209,.end = 209,.cont = 1,.type = - GPIO_ALTF_B,}, - {.altfun = GPIO_ALT_SPI_1,.start = 212,.end = 214,.cont = 0,.type = - GPIO_ALTF_B,}, - {.altfun = GPIO_ALT_SPI_2,.start = 215,.end = 218,.cont = 0,.type = - GPIO_ALTF_C,}, - {.altfun = GPIO_ALT_SPI_3,.start = 29,.end = 32,.cont = 0,.type = - GPIO_ALTF_B,}, -}; - -/* - * Static Function declarations - */ -gpio_error gpio_setpinconfig(gpio_pin pin_id, gpio_config * config) -{ - struct gpio_register *p_gpio_register = addr_gpio_register[GPIO_BLOCK(pin_id)]; - u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); - gpio_error gpio_error = GPIO_OK; - u32 temp_reg; - - switch (config->mode) { - case GPIO_ALTF_A: - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg |= mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - break; - case GPIO_ALTF_B: - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg |= mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - break; - case GPIO_ALTF_C: - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg |= mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg |= mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - break; - case GPIO_MODE_SOFTWARE: - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - - switch (config->direction) { - case GPIO_DIR_INPUT: - writel(mask, &p_gpio_register->gpio_dirc); - break; - case GPIO_DIR_OUTPUT: - writel(mask, &p_gpio_register->gpio_dirs); - break; - case GPIO_DIR_LEAVE_UNCHANGED: - break; - default: - return (GPIO_INVALID_PARAMETER); - } - - break; - case GPIO_MODE_LEAVE_UNCHANGED: - break; - default: - return (GPIO_INVALID_PARAMETER); - } - return (gpio_error); -} - -gpio_error gpio_resetgpiopin(gpio_pin pin_id, char *dev_name) -{ - struct gpio_register *p_gpio_register = addr_gpio_register[GPIO_BLOCK(pin_id)]; - u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); - gpio_error gpio_error = GPIO_OK; - u32 temp_reg; - - temp_reg = readl(&p_gpio_register->gpio_afsa); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsa); - temp_reg = readl(&p_gpio_register->gpio_afsb); - temp_reg &= ~mask; - writel(temp_reg, &p_gpio_register->gpio_afsb); - writel(mask, &p_gpio_register->gpio_dirc); - - return (gpio_error); -} - -gpio_config altfun_pinconfig; -gpio_error gpio_altfunction(gpio_alt_function alt_func, - int which_altfunc, char *dev_name) -{ - int i, j, start, end; - gpio_error error = -1; - - for (i = 0; i < sz_altfun_tbl; i++) { - if (altfun_table[i].altfun != alt_func) - continue; - - start = altfun_table[i].start; - end = altfun_table[i].end; - for (j = start; j <= end; j++) { - if (which_altfunc == GPIO_ALTF_FIND) { - altfun_pinconfig.mode = - altfun_table[i].type; - } else { - altfun_pinconfig.mode = which_altfunc; - } - altfun_pinconfig.direction = GPIO_DIR_OUTPUT; - altfun_pinconfig.dev_name = dev_name; - - if (which_altfunc != GPIO_ALTF_DISABLE) { - error = - gpio_setpinconfig(j, - &altfun_pinconfig); - } else { - error = gpio_resetgpiopin(j, dev_name); - } - if (!error) - continue; - printf - ("GPIO %d configuration failure (nmdk_error:%d)", - j, error); - error = GPIO_INVALID_PARAMETER; - return (error); - } - - if (!altfun_table[i].cont) - break; - } - return (error); -} - -int gpio_writepin(gpio_pin pin_id, gpio_data value, char *dev_name) -{ - struct gpio_register *p_gpio_register = addr_gpio_register[GPIO_BLOCK(pin_id)]; - u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); - - switch (value) { - case GPIO_DATA_HIGH: - writel(mask, &p_gpio_register->gpio_dats); - break; - case GPIO_DATA_LOW: - writel(mask, &p_gpio_register->gpio_datc); - break; - default: - nmdk_error("Invalid value passed in %s", __FUNCTION__); - return GPIO_INVALID_PARAMETER; - } - return GPIO_OK; -} - -int gpio_readpin(gpio_pin pin_id, gpio_data * p_value) -{ - struct gpio_register *p_gpio_register = addr_gpio_register[GPIO_BLOCK(pin_id)]; - u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK); - - if ((readl(&p_gpio_register->gpio_dat) & mask) != 0) { - *p_value = GPIO_DATA_HIGH; - } else { - *p_value = GPIO_DATA_LOW; - } - return GPIO_OK; -} - - -int gpio_altfuncenable(gpio_alt_function altfunc, char *dev_name) -{ - return (int)gpio_altfunction(altfunc, GPIO_ALTF_FIND, dev_name); -} - -int gpio_altfuncdisable(gpio_alt_function altfunc, char *dev_name) -{ - return (int)gpio_altfunction(altfunc, GPIO_ALTF_DISABLE, dev_name); -} - -void gpio_init(void) -{ - - sz_altfun_tbl = sizeof(altfun_table) / sizeof(altfun_table[0]); - - addr_gpio_register[0] =(void *) IO_ADDRESS(CFG_GPIO_0_BASE); - addr_gpio_register[1] =(void *) IO_ADDRESS(CFG_GPIO_1_BASE); - addr_gpio_register[2] =(void *) IO_ADDRESS(CFG_GPIO_2_BASE); - addr_gpio_register[3] =(void *) IO_ADDRESS(CFG_GPIO_3_BASE); - addr_gpio_register[4] =(void *) IO_ADDRESS(CFG_GPIO_4_BASE); - addr_gpio_register[5] =(void *) IO_ADDRESS(CFG_GPIO_5_BASE); - addr_gpio_register[6] =(void *) IO_ADDRESS(CFG_GPIO_6_BASE); - addr_gpio_register[7] =(void *) IO_ADDRESS(CFG_GPIO_7_BASE); - addr_gpio_register[8] =(void *) IO_ADDRESS(CFG_GPIO_8_BASE); - - return; -} diff --git a/board/st/u8500/mcde_display.c b/board/st/u8500/mcde_display.c index f73a53a24..73847bf26 100644 --- a/board/st/u8500/mcde_display.c +++ b/board/st/u8500/mcde_display.c @@ -10,7 +10,6 @@ #include <common.h> #include <command.h> -#include <asm/arch/gpio.h> #include "mcde_display.h" #include "dsilink_regs.h" #include <tc35892.h> diff --git a/board/st/u8500/mcde_hw.c b/board/st/u8500/mcde_hw.c index e281d874c..d89a8eb52 100644 --- a/board/st/u8500/mcde_hw.c +++ b/board/st/u8500/mcde_hw.c @@ -9,8 +9,9 @@ #include <common.h> #include <command.h> +#include <asm/io.h> +#include <asm/arch/common.h> #include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> #include <tc35892.h> #include <malloc.h> diff --git a/board/st/u8500/mmc_host.c b/board/st/u8500/mmc_host.c index 8a2e0b3dd..a4f4de9bf 100644 --- a/board/st/u8500/mmc_host.c +++ b/board/st/u8500/mmc_host.c @@ -14,10 +14,10 @@ #define DBG_LVL_INFO (1) #define DBG_LVL_VERBOSE (2) +#include <asm/io.h> #include <asm/arch/common.h> #include <asm/arch/cpu.h> #include <mmc.h> -#include <asm/arch/gpio.h> #include "mmc_host.h" #include <malloc.h> #include <div64.h> @@ -449,15 +449,6 @@ struct mmc *alloc_mmc_struct(void) return NULL; } -static int host_poweroff(struct mmc *dev) -{ - struct mmc_host *host = dev->priv; - u32 sdi_pwr = ~SDI_PWR_PWRCTRL_ON; - debugX(DBG_LVL_VERBOSE, "SDI_PWR <= 0x%08X\n", sdi_pwr); - writel(sdi_pwr, &host->base->power); - return 0; -} - /* * emmc_host_init - initialize the emmc controller. * Configure GPIO settings, set initial clock and power for emmc slot. @@ -466,38 +457,15 @@ static int host_poweroff(struct mmc *dev) static int emmc_host_init(struct mmc *dev) { struct mmc_host *host = dev->priv; - gpio_error gpioerror; u32 sdi_u32; /* TODO: Investigate what is actually needed of the below. */ if (u8500_is_earlydrop()) { debugX(DBG_LVL_VERBOSE, "configuring EMMC for ED\n"); - /* Initialize the gpio alternate function for eMMC */ - struct gpio_register *p_gpio_register = - (void *)IO_ADDRESS(CFG_GPIO_6_BASE); - p_gpio_register->gpio_dats |= 0x0000FFE0; - p_gpio_register->gpio_pdis &= ~0x0000FFE0; - - gpioerror = gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC"); - if (GPIO_OK != gpioerror) { - printf( - "emmc_host_init() gpio_altfuncenable %d failed\n", - gpioerror); - goto end; - } - host->base = (struct sdi_registers *)CFG_EMMC_BASE_ED; } else { debugX(DBG_LVL_VERBOSE, "configuring EMMC for V1\n"); - /* enable the alternate function of PoP EMMC */ - gpioerror = gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC"); - if (gpioerror != GPIO_OK) { - printf( - "emmc_host_init() gpio_altfuncenable %d failed \n", - gpioerror); - goto end; - } host->base = (struct sdi_registers *)CFG_EMMC_BASE_V1; } @@ -524,15 +492,6 @@ static int emmc_host_init(struct mmc *dev) dev->f_max = MCLK / 2; dev->ddr_en = 0; return 0; - - end: - if (u8500_is_earlydrop()) - gpio_altfuncdisable(GPIO_ALT_EMMC, "EMMC"); - else - gpio_altfuncdisable(GPIO_ALT_POP_EMMC, "EMMC"); - - host_poweroff(dev); - return MMC_UNSUPPORTED_HW; } /* @@ -543,22 +502,8 @@ static int emmc_host_init(struct mmc *dev) static int mmc_host_init(struct mmc *dev) { struct mmc_host *host = dev->priv; - gpio_error gpioerror; - struct gpio_register *gpio_base_address; u32 sdi_u32; - gpio_base_address = (void *) IO_ADDRESS(CFG_GPIO_0_BASE); - gpio_base_address->gpio_dats |= 0xFFC0000; - gpio_base_address->gpio_pdis &= ~0xFFC0000; - - /* save the GPIO0 AFSELA register */ - gpioerror = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC"); - if (gpioerror != GPIO_OK) { - printf("mmc_host_init() gpio_altfuncenable %d failed \n", - gpioerror); - goto end; - } - host->base = (struct sdi_registers *)CFG_MMC_BASE; sdi_u32 = 0xBF; debugX(DBG_LVL_VERBOSE, "SDI_PWR <= 0x%08X\n", sdi_u32); @@ -583,11 +528,6 @@ static int mmc_host_init(struct mmc *dev) dev->f_max = MCLK / 2; dev->ddr_en = 0; return 0; - - end: - gpio_altfuncdisable(GPIO_ALT_SD_CARD0, "MMC"); - host_poweroff(dev); - return MMC_UNSUPPORTED_HW; } /* diff --git a/board/st/u8500/u8500.c b/board/st/u8500/u8500.c index 8177fadbe..a23056c55 100644 --- a/board/st/u8500/u8500.c +++ b/board/st/u8500/u8500.c @@ -17,10 +17,14 @@ #include <asm/arch/ab8500.h> #include <asm/arch/prcmu.h> #include <tc35892.h> -#include <asm/arch/gpio.h> #include "itp.h" #include <asm/arch/common.h> + +#include "db8500_pincfg.h" +#include "db8500_pins.h" + + #ifdef CONFIG_VIDEO_LOGO #include "mcde_display.h" #endif @@ -34,6 +38,90 @@ #define DMC_BASE_ADDR 0x80156000 #define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) +/* + * GPIO pin config for MOP500 board + */ +pin_cfg_t gpio_cfg[] = { + /* I2C */ + GPIO147_I2C0_SCL, + GPIO148_I2C0_SDA, + GPIO16_I2C1_SCL, + GPIO17_I2C1_SDA, + GPIO10_I2C2_SDA, + GPIO11_I2C2_SCL, + GPIO229_I2C3_SDA, + GPIO230_I2C3_SCL, + + /* SSP0, to AB8500 */ + GPIO143_SSP0_CLK, + GPIO144_SSP0_FRM, + GPIO145_SSP0_RXD | PIN_PULL_DOWN, + GPIO146_SSP0_TXD, + + /* MMC0 (MicroSD card) */ + GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, + GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, + GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, + GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, + GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, + GPIO23_MC0_CLK | PIN_OUTPUT_LOW, + GPIO24_MC0_CMD | PIN_INPUT_PULLUP, + GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, + GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, + GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, + GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, + + /* MMC2 (POP eMMC) */ + GPIO128_MC2_CLK | PIN_OUTPUT_LOW, + GPIO129_MC2_CMD | PIN_INPUT_PULLUP, + GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL, + GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP, + GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP, + GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP, + GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP, + GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP, + GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP, + GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP, + GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP, + + /* MMC4 (On-board eMMC) */ + GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, + GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, + GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, + GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, + GPIO201_MC4_CMD | PIN_INPUT_PULLUP, + GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, + GPIO203_MC4_CLK | PIN_OUTPUT_LOW, + GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, + GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, + GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, + GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, + + /* UART2, console */ + GPIO29_U2_RXD | PIN_INPUT_PULLUP, + GPIO30_U2_TXD | PIN_OUTPUT_HIGH, + GPIO31_U2_CTSn | PIN_INPUT_PULLUP, + GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, + + /* + * USB, pin 256-267 USB, Is probably already setup correctly from + * BootROM/boot stages, but we don't trust that and set it up anyway + */ + GPIO256_USB_NXT, + GPIO257_USB_STP, + GPIO258_USB_XCLK, + GPIO259_USB_DIR, + GPIO260_USB_DAT7, + GPIO261_USB_DAT6, + GPIO262_USB_DAT5, + GPIO263_USB_DAT4, + GPIO264_USB_DAT3, + GPIO265_USB_DAT2, + GPIO266_USB_DAT1, + GPIO267_USB_DAT0, +}; + + int board_id; /* set in board_late_init() */ int errno; @@ -98,8 +186,8 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_U8500; gd->bd->bi_boot_params = 0x00000100; - gpio_init(); - config_gpio(); + /* Configure GPIO pins needed by U-boot */ + db8500_gpio_config_pins(gpio_cfg, ARRAY_SIZE(gpio_cfg)); return 0; } @@ -376,42 +464,3 @@ int board_late_init(void) return (0); } #endif /* BOARD_LATE_INIT */ - -static void config_gpio(void) -{ - { - /* UART2: 29, 30 */ - struct gpio_register *p_gpio_register = (void *) IO_ADDRESS(CFG_GPIO_0_BASE); - p_gpio_register -> gpio_dats |= 0x60000000; - p_gpio_register -> gpio_pdis &= ~0x60000000; - } - gpio_altfuncenable(GPIO_ALT_UART_2, "UART2"); - - { - /* 197 - 207 */ - struct gpio_register *p_gpio_register = (void *) IO_ADDRESS(CFG_GPIO_6_BASE); - p_gpio_register -> gpio_dats |= 0x0000ffe0; - p_gpio_register -> gpio_pdis &= ~0x0000ffe0; - } - gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC"); - - { - /* 18 - 28 */ - struct gpio_register *p_gpio_register = (void *) IO_ADDRESS(CFG_GPIO_0_BASE); - // p_gpio_register -> gpio_dats |= 0x0ffc0000; - p_gpio_register -> gpio_pdis &= ~0x0ffc0000; - } - gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD"); - - if (!u8500_is_earlydrop()) { - { - /* 128 - 138 */ - struct gpio_register *p_gpio_register = (void *) IO_ADDRESS(CFG_GPIO_4_BASE); - p_gpio_register -> gpio_dats |= 0x000007ff; - p_gpio_register -> gpio_pdis &= ~0x000007ff; - } - - gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC"); - } -} - diff --git a/board/st/u8500/u8500_i2c.c b/board/st/u8500/u8500_i2c.c index f99f9ccf4..8e642ded4 100644 --- a/board/st/u8500/u8500_i2c.c +++ b/board/st/u8500/u8500_i2c.c @@ -16,7 +16,6 @@ /* later: #include <asm/arch/i2c.h> */ #include "i2c.h" -#include <asm/arch/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -52,16 +51,6 @@ static t_i2c_registers *i2c_dev[] = { }; static struct { - gpio_alt_function altfunc; - char *dev_name; -} i2c_gpio_altfunc[] = { - {GPIO_ALT_I2C_0, "i2c0"}, - {GPIO_ALT_I2C_1, "i2c1"}, - {GPIO_ALT_I2C_2, "i2c2"}, - {GPIO_ALT_I2C_3, "i2c3"}, -}; - -static struct { int periph; int pcken; int kcken; @@ -112,9 +101,6 @@ void i2c_init(int speed, int slaveaddr) debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed); - (void) gpio_altfuncenable(i2c_gpio_altfunc[i2c_bus_num].altfunc, - i2c_gpio_altfunc[i2c_bus_num].dev_name); - u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph, i2c_clock_bits[i2c_bus_num].pcken, i2c_clock_bits[i2c_bus_num].kcken); diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fc3ee5ea9..64f0bd718 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libgpio.a +COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/gpio/db8500_gpio.c b/drivers/gpio/db8500_gpio.c new file mode 100644 index 000000000..1ed4ba15d --- /dev/null +++ b/drivers/gpio/db8500_gpio.c @@ -0,0 +1,226 @@ +/* + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Original Linux authors: + * Copyright (C) 2008,2009 STMicroelectronics + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/io.h> + +#include <db8500_gpio.h> +#include <db8500_pincfg.h> + +/* + * Macros to work with IO space + * Not actually used? + */ +#define __iomem +#define IO_ADDR(x) (void *) (x) + +/* + * The GPIO module in the db8500 Systems-on-Chip is an + * AMBA device, managing 32 pins and alternate functions. The logic block + * is currently only used in the db8500. + */ + +#define GPIO_TOTAL_PINS 268 +#define GPIO_PINS_PER_BLOCK 32 +#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1) +#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1) +#define GPIO_PIN_WITHIN_BLOCK(pin) ((pin)%(GPIO_PINS_PER_BLOCK)) + +/* Register in the logic block */ +#define DB8500_GPIO_DAT 0x00 +#define DB8500_GPIO_DATS 0x04 +#define DB8500_GPIO_DATC 0x08 +#define DB8500_GPIO_PDIS 0x0c +#define DB8500_GPIO_DIR 0x10 +#define DB8500_GPIO_DIRS 0x14 +#define DB8500_GPIO_DIRC 0x18 +#define DB8500_GPIO_SLPC 0x1c +#define DB8500_GPIO_AFSLA 0x20 +#define DB8500_GPIO_AFSLB 0x24 + +#define DB8500_GPIO_RIMSC 0x40 +#define DB8500_GPIO_FIMSC 0x44 +#define DB8500_GPIO_IS 0x48 +#define DB8500_GPIO_IC 0x4c +#define DB8500_GPIO_RWIMSC 0x50 +#define DB8500_GPIO_FWIMSC 0x54 +#define DB8500_GPIO_WKS 0x58 + +static void __iomem *get_gpio_addr(unsigned gpio) +{ + /* Our list of GPIO chips */ + static void __iomem *gpio_addrs[GPIO_BLOCKS_COUNT] = { + IO_ADDR(CFG_GPIO_0_BASE), + IO_ADDR(CFG_GPIO_1_BASE), + IO_ADDR(CFG_GPIO_2_BASE), + IO_ADDR(CFG_GPIO_3_BASE), + IO_ADDR(CFG_GPIO_4_BASE), + IO_ADDR(CFG_GPIO_5_BASE), + IO_ADDR(CFG_GPIO_6_BASE), + IO_ADDR(CFG_GPIO_7_BASE), + IO_ADDR(CFG_GPIO_8_BASE) + }; + + return gpio_addrs[GPIO_BLOCK(gpio)]; +} + +static unsigned get_gpio_offset(unsigned gpio) +{ + return GPIO_PIN_WITHIN_BLOCK(gpio); +} + +/* Can only be called from config_pin. Don't configure alt-mode directly */ +static void gpio_set_mode(unsigned gpio, enum db8500_gpio_alt mode) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + u32 afunc, bfunc; + + afunc = readl(addr + DB8500_GPIO_AFSLA) & ~bit; + bfunc = readl(addr + DB8500_GPIO_AFSLB) & ~bit; + if (mode & DB8500_GPIO_ALT_A) + afunc |= bit; + if (mode & DB8500_GPIO_ALT_B) + bfunc |= bit; + writel(afunc, addr + DB8500_GPIO_AFSLA); + writel(bfunc, addr + DB8500_GPIO_AFSLB); +} + +/** + * db8500_gpio_set_pull() - enable/disable pull up/down on a gpio + * @gpio: pin number + * @pull: one of DB8500_GPIO_PULL_DOWN, DB8500_GPIO_PULL_UP, + * and DB8500_GPIO_PULL_NONE + * + * Enables/disables pull up/down on a specified pin. This only takes effect if + * the pin is configured as an input (either explicitly or by the alternate + * function). + * + * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is + * configured as an input. Otherwise, due to the way the controller registers + * work, this function will change the value output on the pin. + */ +void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + u32 pdis; + + pdis = readl(addr + DB8500_GPIO_PDIS); + if (pull == DB8500_GPIO_PULL_NONE) + pdis |= bit; + else + pdis &= ~bit; + writel(pdis, addr + DB8500_GPIO_PDIS); + + if (pull == DB8500_GPIO_PULL_UP) + writel(bit, addr + DB8500_GPIO_DATS); + else if (pull == DB8500_GPIO_PULL_DOWN) + writel(bit, addr + DB8500_GPIO_DATC); +} + +void db8500_gpio_make_input(unsigned gpio) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + writel(1 << offset, addr + DB8500_GPIO_DIRC); +} + +int db8500_gpio_get_input(unsigned gpio) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + + printf("db8500_gpio_get_input gpio=%u addr=%p offset=%u bit=%#x\n", + gpio, addr, offset, bit); + + return (readl(addr + DB8500_GPIO_DAT) & bit) != 0; +} + +void db8500_gpio_make_output(unsigned gpio, int val) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + writel(1 << offset, addr + DB8500_GPIO_DIRS); + db8500_gpio_set_output(gpio, val); +} + +void db8500_gpio_set_output(unsigned gpio, int val) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + if (val) + writel(1 << offset, addr + DB8500_GPIO_DATS); + else + writel(1 << offset, addr + DB8500_GPIO_DATC); +} + +/** + * config_pin - configure a pin's mux attributes + * @cfg: pin confguration + * + * Configures a pin's mode (alternate function or GPIO), its pull up status, + * and its sleep mode based on the specified configuration. The @cfg is + * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These + * are constructed using, and can be further enhanced with, the macros in + * plat/pincfg.h. + * + * If a pin's mode is set to GPIO, it is configured as an input to avoid + * side-effects. The gpio can be manipulated later using standard GPIO API + * calls. + */ +static void config_pin(pin_cfg_t cfg) +{ + int pin = PIN_NUM(cfg); + int pull = PIN_PULL(cfg); + int af = PIN_ALT(cfg); + int output = PIN_DIR(cfg); + int val = PIN_VAL(cfg); + + if (output) + db8500_gpio_make_output(pin, val); + else { + db8500_gpio_make_input(pin); + db8500_gpio_set_pull(pin, pull); + } + + gpio_set_mode(pin, af); +} + +/** + * db8500_config_pins - configure several pins at once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several pins using config_pin(). Refer to that function for + * further information. + */ +void db8500_gpio_config_pins(pin_cfg_t *cfgs, size_t num) +{ + size_t i; + + for (i = 0; i < num; i++) + config_pin(cfgs[i]); +} + diff --git a/drivers/spi/u8500_spi.c b/drivers/spi/u8500_spi.c index 3b1ae6a5e..a5f4422ce 100644 --- a/drivers/spi/u8500_spi.c +++ b/drivers/spi/u8500_spi.c @@ -13,7 +13,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> -#include <asm/arch/gpio.h> #include <spi.h> @@ -357,9 +356,6 @@ int spi_claim_bus(struct spi_slave *slave) { struct stm_spi_slave *sss = to_stm_spi_slave(slave); int ret = 0; - gpio_config pin_config; - gpio_pin clk_pin, frm_pin, txd_pin, rxd_pin; - gpio_alt_function altfunc; pr_dbg("slave 0x%p", slave); @@ -372,31 +368,16 @@ int spi_claim_bus(struct spi_slave *slave) switch (sss->slave.bus) { #if defined(SPI_0_BASE) && defined(CONFIG_U8500) case 0: - altfunc = GPIO_ALT_SPI_0; - clk_pin = GPIO_PIN_220; - frm_pin = GPIO_PIN_223; - txd_pin = GPIO_PIN_224; - rxd_pin = GPIO_PIN_225; u8500_clock_enable(2, 8, -1); break; #endif #if defined(SPI_1_BASE) && defined(CONFIG_U8500) case 1: - altfunc = GPIO_ALT_SPI_1; - clk_pin = GPIO_PIN_209; - frm_pin = GPIO_PIN_212; - txd_pin = GPIO_PIN_213; - rxd_pin = GPIO_PIN_214; u8500_clock_enable(2, 2, -1); break; #endif #if defined(SPI_2_BASE) && defined(CONFIG_U8500) case 2: - altfunc = GPIO_ALT_SPI_2; - clk_pin = GPIO_PIN_217; - frm_pin = GPIO_PIN_216; - txd_pin = GPIO_PIN_215; - rxd_pin = GPIO_PIN_218; u8500_clock_enable(2, 1, -1); /* @@ -412,11 +393,6 @@ int spi_claim_bus(struct spi_slave *slave) #endif #if defined(SPI_3_BASE) && defined(CONFIG_U8500) case 3: - altfunc = GPIO_ALT_SPI_3; - clk_pin = GPIO_PIN_29; - frm_pin = GPIO_PIN_31; - txd_pin = GPIO_PIN_32; - rxd_pin = GPIO_PIN_30; u8500_clock_enable(1, 7, -1); break; #endif @@ -447,57 +423,9 @@ int spi_claim_bus(struct spi_slave *slave) /* - * 3. Program the GPIO on which SPI port signals are attached to - * deliver the SPI signals by setting bits alternate function - * enable GPIO_AFSLAx = 1b in GPIO register. - * - * First the GPIO's are configured in software mode so - * the pull-up/pull-down configuration is correctly applied. - * After that pins are set to the correct alternate mode. + * 3. Program the GPIO on which SPI port signals are attached to. + * This should already be done by the Board GPIO setup */ - pin_config.dev_name = "SPI_CLK"; - pin_config.direction = GPIO_DIR_OUTPUT; - pin_config.mode = GPIO_MODE_SOFTWARE; - pin_config.trig = GPIO_TRIG_DISABLE; - ret = gpio_setpinconfig(clk_pin, &pin_config); - if (ret != 0) { - pr_err("Error %i when configuring '%s' (pin %i) for '%s'", - ret, pin_config.dev_name, clk_pin, sss->dev_name); - return ret; - } - - pin_config.dev_name = "SPI_FRM"; - ret = gpio_setpinconfig(frm_pin, &pin_config); - if (ret != 0) { - pr_err("Error %i when configuring '%s' (pin %i) for '%s'", - ret, pin_config.dev_name, frm_pin, sss->dev_name); - return ret; - } - - pin_config.dev_name = "SPI_TXD"; - ret = gpio_setpinconfig(txd_pin, &pin_config); - if (ret != 0) { - pr_err("Error %i when configuring '%s' (pin %i) for '%s'", - ret, pin_config.dev_name, txd_pin, sss->dev_name); - return ret; - } - - pin_config.dev_name = "SPI_RXD"; - pin_config.direction = GPIO_DIR_INPUT; - ret = gpio_setpinconfig(rxd_pin, &pin_config); - if (ret != 0) { - pr_err("Error %i when configuring '%s' (pin %i) for '%s'", - ret, pin_config.dev_name, rxd_pin, sss->dev_name); - return ret; - } - - ret = gpio_altfuncenable(altfunc, sss->dev_name); - if (ret != 0) { - pr_err("Error %i when configuring '%s' to %i", - ret, sss->dev_name, altfunc); - return ret; - } - /* * 4. Program the SPI clock prescale register, SPI_CPSR, diff --git a/drivers/usb/gadget/u8500_udc.c b/drivers/usb/gadget/u8500_udc.c index 109e11dda..92f1b57c8 100755 --- a/drivers/usb/gadget/u8500_udc.c +++ b/drivers/usb/gadget/u8500_udc.c @@ -21,7 +21,6 @@ #include <common.h> #include "u8500_udc.h" -#include <asm/arch/gpio.h> static volatile struct mg_dev_register *pRegs = 0; @@ -32,8 +31,6 @@ int udc_musb_platform_init(void) u8 soft_reset; u16 temp; pRegs = (volatile struct mg_dev_register *) CONFIG_USB_BASE; - - gpio_altfuncenable(GPIO_ALT_USB_OTG, "USB-OTG"); top = pRegs->OTG_TOPCTRL; pRegs->OTG_TOPCTRL = (top | MODE_ULPI); diff --git a/include/asm-arm/arch-db8500/common.h b/include/asm-arm/arch-db8500/common.h index 81f100a50..42fb8928f 100644 --- a/include/asm-arm/arch-db8500/common.h +++ b/include/asm-arm/arch-db8500/common.h @@ -127,7 +127,5 @@ typedef u32 t_physical_address; typedef u32 t_logical_address; /*function prototypes*/ -void gpio_init(void); - int board_early_access(block_dev_desc_t *block_dev); #endif /* _DB8500_COMMON_H_ */ diff --git a/include/asm-arm/arch-db8500/gpio.h b/include/asm-arm/arch-db8500/gpio.h deleted file mode 100644 index fbff7fcb6..000000000 --- a/include/asm-arm/arch-db8500/gpio.h +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _MOP500_GPIO_h -#define _MOP500_GPIO_h - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/errno.h> - -#include <asm/arch/common.h> - -#define GPIO_TOTAL_PINS 268 - -#define GPIO_PINS_PER_BLOCK 32 -#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK +1) -#define GPIO_BLOCK(pin) ( ( ( pin + GPIO_PINS_PER_BLOCK ) >> 5) - 1 ) - - -struct gpio_register { - u32 gpio_dat; /* GPIO data register *//*0x000 */ - u32 gpio_dats; /* GPIO data Set register *//*0x004 */ - u32 gpio_datc; /* GPIO data Clear register *//*0x008 */ - u32 gpio_pdis; /* GPIO Pull disable register *//*0x00C */ - u32 gpio_dir; /* GPIO data direction register *//*0x010 */ - u32 gpio_dirs; /* GPIO data dir Set register *//*0x014 */ - u32 gpio_dirc; /* GPIO data dir Clear register *//*0x018 */ - u32 gpio_slpm; /* GPIO Sleep mode register *//*0x01C */ - u32 gpio_afsa; /* GPIO AltFun A Select reg *//*0x020 */ - u32 gpio_afsb; /* GPIO AltFun B Select reg *//*0x024 */ - u32 gpio_lowemi; /* GPIO low EMI Select reg *//*0x028 */ - u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/ - u32 gpio_rimsc; /* GPIO rising edge intr set/clear *//*0x040 */ - u32 gpio_fimsc; /* GPIO falling edge interrupt set/clear register *//*0x044 */ - u32 gpio_mis; /* GPIO masked interrupt status register *//*0x048 */ - u32 gpio_ic; /* GPIO Interrupt Clear register *//*0x04C */ - u32 gpio_rwimsc; /* GPIO Rising-edge Wakeup IMSC register *//*0x050 */ - u32 gpio_fwimsc; /* GPIO Falling-edge Wakeup IMSC register *//*0x054 */ - u32 gpio_wks; /* GPIO Wakeup Status register *//*0x058 */ -}; - -/* Error values returned by functions */ -typedef enum { - GPIO_OK = 0, /* (0) */ - GPIO_UNSUPPORTED_HW = -2, /* NOMADIK_UNSUPPORTED_HW, (-2) */ - GPIO_UNSUPPORTED_FEATURE = -3, /* NOMADIK_UNSUPPORTED_FEATURE, (-3) */ - GPIO_INVALID_PARAMETER = -4, /* NOMADIK_INVALID_PARAMETER, (-4) */ - GPIO_REQUEST_NOT_APPLICABLE = -5, /* NOMADIK_REQUEST_NOT_APPLICABLE, (-5) */ - GPIO_REQUEST_PENDING = -6, /* NOMADIK_REQUEST_PENDING, (-6) */ - GPIO_NOT_CONFIGURED = -7, /* NOMADIK_NOT_CONFIGURED, (-7) */ - GPIO_INTERNAL_ERROR = -8, /* NOMADIK_INTERNAL_ERROR, (-8) */ - GPIO_INTERNAL_EVENT = 1, /* NOMADIK_INTERNAL_EVENT,*/ - GPIO_REMAINING_EVENT = 2, /* NOMADIK_REMAINING_PENDING_EVENTS,*/ - GPIO_NO_MORE_PENDING_EVENT = 3, /* NOMADIK_NO_MORE_PENDING_EVENT,*/ - GPIO_INVALID_CLIENT = -25, - GPIO_INVALID_PIN = -26, - GPIO_PIN_BUSY = -27, - GPIO_PIN_NOT_ALLOCATED = -28, - GPIO_WRONG_CLIENT = -29, - GPIO_UNSUPPORTED_ALTFUNC = -30, - -} gpio_error; - -/*GPIO DEVICE ID */ -typedef enum { - GPIO_DEVICE_ID_0, - GPIO_DEVICE_ID_1, - GPIO_DEVICE_ID_2, - GPIO_DEVICE_ID_3, - GPIO_DEVICE_ID_INVALID -} gpio_device_id; - -/* - * Pin description To be used in SOFTWARE mode: refers to a pin. - */ -typedef enum { - GPIO_PIN_0, - GPIO_PIN_1, - GPIO_PIN_2, - GPIO_PIN_3, - GPIO_PIN_4, - GPIO_PIN_5, - GPIO_PIN_6, - GPIO_PIN_7, - GPIO_PIN_8, - GPIO_PIN_9, - GPIO_PIN_10, - GPIO_PIN_11, - GPIO_PIN_12, - GPIO_PIN_13, - GPIO_PIN_14, - GPIO_PIN_15, - GPIO_PIN_16, - GPIO_PIN_17, - GPIO_PIN_18, - GPIO_PIN_19, - GPIO_PIN_20, - GPIO_PIN_21, - GPIO_PIN_22, - GPIO_PIN_23, - GPIO_PIN_24, - GPIO_PIN_25, - GPIO_PIN_26, - GPIO_PIN_27, - GPIO_PIN_28, - GPIO_PIN_29, - GPIO_PIN_30, - GPIO_PIN_31, - GPIO_PIN_32, - GPIO_PIN_33, - GPIO_PIN_34, - GPIO_PIN_35, - GPIO_PIN_36, - GPIO_PIN_37, - GPIO_PIN_38, - GPIO_PIN_39, - GPIO_PIN_40, - GPIO_PIN_41, - GPIO_PIN_42, - GPIO_PIN_43, - GPIO_PIN_44, - GPIO_PIN_45, - GPIO_PIN_46, - GPIO_PIN_47, - GPIO_PIN_48, - GPIO_PIN_49, - GPIO_PIN_50, - GPIO_PIN_51, - GPIO_PIN_52, - GPIO_PIN_53, - GPIO_PIN_54, - GPIO_PIN_55, - GPIO_PIN_56, - GPIO_PIN_57, - GPIO_PIN_58, - GPIO_PIN_59, - GPIO_PIN_60, - GPIO_PIN_61, - GPIO_PIN_62, - GPIO_PIN_63, - GPIO_PIN_64, - GPIO_PIN_65, - GPIO_PIN_66, - GPIO_PIN_67, - GPIO_PIN_68, - GPIO_PIN_69, - GPIO_PIN_70, - GPIO_PIN_71, - GPIO_PIN_72, - GPIO_PIN_73, - GPIO_PIN_74, - GPIO_PIN_75, - GPIO_PIN_76, - GPIO_PIN_77, - GPIO_PIN_78, - GPIO_PIN_79, - GPIO_PIN_80, - GPIO_PIN_81, - GPIO_PIN_82, - GPIO_PIN_83, - GPIO_PIN_84, - GPIO_PIN_85, - GPIO_PIN_86, - GPIO_PIN_87, - GPIO_PIN_88, - GPIO_PIN_89, - GPIO_PIN_90, - GPIO_PIN_91, - GPIO_PIN_92, - GPIO_PIN_93, - GPIO_PIN_94, - GPIO_PIN_95, - GPIO_PIN_96, - GPIO_PIN_97, - GPIO_PIN_98, - GPIO_PIN_99, - GPIO_PIN_100, - GPIO_PIN_101, - GPIO_PIN_102, - GPIO_PIN_103, - GPIO_PIN_104, - GPIO_PIN_105, - GPIO_PIN_106, - GPIO_PIN_107, - GPIO_PIN_108, - GPIO_PIN_109, - GPIO_PIN_110, - GPIO_PIN_111, - GPIO_PIN_112, - GPIO_PIN_113, - GPIO_PIN_114, - GPIO_PIN_115, - GPIO_PIN_116, - GPIO_PIN_117, - GPIO_PIN_118, - GPIO_PIN_119, - GPIO_PIN_120, - GPIO_PIN_121, - GPIO_PIN_122, - GPIO_PIN_123, - GPIO_PIN_124, - GPIO_PIN_125, - GPIO_PIN_126, - GPIO_PIN_127, - GPIO_PIN_128, - GPIO_PIN_129, - GPIO_PIN_130, - GPIO_PIN_131, - GPIO_PIN_132, - GPIO_PIN_133, - GPIO_PIN_134, - GPIO_PIN_135, - GPIO_PIN_136, - GPIO_PIN_137, - GPIO_PIN_138, - GPIO_PIN_139, - GPIO_PIN_140, - GPIO_PIN_141, - GPIO_PIN_142, - GPIO_PIN_143, - GPIO_PIN_144, - GPIO_PIN_145, - GPIO_PIN_146, - GPIO_PIN_147, - GPIO_PIN_148, - GPIO_PIN_149, - GPIO_PIN_150, - GPIO_PIN_151, - GPIO_PIN_152, - GPIO_PIN_153, - GPIO_PIN_154, - GPIO_PIN_155, - GPIO_PIN_156, - GPIO_PIN_157, - GPIO_PIN_158, - GPIO_PIN_159, - GPIO_PIN_160, - GPIO_PIN_161, - GPIO_PIN_162, - GPIO_PIN_163, - GPIO_PIN_164, - GPIO_PIN_165, - GPIO_PIN_166, - GPIO_PIN_167, - GPIO_PIN_168, - GPIO_PIN_169, - GPIO_PIN_170, - GPIO_PIN_171, - GPIO_PIN_172, - GPIO_PIN_173, - GPIO_PIN_174, - GPIO_PIN_175, - GPIO_PIN_176, - GPIO_PIN_177, - GPIO_PIN_178, - GPIO_PIN_179, - GPIO_PIN_180, - GPIO_PIN_181, - GPIO_PIN_182, - GPIO_PIN_183, - GPIO_PIN_184, - GPIO_PIN_185, - GPIO_PIN_186, - GPIO_PIN_187, - GPIO_PIN_188, - GPIO_PIN_189, - GPIO_PIN_190, - GPIO_PIN_191, - GPIO_PIN_192, - GPIO_PIN_193, - GPIO_PIN_194, - GPIO_PIN_195, - GPIO_PIN_196, - GPIO_PIN_197, - GPIO_PIN_198, - GPIO_PIN_199, - GPIO_PIN_200, - GPIO_PIN_201, - GPIO_PIN_202, - GPIO_PIN_203, - GPIO_PIN_204, - GPIO_PIN_205, - GPIO_PIN_206, - GPIO_PIN_207, - GPIO_PIN_208, - GPIO_PIN_209, - GPIO_PIN_210, - GPIO_PIN_211, - GPIO_PIN_212, - GPIO_PIN_213, - GPIO_PIN_214, - GPIO_PIN_215, - GPIO_PIN_216, - GPIO_PIN_217, - GPIO_PIN_218, - GPIO_PIN_219, - GPIO_PIN_220, - GPIO_PIN_221, - GPIO_PIN_222, - GPIO_PIN_223, - GPIO_PIN_224, - GPIO_PIN_225, - GPIO_PIN_226, - GPIO_PIN_227, - GPIO_PIN_228, - GPIO_PIN_229, - GPIO_PIN_230, - GPIO_PIN_231, - GPIO_PIN_232, - GPIO_PIN_233, - GPIO_PIN_234, - GPIO_PIN_235, - GPIO_PIN_236, - GPIO_PIN_237, - GPIO_PIN_238, - GPIO_PIN_239, - GPIO_PIN_240, - GPIO_PIN_241, - GPIO_PIN_242, - GPIO_PIN_243, - GPIO_PIN_244, - GPIO_PIN_245, - GPIO_PIN_246, - GPIO_PIN_247, - GPIO_PIN_248, - GPIO_PIN_249, - GPIO_PIN_250, - GPIO_PIN_251, - GPIO_PIN_252, - GPIO_PIN_253, - GPIO_PIN_254, - GPIO_PIN_255, - GPIO_PIN_256, - GPIO_PIN_257, - GPIO_PIN_258, - GPIO_PIN_259, - GPIO_PIN_260, - GPIO_PIN_261, - GPIO_PIN_262, - GPIO_PIN_263, - GPIO_PIN_264, - GPIO_PIN_265, - GPIO_PIN_266, - GPIO_PIN_267 -} gpio_pin; - -/* - * Alternate Function: - * refered in altfun_table to pointout particular altfun to be enabled - * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation - */ -typedef enum { - GPIO_ALT_UART_0_MODEM, - GPIO_ALT_UART_0_NO_MODEM, - GPIO_ALT_UART_1, - GPIO_ALT_UART_2, - GPIO_ALT_I2C_0, - GPIO_ALT_I2C_1, - GPIO_ALT_I2C_2, - GPIO_ALT_I2C_3, - GPIO_ALT_MSP_0, - GPIO_ALT_MSP_1, - GPIO_ALT_MSP_2, - GPIO_ALT_MSP_3, - GPIO_ALT_MSP_4, - GPIO_ALT_MSP_5, - GPIO_ALT_SSP_0, - GPIO_ALT_SSP_1, - GPIO_ALT_MM_CARD0, - GPIO_ALT_SD_CARD0, - GPIO_ALT_DMA_0, - GPIO_ALT_DMA_1, - GPIO_ALT_HSI0, - GPIO_ALT_CCIR656_INPUT, - GPIO_ALT_CCIR656_OUTPUT, - GPIO_ALT_LCD_PANEL, - GPIO_ALT_MDIF, - GPIO_ALT_SDRAM, - GPIO_ALT_HAMAC_AUDIO_DBG, - GPIO_ALT_HAMAC_VIDEO_DBG, - GPIO_ALT_CLOCK_RESET, - GPIO_ALT_TSP, - GPIO_ALT_IRDA, - GPIO_ALT_USB_MINIMUM, - GPIO_ALT_USB_I2C, - GPIO_ALT_OWM, - GPIO_ALT_PWL, - GPIO_ALT_FSMC, - GPIO_ALT_COMP_FLASH, - GPIO_ALT_SRAM_NOR_FLASH, - GPIO_ALT_FSMC_ADDLINE_0_TO_15, - GPIO_ALT_SCROLL_KEY, - GPIO_ALT_MSHC, - GPIO_ALT_HPI, - GPIO_ALT_USB_OTG, - GPIO_ALT_SDIO, - GPIO_ALT_HSMMC, - GPIO_ALT_FSMC_ADD_DATA_0_TO_25, - GPIO_ALT_HSI1, - GPIO_ALT_NOR, - GPIO_ALT_NAND, - GPIO_ALT_KEYPAD, - GPIO_ALT_VPIP, - GPIO_ALT_CAM, - GPIO_ALT_CCP1, - GPIO_ALT_EMMC, - GPIO_ALT_POP_EMMC, - GPIO_ALT_SPI_0, - GPIO_ALT_SPI_1, - GPIO_ALT_SPI_2, - GPIO_ALT_SPI_3, - GPIO_ALT_FUNMAX /* Add new alt func before this */ -} gpio_alt_function; - -/* Defines pin assignment(Software mode or Alternate mode) */ -typedef enum { - GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ - GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */ - GPIO_ALTF_A, /* Pin connected to alternate function 1 (HW periph 1) */ - GPIO_ALTF_B, /* Pin connected to alternate function 2 (HW periph 2) */ - GPIO_ALTF_C, /* Pin connected to alternate function 3 (HW periph 3) */ - GPIO_ALTF_FIND, /* Pin connected to alternate function 3 (HW periph 3) */ - GPIO_ALTF_DISABLE /* Pin connected to alternate function 3 (HW periph 3) */ -} gpio_mode; - -/* Defines GPIO pin direction */ -typedef enum { - GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ - GPIO_DIR_INPUT, /* GPIO set as input */ - GPIO_DIR_OUTPUT /* GPIO set as output */ -} gpio_direction; - -/* Interrupt trigger mode */ -typedef enum { - GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored by the function */ - GPIO_TRIG_DISABLE, /* Triggers no IT */ - GPIO_TRIG_RISING_EDGE, /* Triggers an IT on a rising edge */ - GPIO_TRIG_FALLING_EDGE, /* Triggers an IT on a falling edge */ - GPIO_TRIG_BOTH_EDGES, /* Triggers an IT on a rising and a falling edge */ - GPIO_TRIG_HIGH_LEVEL, /* Triggers an IT on a high level */ - GPIO_TRIG_LOW_LEVEL /* Triggers an IT on a low level */ -} gpio_trig; /* Interrupt trigger mode, or disable */ - -/* Configuration parameters for one GPIO pin.*/ -typedef struct { - gpio_mode mode; /* Defines mode (SOFTWARE or Alternate). */ - gpio_direction direction; /* Define pin direction (in SOFTWARE mode only). */ - gpio_trig trig; /* Interrupt trigger (in SOFTWARE mode only) */ - char *dev_name; /* Name of client driver who owns the gpio pin */ -} gpio_config; - -/* GPIO pin data*/ -typedef enum { - GPIO_DATA_LOW, /* GPIO pin status is low. */ - GPIO_DATA_HIGH /* GPIO pin status is high. */ -} gpio_data; - -/* GPIO behaviour in sleep mode */ -typedef enum { - GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ - GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull up/down enabled - when in sleep mode. */ - GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by GPIO IP. So mode, - direction and data values for GPIO pin in - sleep mode are determined by configuration - set to GPIO pin before entering to sleep mode. */ -} gpio_sleep_mode; - -/* GPIO ability to wake the system up from sleep mode.*/ -typedef enum { - GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ - GPIO_WAKE_DISABLE, /* GPIO will not wake the system from sleep mode. */ - GPIO_WAKE_LOW_LEVEL, /* GPIO will wake the system up on a LOW level. */ - GPIO_WAKE_HIGH_LEVEL, /* GPIO will wake the system up on a HIGH level. */ - GPIO_WAKE_RISING_EDGE, /* GPIO will wake the system up on a RISING edge. */ - GPIO_WAKE_FALLING_EDGE, /* GPIO will wake the system up on a FALLING edge. */ - GPIO_WAKE_BOTH_EDGES /* GPIO will wake the system up on both RISING and FALLING edge. */ -} gpio_wake; - -/* Configuration parameters for one GPIO pin in sleep mode.*/ -typedef struct { - gpio_sleep_mode sleep_mode; /* GPIO behaviour in sleep mode. */ - gpio_wake wake; /* GPIO ability to wake up the system. */ -} gpio_sleep_config; - -/*------------------------------------------------------------------------ - * Functions declaration - * refer ./Documentation/arm/STM-Nomadik/gpio_user_guide.txt - *----------------------------------------------------------------------*/ - -extern gpio_error gpio_setpinconfig(gpio_pin pin_id, gpio_config * pin_config); -extern gpio_error gpio_resetpinconfig(gpio_pin pin_id, char *dev_name); -extern int gpio_writepin(gpio_pin pin_id, gpio_data value, char *dev_name); -extern int gpio_readpin(gpio_pin pin_id, gpio_data * value); -extern int gpio_altfuncenable(gpio_alt_function altfunc, - char *dev_name); -extern int gpio_altfuncdisable(gpio_alt_function altfunc, - char *dev_name); - -struct gpio_altfun_data { - u16 altfun; - u16 start; - u16 end; - t_bool cont; - u8 type; -}; - -#endif /* __INC_GPIO_H */ diff --git a/include/configs/u8500.h b/include/configs/u8500.h index 7a0284c0b..0bca0dcf6 100644 --- a/include/configs/u8500.h +++ b/include/configs/u8500.h @@ -309,6 +309,7 @@ /* * U8500 GPIO register base for 9 banks */ +#define CONFIG_DB8500_GPIO #define CFG_GPIO_0_BASE 0x8012E000 #define CFG_GPIO_1_BASE 0x8012E080 #define CFG_GPIO_2_BASE 0x8000E000 diff --git a/include/db8500_gpio.h b/include/db8500_gpio.h new file mode 100644 index 000000000..67d7e4d56 --- /dev/null +++ b/include/db8500_gpio.h @@ -0,0 +1,43 @@ +/* + * Structures and registers for GPIO access in the Nomadik SoC + * + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + * Copyright (C) 2008 STMicroelectronics + * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DB8500_GPIO_H__ +#define __DB8500_GPIO_H__ + +/* Alternate functions: function C is set in hw by setting both A and B */ +enum db8500_gpio_alt { + DB8500_GPIO_ALT_GPIO = 0, + DB8500_GPIO_ALT_A = 1, + DB8500_GPIO_ALT_B = 2, + DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B) +}; + +enum db8500_gpio_pull { + DB8500_GPIO_PULL_NONE, + DB8500_GPIO_PULL_UP, + DB8500_GPIO_PULL_DOWN +}; + +void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull); +void db8500_gpio_make_input(unsigned gpio); +int db8500_gpio_get_input(unsigned gpio); +void db8500_gpio_make_output(unsigned gpio, int val); +void db8500_gpio_set_output(unsigned gpio, int val); + +#endif /* __DB8500_GPIO_H__ */ + diff --git a/include/db8500_pincfg.h b/include/db8500_pincfg.h new file mode 100644 index 000000000..d1bcb65a9 --- /dev/null +++ b/include/db8500_pincfg.h @@ -0,0 +1,173 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. Ported 2010 to U-boot by: + * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com> + * + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * + * + * Based on arch/arm/mach-pxa/include/mach/mfp.h: + * Copyright (C) 2007 Marvell International Ltd. + * eric miao <eric.miao@marvell.com> + */ + +#ifndef __DB8500_PINCFG_H +#define __DB8500_PINCFG_H + +#include "db8500_gpio.h" + +/* + * U-boot info: + * SLPM (sleep mode) config will be ignored by U-boot but it is still + * possible to configure it in order to keep cut-n-paste compability + * with Linux kernel config. + * + * pin configurations are represented by 32-bit integers: + * + * bit 0.. 8 - Pin Number (512 Pins Maximum) + * bit 9..10 - Alternate Function Selection + * bit 11..12 - Pull up/down state + * bit 13 - Sleep mode behaviour (not used in U-boot) + * bit 14 - Direction + * bit 15 - Value (if output) + * bit 16..18 - SLPM pull up/down state (not used in U-boot) + * bit 19..20 - SLPM direction (not used in U-boot) + * bit 21..22 - SLPM Value (if output) (not used in U-boot) + * + * to facilitate the definition, the following macros are provided + * + * PIN_CFG_DEFAULT - default config (0): + * pull up/down = disabled + * sleep mode = input/wakeup + * direction = input + * value = low + * SLPM direction = same as normal + * SLPM pull = same as normal + * SLPM value = same as normal + * + * PIN_CFG - default config with alternate function + * PIN_CFG_PULL - default config with alternate function and pull up/down + */ + +typedef unsigned long pin_cfg_t; + +/* Sleep mode */ +enum db8500_gpio_slpm { + DB8500_GPIO_SLPM_INPUT, + DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT, + DB8500_GPIO_SLPM_NOCHANGE, + DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE, +}; + +#define PIN_NUM_MASK 0x1ff +#define PIN_NUM(x) ((x) & PIN_NUM_MASK) + +#define PIN_ALT_SHIFT 9 +#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) +#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) +#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT) +#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT) +#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT) +#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT) + +#define PIN_PULL_SHIFT 11 +#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) +#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) +#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT) +#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT) +#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT) + +#define PIN_SLPM_SHIFT 13 +#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) +#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) +#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) +#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) +/* These two replace the above in DB8500v2+ */ +#define PIN_SLPM_WAKEUP_ENABLE \ + (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_WAKEUP_DISABLE \ + (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) + +#define PIN_DIR_SHIFT 14 +#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) +#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) +#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) +#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) + +#define PIN_VAL_SHIFT 15 +#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) +#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) +#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) +#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) + +#define PIN_SLPM_PULL_SHIFT 16 +#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL(x) \ + (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_NONE \ + ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_UP \ + ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_DOWN \ + ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) + +#define PIN_SLPM_DIR_SHIFT 19 +#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR(x) \ + (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) + +#define PIN_SLPM_VAL_SHIFT 21 +#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL(x) \ + (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) + +/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ +#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) +#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) +#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) +#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) +#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) + +#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) +#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) +#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) +#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) +#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) + +#define PIN_CFG_DEFAULT (0) + +#define PIN_CFG(num, alt) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt)) + +#define PIN_CFG_INPUT(num, alt, pull) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) + +#define PIN_CFG_OUTPUT(num, alt, val) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) + +#define PIN_CFG_PULL(num, alt, pull) \ + ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ + (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) + +/** + * db8500_gpio_config_pins - configure several pins at once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several GPIO pins. + */ +void db8500_gpio_config_pins(pin_cfg_t *cfgs, size_t num); + +#endif + |