diff options
| -rw-r--r-- | board/st/u8500/u8500.c | 49 | ||||
| -rw-r--r-- | include/configs/u8500.h | 16 |
2 files changed, 56 insertions, 9 deletions
diff --git a/board/st/u8500/u8500.c b/board/st/u8500/u8500.c index 5bd11a4dc..b5c5e60a7 100644 --- a/board/st/u8500/u8500.c +++ b/board/st/u8500/u8500.c @@ -60,6 +60,12 @@ #define PRCM_TCR (PRCMU_BASE + 0x1C8) +/* + * Memory controller register + */ +#define DMC_BASE_ADDR 0x80156000 +#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) + int board_id; /* set in board_late_init() */ /* PLLs for clock management registers */ @@ -170,9 +176,32 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE_1; - return 0; + uint32_t unused_cols_rows; + unsigned int nrows; + unsigned int ncols; + + gd->bd->bi_dram[0].start = 0; + if (u8500_is_earlydrop()) { + gd->bd->bi_dram[0].size = 0x10000000; /* 256 MiB */ + return 0; + } + + /* + * Assumption: 2 CS active, both CS have same layout. + * 15 rows max, 11 cols max (controller spec). + * memory chip has 8 banks, I/O width 32 bit. + * The correct way would be to read MR#8: I/O width and density, + * but this requires locking against the PRCMU firmware. + * Simplified approach: + * Read number of unused rows and columns from mem controller. + * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes + */ + unused_cols_rows = readl(DMC_CTL_97); + nrows = 15 - (unused_cols_rows & 0xff); + ncols = 11 - ((unused_cols_rows & 0xff00) >> 8); + gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4; + + return 0; } #ifdef CONFIG_VIDEO_LOGO @@ -358,6 +387,20 @@ int board_late_init(void) #ifdef CONFIG_VIDEO_LOGO dss_init(); #endif + /* + * Create a memargs variable which points uses either the memargs256 or + * memargs512 environment variable, depending on the memory size. + * memargs is used to build the bootargs, memargs256 and memargs512 are + * stored in the environment. + */ + if (gd->bd->bi_dram[0].size == 0x10000000) { + setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}"); + setenv("mem", "256M"); + } else { + setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}"); + setenv("mem", "512M"); + } + return (0); } #endif /* BOARD_LATE_INIT */ diff --git a/include/configs/u8500.h b/include/configs/u8500.h index b829de92b..7ae82dc2d 100644 --- a/include/configs/u8500.h +++ b/include/configs/u8500.h @@ -120,9 +120,13 @@ "verify=n\0" \ "loadaddr=0x00100000\0" \ "console=ttyAMA2,115200n8\0" \ + "memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M " \ + "pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0" \ + "memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M " \ + "pmem=22M@172M mem=30M@194M mem_mali=32M@224M " \ + "pmem_hwb=54M@256M mem=202M@310M\0" \ "commonargs=setenv bootargs cachepolicy=writealloc noinitrd " \ - "init=init mem=96M@0 mem=34M@128M " \ - "pmem=22M@162M pmem_mio=8M@184M pmem_hwb=32M@192M " \ + "init=init " \ "board_id=${board_id} " \ "logo.${logo} " \ "startup_graphics=${startup_graphics}\0" \ @@ -132,8 +136,8 @@ "addcons=setenv bootargs ${bootargs} " \ "console=${console}\0" \ "emmcboot=echo Booting from eMMC ...; " \ - "run commonargs emmcargs addcons;" \ - "emmc_read ${loadaddr} 0x14000000 0x200000; " \ + "run commonargs emmcargs addcons memargs;" \ + "emmc_read ${loadaddr} 0x14000000 0x300000; " \ "bootm ${loadaddr}\0" \ "cmdfile=mmc init 1;mmc_read_cmd_file;run bootcmd\0" \ "flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;" \ @@ -150,12 +154,12 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ |