diff options
Diffstat (limited to 'cpu/arm926ejs/davinci/psc.c')
| -rw-r--r-- | cpu/arm926ejs/davinci/psc.c | 103 |
1 files changed, 28 insertions, 75 deletions
diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c index 28e2a4b5b..5bb972f18 100644 --- a/cpu/arm926ejs/davinci/psc.c +++ b/cpu/arm926ejs/davinci/psc.c @@ -26,22 +26,22 @@ #include <common.h> #include <asm/arch/hardware.h> -#define PINMUX0_EMACEN (1 << 31) -#define PINMUX0_AECS5 (1 << 11) -#define PINMUX0_AECS4 (1 << 10) - -#define PINMUX1_I2C (1 << 7) -#define PINMUX1_UART1 (1 << 1) -#define PINMUX1_UART0 (1 << 0) - /* - * The DM6446 includes two separate power domains: "Always On" and "DSP". The - * "Always On" power domain is always on when the chip is on. The "Always On" - * domain is powered by the VDD pins of the DM6446. The majority of the - * DM6446's modules lie within the "Always On" power domain. A separate - * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain - * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of - * the DM6446. + * The PSC manages three inputs to a "module" which may be a peripheral or + * CPU. Those inputs are the module's: clock; reset signal; and sometimes + * its power domain. For our purposes, we only care whether clock and power + * are active, and the module is out of reset. + * + * DaVinci chips may include two separate power domains: "Always On" and "DSP". + * Chips without a DSP generally have only one domain. + * + * The "Always On" power domain is always on when the chip is on, and is + * powered by the VDD pins (on DM644X). The majority of DaVinci modules + * lie within the "Always On" power domain. + * + * A separate domain called the "DSP" domain houses the C64x+ and other video + * hardware such as VICP. In some chips, the "DSP" domain is not always on. + * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X). */ /* Works on Always On power domain only (no PD argument) */ @@ -55,15 +55,17 @@ void lpsc_on(unsigned int id) mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - while (REG(PSC_PTSTAT) & 0x01); + while (REG(PSC_PTSTAT) & 0x01) + continue; if ((*mdstat & 0x1f) == 0x03) return; /* Already on and enabled */ *mdctl |= 0x03; - /* Special treatment for some modules as for sprue14 p.7.4.2 */ switch (id) { +#ifdef CONFIG_SOC_DM644X + /* Special treatment for some modules as for sprue14 p.7.4.2 */ case DAVINCI_LPSC_VPSSSLV: case DAVINCI_LPSC_EMAC: case DAVINCI_LPSC_EMAC_WRAPPER: @@ -80,14 +82,20 @@ void lpsc_on(unsigned int id) case DAVINCI_LPSC_GPIO: *mdctl |= 0x200; break; +#endif } REG(PSC_PTCMD) = 0x01; - while (REG(PSC_PTSTAT) & 0x03); - while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ + while (REG(PSC_PTSTAT) & 0x03) + continue; + while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */ + continue; } +/* Not all DaVinci chips have a DSP power domain. */ +#ifdef CONFIG_SOC_DM644X + /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ #if !defined(CONFIG_SYS_USE_DSPLINK) void dsp_on(void) @@ -124,59 +132,4 @@ void dsp_on(void) } #endif /* CONFIG_SYS_USE_DSPLINK */ -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_LPSC_UART0); - - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x0000e003; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= PINMUX1_UART0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC -void davinci_enable_emac(void) -{ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable EMAC. */ - REG(PINMUX0) |= PINMUX0_EMACEN; -} -#endif - -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_LPSC_I2C); - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= PINMUX1_I2C; -} - -void davinci_errata_workarounds(void) -{ - /* - * Workaround for TMS320DM6446 errata 1.3.22: - * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset - * Revision(s) Affected: 1.3 and earlier - */ - REG(PSC_SILVER_BULLET) = 0; - - /* - * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) - * as suggested in TMS320DM6446 errata 2.1.2: - * - * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions - * low priority modules can occupy the bus and prevent high priority - * modules like the VPSS from getting the required DDR2 throughput. - * A hex value of 0x20 should provide a good ARM (cache enabled) - * performance and still allow good utilization by the VPSS or other - * modules. - */ - REG(VBPR) = 0x20; -} +#endif /* have a DSP */ |