diff options
Diffstat (limited to 'cpu/arm_cortexa9/stw8500/timer.c')
| -rw-r--r--[-rwxr-xr-x] | cpu/arm_cortexa9/stw8500/timer.c | 92 |
1 files changed, 50 insertions, 42 deletions
diff --git a/cpu/arm_cortexa9/stw8500/timer.c b/cpu/arm_cortexa9/stw8500/timer.c index f0d015c04..1760a6472 100755..100644 --- a/cpu/arm_cortexa9/stw8500/timer.c +++ b/cpu/arm_cortexa9/stw8500/timer.c @@ -22,58 +22,75 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/mtu.h> -#include <asm/boottime.h> +#include <asm/arch/hardware.h> /* - * The timer is a decrementer, we'll left it free running at 2.4MHz. - * We have 2.4 ticks per microsecond and an overflow in almost 30min - * - * EABEJON: On HREF (atleast) there is no way the timer runs at 2.4MHz - * It is more likely that it around ~100 MHz with 1 as perscaler. - * Changing the perscaler setting to 16 gives a timer decrease rate of - * ~6.25MHz. - * - * Use the 3rd counter on MTU0 and let it run free since we're interested - * in how long time it takes to boot uboot+linux. Linux ux500 uses MTU0, - * timer0 and MTU1, timer0. - * + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. */ -#if 0 -#define TIMER_CLOCK (24 * 100 * 1000) -#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */ -#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */ -#endif - -#define TIMER_CLOCK (625 * 10 * 1000) -#define COUNT_TO_USEC(x) ((x) * 4 / 25) -#define USEC_TO_COUNT(x) ((x) * 25 / 4) - +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + +#define TIMER_CLOCK (110 * 1000 * 1000) +#define COUNT_TO_USEC(x) ((x) / 110) +#define USEC_TO_COUNT(x) ((x) * 110) #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) -/* Timer on MTU0 (from 0 to 3) */ -#define MTU_TIMER 2 - +static unsigned int timerbase; /* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(MTU_TIMER))) +#define READ_TIMER() (~readl(timerbase + MTU_VAL(0))) -/* Configure a free-running, auto-wrap counter with division by 16 as prescaler */ +/* Configure a free-running, auto-wrap counter with no prescaler */ int timer_init(void) { - writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_16 | MTU_CRn_32BITS, - CONFIG_SYS_TIMERBASE + MTU_CR(MTU_TIMER)); + timerbase = u8500_is_earlydrop() ? U8500_MTU0_BASE_ED + : U8500_MTU0_BASE_V1; + + writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, + timerbase + MTU_CR(0)); reset_timer(); - boottime_tag("uboot_init"); return 0; } /* Restart counting from 0 */ void reset_timer(void) { - writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(MTU_TIMER)); /* Immediate effect */ + writel(0, timerbase + MTU_LR(0)); /* Immediate effect */ } /* Return how many HZ passed since "base" */ @@ -82,14 +99,6 @@ ulong get_timer(ulong base) return TICKS_TO_HZ(READ_TIMER()) - base; } - -/* Return how many HZ passed since "base" */ -ulong get_raw_timer(void) -{ - return READ_TIMER(); -} - - /* Delay x useconds */ void udelay(unsigned long usec) { @@ -99,5 +108,4 @@ void udelay(unsigned long usec) end = ini + USEC_TO_COUNT(usec); while ((signed)(end - READ_TIMER()) > 0) ; - boottime_idle_add(USEC_TO_COUNT(usec)); } |