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Introduces various optimisations that approximately triple the
read data rate from NAND when run on da830evm.
Most of these optimisations depend on the endianess of the machine
and most of them are very similar to optimisations already present
in the Linux Kernel.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
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Davinci: NAND enable ECC even when not in NAND boot mode
On Davinci platforms, the default NAND device is enabled (for ECC)
in low level boot code when NAND boot mode is used. If booting in
another mode, NAND ECC is not enabled. The driver should make
sure ECC is enabled regardless of boot mode if NAND is configured
in U-Boot.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
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Davinci: Configurable NAND chip selects
Add a CONFIG_SYS_NAND_CS setting to all davinci configs and
use it to setup the NAND controller in the davinci_nand
mtd driver.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
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Currently, the last block of NAND devices can't be accessed. This patch
fixes this issue by correcting the boundary checking (off-by-one error).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
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There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Conflicts:
lib_generic/zlib.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Depending on offset, flash size and the number of bad blocks,
get_len_incl_bad may return a too small value which may lead to:
1) If there are no bad blocks, nand_{read,write}_skip_bad chooses the
bad block aware read/write code. This may hurt performance, but does
not have any adverse effects.
2) If there are bad blocks, the nand_{read,write}_skip_bad may choose
the bad block unaware read/write code (if len_incl_bad == *length)
which leads to corrupted data.
Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
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Conflicts:
board/esd/plu405/plu405.c
drivers/rtc/ftrtc010.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch moves the s3c64xx header files from include/
to include/asm-arm/arch-s3c64xx
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch moves the s3c24x0 header files from include/ to
include/asm-arm/arch-s3c24x0/.
checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due
to a non-UTF8 character in David M?ller's name:
ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8
#489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3:
+ * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch
As David's name correctly contains a non-UTF8 character I haven't fixed
these errors.
The 3 warnings were all because of the use of 'volatile' in s3c24x0.h:
WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35:
+typedef volatile u8 S3C24X0_REG8;
+typedef volatile u16 S3C24X0_REG16;
+typedef volatile u32 S3C24X0_REG32;
I'll fix these errors in another patch.
Tested by running MAKEALL for ARM8 targets and ensuring there were no new
errors or warnings.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Reported-by: Peter Gombos <gombos@protecta.hu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Jason McMullan <jason.mcmullan@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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This patch adds support for NAND devices with a page size of
4K in the DaVinci NAND driver. The layout matches the layout that TI uses
for 4K page size NAND devices in the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch add nand_read_buf() for S3C2410 NAND SPL.
In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip,
so nand->select_chip should also be initialized.
Signed-off-by: Hui.Tang <zetalabs@gmail.com>
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This patch updates a check condition in the NAND driver.
The check condition is similat to what is in linux/next.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds support for Flex-OneNAND devices.
Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com>
Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
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The commit 66372fe2 manually relocated the bbt pattern pointer,
which can be removed by using full relocation.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
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The syndrome based page read/write routines store ECC, and possibly other
"OOB" data, right after each chunk of ECC'd data. With ECC chunk size of
512 bytes and a large page (2KiB) NAND, the layout is:
data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover
Where OOBx is (prepad, ECC, postpad). However, the current "raw" routines
use a traditional layout -- data OOB, disregarding the prepad and postpad
values -- so when they're used with that type of ECC hardware, those calls
mix up the data and OOB. Which means, in particular, that bad block
tables won't be found on startup, with data corruption and related chaos
ensuing.
The current syndrome-based drivers in mainline all seem to use one chunk
per page; presumably they haven't noticed such bugs.
Fix this, by adding read/write page_raw_syndrome() routines as siblings of
the existing non-raw routines; "raw" just means to bypass the ECC
computations, not change data and OOB layout.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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When computing oobavail from the list of free areas in the OOB,
don't assume there will always be an unused slot at the end.
This syncs up with the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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The patch updates the check condition for determining
whether the ECC corrections has failed.
This makes it similar to what is in the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Patch updates the comments and explanations for
the arguments to various functions.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This was originally part of Thomas Gleixner's patch for
adding support for 4KiB pages.
This is not part of the U-Boot NAND driver so updating the
driver with this to sync up with the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Patch removes already commented out dead code
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch updates the "chip_shift" calculation in the
NAND driver. This is being done to sync up the NAND driver with
the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds support for NANDs greater than 2 GB.
Patch is based on the MTD NAND driver in the kernel.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Currently the CFI driver issues both AMD and Intel reset commands.
This is because the driver doesn't know yet which chips are connected.
This dual reset seems to cause problems with the M29W128G chips as
reported by Richard Retanubun. This patch now introduces a weak default
function for the CFI reset command, still with both resets. This can
be overridden by a board specific version if necessary.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
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Some of the new spi flash files were missing explicit license lines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes
to add support for the Embest SBC2440-II Board.
The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports
It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
- patches 1/4, 2/4 and 3/4 of this series
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch includes the onenand driver for s5pc100
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
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Add #ifdefs where necessary to not perform relocation fixups. This
allows boards/architectures which support relocation to trim a decent
chunk of code.
Note that this patch doesn't add #ifdefs to architecture-specific code
which does not support relocation.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Micron nand flash needs a reset before a read command is issued.
The current mpc5121_nfc driver ignores the reset command.
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This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Scott Wood <scottwood@freescale.com>
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This patch adds 4 BIT ECC support in the DaVinci NAND
driver. Tested on both the DM355 and DM365.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to
support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND
chips. This ECC mode is similar to NAND_ECC_HW, with the exception of
read_page API that first reads the OOB area, reads the data in chunks,
feeds the ECC from OOB area to the ECC hw engine and perform any
correction on the data as per the ECC status reported by the engine.
This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Driver for NFC NAND controller found on Freescale's MX2 and MX3
processors. Ported from Linux. Tested only with i.MX27 but should
works with other MX2 and MX3 processors too.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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This patch adds a new "page" parameter to all NAND read_page/read_page_raw
APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the
page information to send the READOOB command and read the OOB area before
the data area.
This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch
WE would like this to become part of the u-boot GIT as well
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Remove unused read_spareram and add unlock_all as kernel does
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Add KB9202 NAND driver
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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see http://www.jedec.org/download/search/jep106Z.pdf
Add some second source legacy flash chips 256x8.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
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Fix ECC Correction bug where the byte offset location were double
flipped causing correction routine to toggle the wrong byte location
in the ECC segment. The ndfc_calculate_ecc routine change the order
of getting the ECC code.
/* The NDFC uses Smart Media (SMC) bytes order */
ecc_code[0] = p[2];
ecc_code[1] = p[1];
ecc_code[2] = p[3];
But in the Correction algorithm when calculating the byte offset
location, the s1 is used as the upper part of the address. Which
again reverse the order making the final byte offset address
location incorrect.
byteoffs = (s1 << 0) & 0x80;
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byteoffs |= (s0 >> 4) & 0x08;
The order is change to read it in straight and let the correction
function to revert it to SMC order.
Signed-off-by: Feng Kan <fkan@amcc.com>
Acked-by: Victor Gallardo <vgallardo@amcc.com>
Acked-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: giulio.benetti@micronovasrl.com
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Fix bug introduced by 9c048b523413ae5f3ff34e00cf57569c3368ab51.
The cfi_flash.c driver cast the flash buffer size to a uchar in
flash_write_cfibuffer(). On some flash parts, (tested on Numonyx
part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to
uchar to enable buffer sizes to be larger.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This chip is used in a number of boards manufactured by Calao-Systems
which should be supported soon. This driver provides the necessary
spi_read and spi_write functions necessary to communicate with the chip.
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
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