path: root/board/st/u8500/dsilink_regs.h

/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
* for ST-Ericsson.
*
* License terms: GNU General Public License (GPL), version 2.
*/
#ifndef __DSILINK_REGS_H__
#define __DSILINK_REGS_H__

#define DSI_VAL2REG(__reg, __fld, __val) \
	(((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK)
#define DSI_REG2VAL(__reg, __fld, __val) \
	(((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT)

#define DSI_MCTL_INTEGRATION_MODE 0x00000000
#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN_SHIFT 0
#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN_MASK 0x00000001
#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_INTEGRATION_MODE, INT_MODE_EN, __x)
#define DSI_MCTL_MAIN_DATA_CTL 0x00000004
#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN_SHIFT 0
#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN_MASK 0x00000001
#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, LINK_EN, __x)
#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_SHIFT 1
#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_MASK 0x00000002
#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_CMD 0
#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_VID 1
#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_ENUM(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_MODE, \
	DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_##__x)
#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_MODE, __x)
#define DSI_MCTL_MAIN_DATA_CTL_VID_EN_SHIFT 2
#define DSI_MCTL_MAIN_DATA_CTL_VID_EN_MASK 0x00000004
#define DSI_MCTL_MAIN_DATA_CTL_VID_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, VID_EN, __x)
#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL_SHIFT 3
#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL_MASK 0x00000008
#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, TVG_SEL, __x)
#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL_SHIFT 4
#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL_MASK 0x00000010
#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, TBG_SEL, __x)
#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN_SHIFT 5
#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN_MASK 0x00000020
#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_TE_EN, __x)
#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN_SHIFT 6
#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN_MASK 0x00000040
#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF2_TE_EN, __x)
#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN_SHIFT 7
#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN_MASK 0x00000080
#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, REG_TE_EN, __x)
#define DSI_MCTL_MAIN_DATA_CTL_READ_EN_SHIFT 8
#define DSI_MCTL_MAIN_DATA_CTL_READ_EN_MASK 0x00000100
#define DSI_MCTL_MAIN_DATA_CTL_READ_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, READ_EN, __x)
#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN_SHIFT 9
#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN_MASK 0x00000200
#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, BTA_EN, __x)
#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC_SHIFT 10
#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC_MASK 0x00000400
#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_GEN_ECC, __x)
#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM_SHIFT 11
#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM_MASK 0x00000800
#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_GEN_CHECKSUM, __x)
#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN_SHIFT 12
#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN_MASK 0x00001000
#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, HOST_EOT_GEN, __x)
#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN_SHIFT 13
#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN_MASK 0x00002000
#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_EOT_GEN, __x)
#define DSI_MCTL_MAIN_PHY_CTL 0x00000008
#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN_SHIFT 0
#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN_MASK 0x00000001
#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, LANE2_EN, __x)
#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE_SHIFT 1
#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE_MASK 0x00000002
#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, FORCE_STOP_MODE, __x)
#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS_SHIFT 2
#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS_MASK 0x00000004
#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, CLK_CONTINUOUS, __x)
#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN_SHIFT 3
#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN_MASK 0x00000008
#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, CLK_ULPM_EN, __x)
#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN_SHIFT 4
#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN_MASK 0x00000010
#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, DAT1_ULPM_EN, __x)
#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN_SHIFT 5
#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN_MASK 0x00000020
#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, DAT2_ULPM_EN, __x)
#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT 6
#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, WAIT_BURST_TIME, __x)
#define DSI_MCTL_PLL_CTL 0x0000000C
#define DSI_MCTL_PLL_CTL_PLL_MULT_SHIFT 0
#define DSI_MCTL_PLL_CTL_PLL_MULT_MASK 0x000000FF
#define DSI_MCTL_PLL_CTL_PLL_MULT(__x) \
	DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_MULT, __x)
#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV_SHIFT 8
#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV_MASK 0x00003F00
#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV(__x) \
	DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_DIV, __x)
#define DSI_MCTL_PLL_CTL_PLL_IN_DIV_SHIFT 14
#define DSI_MCTL_PLL_CTL_PLL_IN_DIV_MASK 0x0001C000
#define DSI_MCTL_PLL_CTL_PLL_IN_DIV(__x) \
	DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_IN_DIV, __x)
#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2_SHIFT 17
#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2_MASK 0x00020000
#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2(__x) \
	DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_SEL_DIV2, __x)
#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_SHIFT 18
#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_MASK 0x00040000
#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_INT_PLL 0
#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_SYS_PLL 1
#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_ENUM(__x) \
	DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_SEL, \
	DSI_MCTL_PLL_CTL_PLL_OUT_SEL_##__x)
#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL(__x) \
	DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_SEL, __x)
#define DSI_MCTL_PLL_CTL_PLL_MASTER_SHIFT 31
#define DSI_MCTL_PLL_CTL_PLL_MASTER_MASK 0x80000000
#define DSI_MCTL_PLL_CTL_PLL_MASTER(__x) \
	DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_MASTER, __x)
#define DSI_MCTL_LANE_STS 0x00000010
#define DSI_MCTL_LANE_STS_CLKLANE_STATE_SHIFT 0
#define DSI_MCTL_LANE_STS_CLKLANE_STATE_MASK 0x00000003
#define DSI_MCTL_LANE_STS_CLKLANE_STATE_START 0
#define DSI_MCTL_LANE_STS_CLKLANE_STATE_IDLE 1
#define DSI_MCTL_LANE_STS_CLKLANE_STATE_HS 2
#define DSI_MCTL_LANE_STS_CLKLANE_STATE_ULPM 3
#define DSI_MCTL_LANE_STS_CLKLANE_STATE_ENUM(__x) \
	DSI_VAL2REG(DSI_MCTL_LANE_STS, CLKLANE_STATE, \
	DSI_MCTL_LANE_STS_CLKLANE_STATE_##__x)
#define DSI_MCTL_LANE_STS_CLKLANE_STATE(__x) \
	DSI_VAL2REG(DSI_MCTL_LANE_STS, CLKLANE_STATE, __x)
#define DSI_MCTL_LANE_STS_DATLANE1_STATE_SHIFT 2
#define DSI_MCTL_LANE_STS_DATLANE1_STATE_MASK 0x0000001C
#define DSI_MCTL_LANE_STS_DATLANE1_STATE_START 0
#define DSI_MCTL_LANE_STS_DATLANE1_STATE_IDLE 1
#define DSI_MCTL_LANE_STS_DATLANE1_STATE_WRITE 2
#define DSI_MCTL_LANE_STS_DATLANE1_STATE_ULPM 3
#define DSI_MCTL_LANE_STS_DATLANE1_STATE_READ 4
#define DSI_MCTL_LANE_STS_DATLANE1_STATE_ENUM(__x) \
	DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE1_STATE, \
	DSI_MCTL_LANE_STS_DATLANE1_STATE_##__x)
#define DSI_MCTL_LANE_STS_DATLANE1_STATE(__x) \
	DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE1_STATE, __x)
#define DSI_MCTL_LANE_STS_DATLANE2_STATE_SHIFT 5
#define DSI_MCTL_LANE_STS_DATLANE2_STATE_MASK 0x00000060
#define DSI_MCTL_LANE_STS_DATLANE2_STATE_START 0
#define DSI_MCTL_LANE_STS_DATLANE2_STATE_IDLE 1
#define DSI_MCTL_LANE_STS_DATLANE2_STATE_WRITE 2
#define DSI_MCTL_LANE_STS_DATLANE2_STATE_ULPM 3
#define DSI_MCTL_LANE_STS_DATLANE2_STATE_ENUM(__x) \
	DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE2_STATE, \
	DSI_MCTL_LANE_STS_DATLANE2_STATE_##__x)
#define DSI_MCTL_LANE_STS_DATLANE2_STATE(__x) \
	DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE2_STATE, __x)
#define DSI_MCTL_DPHY_TIMEOUT 0x00000014
#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_MASK 0x0000000F
#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, CLK_DIV, __x)
#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT 4
#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_MASK 0x0003FFF0
#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, HSTX_TO_VAL, __x)
#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT 18
#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_MASK 0xFFFC0000
#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, LPRX_TO_VAL, __x)
#define DSI_MCTL_ULPOUT_TIME 0x00000018
#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT 0
#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_MASK 0x000001FF
#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME(__x) \
	DSI_VAL2REG(DSI_MCTL_ULPOUT_TIME, CKLANE_ULPOUT_TIME, __x)
#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT 9
#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_MASK 0x0003FE00
#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME(__x) \
	DSI_VAL2REG(DSI_MCTL_ULPOUT_TIME, DATA_ULPOUT_TIME, __x)
#define DSI_MCTL_DPHY_STATIC 0x0000001C
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT 0
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK_MASK 0x00000001
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_CLK, __x)
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT 1
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK_MASK 0x00000002
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_CLK, __x)
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT 2
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1_MASK 0x00000004
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_DAT1, __x)
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT 3
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1_MASK 0x00000008
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_DAT1, __x)
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT 4
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2_MASK 0x00000010
#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_DAT2, __x)
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT 5
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2_MASK 0x00000020
#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_DAT2, __x)
#define DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT 6
#define DSI_MCTL_DPHY_STATIC_UI_X4_MASK 0x00000FC0
#define DSI_MCTL_DPHY_STATIC_UI_X4(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, UI_X4, __x)
#define DSI_MCTL_MAIN_EN 0x00000020
#define DSI_MCTL_MAIN_EN_PLL_START_SHIFT 0
#define DSI_MCTL_MAIN_EN_PLL_START_MASK 0x00000001
#define DSI_MCTL_MAIN_EN_PLL_START(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, PLL_START, __x)
#define DSI_MCTL_MAIN_EN_CKLANE_EN_SHIFT 3
#define DSI_MCTL_MAIN_EN_CKLANE_EN_MASK 0x00000008
#define DSI_MCTL_MAIN_EN_CKLANE_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, CKLANE_EN, __x)
#define DSI_MCTL_MAIN_EN_DAT1_EN_SHIFT 4
#define DSI_MCTL_MAIN_EN_DAT1_EN_MASK 0x00000010
#define DSI_MCTL_MAIN_EN_DAT1_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT1_EN, __x)
#define DSI_MCTL_MAIN_EN_DAT2_EN_SHIFT 5
#define DSI_MCTL_MAIN_EN_DAT2_EN_MASK 0x00000020
#define DSI_MCTL_MAIN_EN_DAT2_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT2_EN, __x)
#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ_SHIFT 6
#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ_MASK 0x00000040
#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, CLKLANE_ULPM_REQ, __x)
#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ_SHIFT 7
#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ_MASK 0x00000080
#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT1_ULPM_REQ, __x)
#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ_SHIFT 8
#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ_MASK 0x00000100
#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT2_ULPM_REQ, __x)
#define DSI_MCTL_MAIN_EN_IF1_EN_SHIFT 9
#define DSI_MCTL_MAIN_EN_IF1_EN_MASK 0x00000200
#define DSI_MCTL_MAIN_EN_IF1_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, IF1_EN, __x)
#define DSI_MCTL_MAIN_EN_IF2_EN_SHIFT 10
#define DSI_MCTL_MAIN_EN_IF2_EN_MASK 0x00000400
#define DSI_MCTL_MAIN_EN_IF2_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_EN, IF2_EN, __x)
#define DSI_MCTL_MAIN_STS 0x00000024
#define DSI_MCTL_MAIN_STS_PLL_LOCK_SHIFT 0
#define DSI_MCTL_MAIN_STS_PLL_LOCK_MASK 0x00000001
#define DSI_MCTL_MAIN_STS_PLL_LOCK(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS, PLL_LOCK, __x)
#define DSI_MCTL_MAIN_STS_CLKLANE_READY_SHIFT 1
#define DSI_MCTL_MAIN_STS_CLKLANE_READY_MASK 0x00000002
#define DSI_MCTL_MAIN_STS_CLKLANE_READY(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS, CLKLANE_READY, __x)
#define DSI_MCTL_MAIN_STS_DAT1_READY_SHIFT 2
#define DSI_MCTL_MAIN_STS_DAT1_READY_MASK 0x00000004
#define DSI_MCTL_MAIN_STS_DAT1_READY(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS, DAT1_READY, __x)
#define DSI_MCTL_MAIN_STS_DAT2_READY_SHIFT 3
#define DSI_MCTL_MAIN_STS_DAT2_READY_MASK 0x00000008
#define DSI_MCTL_MAIN_STS_DAT2_READY(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS, DAT2_READY, __x)
#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_SHIFT 4
#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_MASK 0x00000010
#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS, HSTX_TO_ERR, __x)
#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_SHIFT 5
#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_MASK 0x00000020
#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS, LPRX_TO_ERR, __x)
#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_SHIFT 6
#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_MASK 0x00000040
#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS, CRS_UNTERM_PCK, __x)
#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_SHIFT 7
#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_MASK 0x00000080
#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS, VRS_UNTERM_PCK, __x)
#define DSI_MCTL_DPHY_ERR 0x00000028
#define DSI_MCTL_DPHY_ERR_ERR_ESC_1_SHIFT 6
#define DSI_MCTL_DPHY_ERR_ERR_ESC_1_MASK 0x00000040
#define DSI_MCTL_DPHY_ERR_ERR_ESC_1(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_ESC_1, __x)
#define DSI_MCTL_DPHY_ERR_ERR_ESC_2_SHIFT 7
#define DSI_MCTL_DPHY_ERR_ERR_ESC_2_MASK 0x00000080
#define DSI_MCTL_DPHY_ERR_ERR_ESC_2(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_ESC_2, __x)
#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1_SHIFT 8
#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1_MASK 0x00000100
#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_SYNCESC_1, __x)
#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2_SHIFT 9
#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2_MASK 0x00000200
#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_SYNCESC_2, __x)
#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1_SHIFT 10
#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1_MASK 0x00000400
#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONTROL_1, __x)
#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2_SHIFT 11
#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2_MASK 0x00000800
#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONTROL_2, __x)
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1_SHIFT 12
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1_MASK 0x00001000
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP0_1, __x)
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2_SHIFT 13
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2_MASK 0x00002000
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP0_2, __x)
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1_SHIFT 14
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1_MASK 0x00004000
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP1_1, __x)
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2_SHIFT 15
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2_MASK 0x00008000
#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP1_2, __x)
#define DSI_INT_VID_RDDATA 0x00000030
#define DSI_INT_VID_RDDATA_IF_DATA_SHIFT 0
#define DSI_INT_VID_RDDATA_IF_DATA_MASK 0x0000FFFF
#define DSI_INT_VID_RDDATA_IF_DATA(__x) \
	DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_DATA, __x)
#define DSI_INT_VID_RDDATA_IF_VALID_SHIFT 16
#define DSI_INT_VID_RDDATA_IF_VALID_MASK 0x00010000
#define DSI_INT_VID_RDDATA_IF_VALID(__x) \
	DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_VALID, __x)
#define DSI_INT_VID_RDDATA_IF_START_SHIFT 17
#define DSI_INT_VID_RDDATA_IF_START_MASK 0x00020000
#define DSI_INT_VID_RDDATA_IF_START(__x) \
	DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_START, __x)
#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC_SHIFT 18
#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC_MASK 0x00040000
#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC(__x) \
	DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_FRAME_SYNC, __x)
#define DSI_INT_VID_GNT 0x00000034
#define DSI_INT_VID_GNT_IF_STALL_SHIFT 0
#define DSI_INT_VID_GNT_IF_STALL_MASK 0x00000001
#define DSI_INT_VID_GNT_IF_STALL(__x) \
	DSI_VAL2REG(DSI_INT_VID_GNT, IF_STALL, __x)
#define DSI_INT_CMD_RDDATA 0x00000038
#define DSI_INT_CMD_RDDATA_IF_DATA_SHIFT 0
#define DSI_INT_CMD_RDDATA_IF_DATA_MASK 0x0000FFFF
#define DSI_INT_CMD_RDDATA_IF_DATA(__x) \
	DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_DATA, __x)
#define DSI_INT_CMD_RDDATA_IF_VALID_SHIFT 16
#define DSI_INT_CMD_RDDATA_IF_VALID_MASK 0x00010000
#define DSI_INT_CMD_RDDATA_IF_VALID(__x) \
	DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_VALID, __x)
#define DSI_INT_CMD_RDDATA_IF_START_SHIFT 17
#define DSI_INT_CMD_RDDATA_IF_START_MASK 0x00020000
#define DSI_INT_CMD_RDDATA_IF_START(__x) \
	DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_START, __x)
#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC_SHIFT 18
#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC_MASK 0x00040000
#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC(__x) \
	DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_FRAME_SYNC, __x)
#define DSI_INT_CMD_GNT 0x0000003C
#define DSI_INT_CMD_GNT_IF_STALL_SHIFT 0
#define DSI_INT_CMD_GNT_IF_STALL_MASK 0x00000001
#define DSI_INT_CMD_GNT_IF_STALL(__x) \
	DSI_VAL2REG(DSI_INT_CMD_GNT, IF_STALL, __x)
#define DSI_INT_INTERRUPT_CTL 0x00000040
#define DSI_INT_INTERRUPT_CTL_INT_VAL_SHIFT 0
#define DSI_INT_INTERRUPT_CTL_INT_VAL_MASK 0x00000001
#define DSI_INT_INTERRUPT_CTL_INT_VAL(__x) \
	DSI_VAL2REG(DSI_INT_INTERRUPT_CTL, INT_VAL, __x)
#define DSI_CMD_MODE_CTL 0x00000050
#define DSI_CMD_MODE_CTL_IF1_ID_SHIFT 0
#define DSI_CMD_MODE_CTL_IF1_ID_MASK 0x00000003
#define DSI_CMD_MODE_CTL_IF1_ID(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_CTL, IF1_ID, __x)
#define DSI_CMD_MODE_CTL_IF2_ID_SHIFT 2
#define DSI_CMD_MODE_CTL_IF2_ID_MASK 0x0000000C
#define DSI_CMD_MODE_CTL_IF2_ID(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_CTL, IF2_ID, __x)
#define DSI_CMD_MODE_CTL_IF1_LP_EN_SHIFT 4
#define DSI_CMD_MODE_CTL_IF1_LP_EN_MASK 0x00000010
#define DSI_CMD_MODE_CTL_IF1_LP_EN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_CTL, IF1_LP_EN, __x)
#define DSI_CMD_MODE_CTL_IF2_LP_EN_SHIFT 5
#define DSI_CMD_MODE_CTL_IF2_LP_EN_MASK 0x00000020
#define DSI_CMD_MODE_CTL_IF2_LP_EN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_CTL, IF2_LP_EN, __x)
#define DSI_CMD_MODE_CTL_ARB_MODE_SHIFT 6
#define DSI_CMD_MODE_CTL_ARB_MODE_MASK 0x00000040
#define DSI_CMD_MODE_CTL_ARB_MODE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_CTL, ARB_MODE, __x)
#define DSI_CMD_MODE_CTL_ARB_PRI_SHIFT 7
#define DSI_CMD_MODE_CTL_ARB_PRI_MASK 0x00000080
#define DSI_CMD_MODE_CTL_ARB_PRI(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_CTL, ARB_PRI, __x)
#define DSI_CMD_MODE_CTL_FIL_VALUE_SHIFT 8
#define DSI_CMD_MODE_CTL_FIL_VALUE_MASK 0x0000FF00
#define DSI_CMD_MODE_CTL_FIL_VALUE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_CTL, FIL_VALUE, __x)
#define DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT 16
#define DSI_CMD_MODE_CTL_TE_TIMEOUT_MASK 0x03FF0000
#define DSI_CMD_MODE_CTL_TE_TIMEOUT(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_CTL, TE_TIMEOUT, __x)
#define DSI_CMD_MODE_STS 0x00000054
#define DSI_CMD_MODE_STS_ERR_NO_TE_SHIFT 0
#define DSI_CMD_MODE_STS_ERR_NO_TE_MASK 0x00000001
#define DSI_CMD_MODE_STS_ERR_NO_TE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_NO_TE, __x)
#define DSI_CMD_MODE_STS_ERR_TE_MISS_SHIFT 1
#define DSI_CMD_MODE_STS_ERR_TE_MISS_MASK 0x00000002
#define DSI_CMD_MODE_STS_ERR_TE_MISS(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_TE_MISS, __x)
#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN_SHIFT 2
#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN_MASK 0x00000004
#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_SDI1_UNDERRUN, __x)
#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN_SHIFT 3
#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN_MASK 0x00000008
#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_SDI2_UNDERRUN, __x)
#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD_SHIFT 4
#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD_MASK 0x00000010
#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_UNWANTED_RD, __x)
#define DSI_CMD_MODE_STS_CSM_RUNNING_SHIFT 5
#define DSI_CMD_MODE_STS_CSM_RUNNING_MASK 0x00000020
#define DSI_CMD_MODE_STS_CSM_RUNNING(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS, CSM_RUNNING, __x)
#define DSI_DIRECT_CMD_SEND 0x00000060
#define DSI_DIRECT_CMD_SEND_START_SHIFT 0
#define DSI_DIRECT_CMD_SEND_START_MASK 0xFFFFFFFF
#define DSI_DIRECT_CMD_SEND_START(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_SEND, START, __x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS 0x00000064
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_SHIFT 0
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_MASK 0x00000007
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE 0
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ 1
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ 4
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TRIG_REQ 5
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_BTA_REQ 6
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_ENUM(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_NAT, \
	DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_##__x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_NAT, __x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT_SHIFT 3
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT_MASK 0x00000008
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_LONGNOTSHORT, __x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT 8
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_MASK 0x00003F00
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_0 5
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_1 21
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_LONG_WRITE 57
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_READ 6
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_HEAD, \
	DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_##__x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_HEAD, __x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT 14
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_MASK 0x0000C000
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_ID, __x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT 16
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_MASK 0x001F0000
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_SIZE, __x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN_SHIFT 21
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN_MASK 0x00200000
#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_LP_EN, __x)
#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_SHIFT 24
#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_MASK 0x0F000000
#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, TRIGGER_VAL, __x)
#define DSI_DIRECT_CMD_STS 0x00000068
#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION_SHIFT 0
#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION_MASK 0x00000001
#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, CMD_TRANSMISSION, __x)
#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED_SHIFT 1
#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED_MASK 0x00000002
#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, WRITE_COMPLETED, __x)
#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED_SHIFT 2
#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED_MASK 0x00000004
#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_COMPLETED, __x)
#define DSI_DIRECT_CMD_STS_READ_COMPLETED_SHIFT 3
#define DSI_DIRECT_CMD_STS_READ_COMPLETED_MASK 0x00000008
#define DSI_DIRECT_CMD_STS_READ_COMPLETED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, READ_COMPLETED, __x)
#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_SHIFT 4
#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_MASK 0x00000010
#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACKNOWLEDGE_RECEIVED, __x)
#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED_SHIFT 5
#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED_MASK 0x00000020
#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACKNOWLEDGE_WITH_ERR_RECEIVED, __x)
#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED_SHIFT 6
#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED_MASK 0x00000040
#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_RECEIVED, __x)
#define DSI_DIRECT_CMD_STS_TE_RECEIVED_SHIFT 7
#define DSI_DIRECT_CMD_STS_TE_RECEIVED_MASK 0x00000080
#define DSI_DIRECT_CMD_STS_TE_RECEIVED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, TE_RECEIVED, __x)
#define DSI_DIRECT_CMD_STS_BTA_COMPLETED_SHIFT 8
#define DSI_DIRECT_CMD_STS_BTA_COMPLETED_MASK 0x00000100
#define DSI_DIRECT_CMD_STS_BTA_COMPLETED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, BTA_COMPLETED, __x)
#define DSI_DIRECT_CMD_STS_BTA_FINISHED_SHIFT 9
#define DSI_DIRECT_CMD_STS_BTA_FINISHED_MASK 0x00000200
#define DSI_DIRECT_CMD_STS_BTA_FINISHED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, BTA_FINISHED, __x)
#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR_SHIFT 10
#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR_MASK 0x00000400
#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, READ_COMPLETED_WITH_ERR, __x)
#define DSI_DIRECT_CMD_STS_TRIGGER_VAL_SHIFT 11
#define DSI_DIRECT_CMD_STS_TRIGGER_VAL_MASK 0x00007800
#define DSI_DIRECT_CMD_STS_TRIGGER_VAL(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_VAL, __x)
#define DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT 16
#define DSI_DIRECT_CMD_STS_ACK_VAL_MASK 0xFFFF0000
#define DSI_DIRECT_CMD_STS_ACK_VAL(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACK_VAL, __x)
#define DSI_DIRECT_CMD_RD_INIT 0x0000006C
#define DSI_DIRECT_CMD_RD_INIT_RESET_SHIFT 0
#define DSI_DIRECT_CMD_RD_INIT_RESET_MASK 0xFFFFFFFF
#define DSI_DIRECT_CMD_RD_INIT_RESET(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_INIT, RESET, __x)
#define DSI_DIRECT_CMD_WRDAT0 0x00000070
#define DSI_DIRECT_CMD_WRDAT0_WRDAT0_SHIFT 0
#define DSI_DIRECT_CMD_WRDAT0_WRDAT0_MASK 0x000000FF
#define DSI_DIRECT_CMD_WRDAT0_WRDAT0(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT0, __x)
#define DSI_DIRECT_CMD_WRDAT0_WRDAT1_SHIFT 8
#define DSI_DIRECT_CMD_WRDAT0_WRDAT1_MASK 0x0000FF00
#define DSI_DIRECT_CMD_WRDAT0_WRDAT1(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT1, __x)
#define DSI_DIRECT_CMD_WRDAT0_WRDAT2_SHIFT 16
#define DSI_DIRECT_CMD_WRDAT0_WRDAT2_MASK 0x00FF0000
#define DSI_DIRECT_CMD_WRDAT0_WRDAT2(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT2, __x)
#define DSI_DIRECT_CMD_WRDAT0_WRDAT3_SHIFT 24
#define DSI_DIRECT_CMD_WRDAT0_WRDAT3_MASK 0xFF000000
#define DSI_DIRECT_CMD_WRDAT0_WRDAT3(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT3, __x)
#define DSI_DIRECT_CMD_WRDAT1 0x00000074
#define DSI_DIRECT_CMD_WRDAT1_WRDAT4_SHIFT 0
#define DSI_DIRECT_CMD_WRDAT1_WRDAT4_MASK 0x000000FF
#define DSI_DIRECT_CMD_WRDAT1_WRDAT4(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT4, __x)
#define DSI_DIRECT_CMD_WRDAT1_WRDAT5_SHIFT 8
#define DSI_DIRECT_CMD_WRDAT1_WRDAT5_MASK 0x0000FF00
#define DSI_DIRECT_CMD_WRDAT1_WRDAT5(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT5, __x)
#define DSI_DIRECT_CMD_WRDAT1_WRDAT6_SHIFT 16
#define DSI_DIRECT_CMD_WRDAT1_WRDAT6_MASK 0x00FF0000
#define DSI_DIRECT_CMD_WRDAT1_WRDAT6(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT6, __x)
#define DSI_DIRECT_CMD_WRDAT1_WRDAT7_SHIFT 24
#define DSI_DIRECT_CMD_WRDAT1_WRDAT7_MASK 0xFF000000
#define DSI_DIRECT_CMD_WRDAT1_WRDAT7(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT7, __x)
#define DSI_DIRECT_CMD_WRDAT2 0x00000078
#define DSI_DIRECT_CMD_WRDAT2_WRDAT8_SHIFT 0
#define DSI_DIRECT_CMD_WRDAT2_WRDAT8_MASK 0x000000FF
#define DSI_DIRECT_CMD_WRDAT2_WRDAT8(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT8, __x)
#define DSI_DIRECT_CMD_WRDAT2_WRDAT9_SHIFT 8
#define DSI_DIRECT_CMD_WRDAT2_WRDAT9_MASK 0x0000FF00
#define DSI_DIRECT_CMD_WRDAT2_WRDAT9(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT9, __x)
#define DSI_DIRECT_CMD_WRDAT2_WRDAT10_SHIFT 16
#define DSI_DIRECT_CMD_WRDAT2_WRDAT10_MASK 0x00FF0000
#define DSI_DIRECT_CMD_WRDAT2_WRDAT10(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT10, __x)
#define DSI_DIRECT_CMD_WRDAT2_WRDAT11_SHIFT 24
#define DSI_DIRECT_CMD_WRDAT2_WRDAT11_MASK 0xFF000000
#define DSI_DIRECT_CMD_WRDAT2_WRDAT11(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT11, __x)
#define DSI_DIRECT_CMD_WRDAT3 0x0000007C
#define DSI_DIRECT_CMD_WRDAT3_WRDAT12_SHIFT 0
#define DSI_DIRECT_CMD_WRDAT3_WRDAT12_MASK 0x000000FF
#define DSI_DIRECT_CMD_WRDAT3_WRDAT12(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT12, __x)
#define DSI_DIRECT_CMD_WRDAT3_WRDAT13_SHIFT 8
#define DSI_DIRECT_CMD_WRDAT3_WRDAT13_MASK 0x0000FF00
#define DSI_DIRECT_CMD_WRDAT3_WRDAT13(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT13, __x)
#define DSI_DIRECT_CMD_WRDAT3_WRDAT14_SHIFT 16
#define DSI_DIRECT_CMD_WRDAT3_WRDAT14_MASK 0x00FF0000
#define DSI_DIRECT_CMD_WRDAT3_WRDAT14(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT14, __x)
#define DSI_DIRECT_CMD_WRDAT3_WRDAT15_SHIFT 24
#define DSI_DIRECT_CMD_WRDAT3_WRDAT15_MASK 0xFF000000
#define DSI_DIRECT_CMD_WRDAT3_WRDAT15(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT15, __x)
#define DSI_DIRECT_CMD_RDDAT 0x00000080
#define DSI_DIRECT_CMD_RDDAT_RDDAT0_SHIFT 0
#define DSI_DIRECT_CMD_RDDAT_RDDAT0_MASK 0x000000FF
#define DSI_DIRECT_CMD_RDDAT_RDDAT0(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT0, __x)
#define DSI_DIRECT_CMD_RDDAT_RDDAT1_SHIFT 8
#define DSI_DIRECT_CMD_RDDAT_RDDAT1_MASK 0x0000FF00
#define DSI_DIRECT_CMD_RDDAT_RDDAT1(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT1, __x)
#define DSI_DIRECT_CMD_RDDAT_RDDAT2_SHIFT 16
#define DSI_DIRECT_CMD_RDDAT_RDDAT2_MASK 0x00FF0000
#define DSI_DIRECT_CMD_RDDAT_RDDAT2(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT2, __x)
#define DSI_DIRECT_CMD_RDDAT_RDDAT3_SHIFT 24
#define DSI_DIRECT_CMD_RDDAT_RDDAT3_MASK 0xFF000000
#define DSI_DIRECT_CMD_RDDAT_RDDAT3(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT3, __x)
#define DSI_DIRECT_CMD_RD_PROPERTY 0x00000084
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_SHIFT 0
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK 0x0000FFFF
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_SIZE, __x)
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_SHIFT 16
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_MASK 0x00030000
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_ID, __x)
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_SHIFT 18
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_MASK 0x00040000
#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_DCSNOTGENERIC, __x)
#define DSI_DIRECT_CMD_RD_STS 0x00000088
#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED_SHIFT 0
#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED_MASK 0x00000001
#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_FIXED, __x)
#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE_SHIFT 1
#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE_MASK 0x00000002
#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_UNCORRECTABLE, __x)
#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM_SHIFT 2
#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM_MASK 0x00000004
#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_CHECKSUM, __x)
#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE_SHIFT 3
#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE_MASK 0x00000008
#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_UNDECODABLE, __x)
#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE_SHIFT 4
#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE_MASK 0x00000010
#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_RECEIVE, __x)
#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE_SHIFT 5
#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE_MASK 0x00000020
#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_OVERSIZE, __x)
#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH_SHIFT 6
#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH_MASK 0x00000040
#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_WRONG_LENGTH, __x)
#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT_SHIFT 7
#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT_MASK 0x00000080
#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_MISSING_EOT, __x)
#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR_SHIFT 8
#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR_MASK 0x00000100
#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_EOT_WITH_ERR, __x)
#define DSI_VID_MAIN_CTL 0x00000090
#define DSI_VID_MAIN_CTL_START_MODE_SHIFT 0
#define DSI_VID_MAIN_CTL_START_MODE_MASK 0x00000003
#define DSI_VID_MAIN_CTL_START_MODE(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, START_MODE, __x)
#define DSI_VID_MAIN_CTL_STOP_MODE_SHIFT 2
#define DSI_VID_MAIN_CTL_STOP_MODE_MASK 0x0000000C
#define DSI_VID_MAIN_CTL_STOP_MODE(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, STOP_MODE, __x)
#define DSI_VID_MAIN_CTL_VID_ID_SHIFT 4
#define DSI_VID_MAIN_CTL_VID_ID_MASK 0x00000030
#define DSI_VID_MAIN_CTL_VID_ID(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_ID, __x)
#define DSI_VID_MAIN_CTL_HEADER_SHIFT 6
#define DSI_VID_MAIN_CTL_HEADER_MASK 0x00000FC0
#define DSI_VID_MAIN_CTL_HEADER(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, HEADER, __x)
#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_SHIFT 12
#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_MASK 0x00003000
#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS 0
#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS 1
#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE 2
#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS 3
#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_ENUM(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_PIXEL_MODE, \
	DSI_VID_MAIN_CTL_VID_PIXEL_MODE_##__x)
#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_PIXEL_MODE, __x)
#define DSI_VID_MAIN_CTL_BURST_MODE_SHIFT 14
#define DSI_VID_MAIN_CTL_BURST_MODE_MASK 0x00004000
#define DSI_VID_MAIN_CTL_BURST_MODE(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, BURST_MODE, __x)
#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE_SHIFT 15
#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE_MASK 0x00008000
#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, SYNC_PULSE_ACTIVE, __x)
#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL_SHIFT 16
#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL_MASK 0x00010000
#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, SYNC_PULSE_HORIZONTAL, __x)
#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_SHIFT 17
#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_MASK 0x00060000
#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_NULL 0
#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING 1
#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0 2
#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 3
#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_ENUM(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKLINE_MODE, \
	DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_##__x)
#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKLINE_MODE, __x)
#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_SHIFT 19
#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_MASK 0x00180000
#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_NULL 0
#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_BLANKING 1
#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 2
#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_1 3
#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_ENUM(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKEOL_MODE, \
	DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_##__x)
#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKEOL_MODE, __x)
#define DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT 21
#define DSI_VID_MAIN_CTL_RECOVERY_MODE_MASK 0x00600000
#define DSI_VID_MAIN_CTL_RECOVERY_MODE(__x) \
	DSI_VAL2REG(DSI_VID_MAIN_CTL, RECOVERY_MODE, __x)
#define DSI_VID_VSIZE 0x00000094
#define DSI_VID_VSIZE_VSA_LENGTH_SHIFT 0
#define DSI_VID_VSIZE_VSA_LENGTH_MASK 0x0000003F
#define DSI_VID_VSIZE_VSA_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_VSIZE, VSA_LENGTH, __x)
#define DSI_VID_VSIZE_VBP_LENGTH_SHIFT 6
#define DSI_VID_VSIZE_VBP_LENGTH_MASK 0x00000FC0
#define DSI_VID_VSIZE_VBP_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_VSIZE, VBP_LENGTH, __x)
#define DSI_VID_VSIZE_VFP_LENGTH_SHIFT 12
#define DSI_VID_VSIZE_VFP_LENGTH_MASK 0x000FF000
#define DSI_VID_VSIZE_VFP_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_VSIZE, VFP_LENGTH, __x)
#define DSI_VID_VSIZE_VACT_LENGTH_SHIFT 20
#define DSI_VID_VSIZE_VACT_LENGTH_MASK 0x7FF00000
#define DSI_VID_VSIZE_VACT_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_VSIZE, VACT_LENGTH, __x)
#define DSI_VID_HSIZE1 0x00000098
#define DSI_VID_HSIZE1_HSA_LENGTH_SHIFT 0
#define DSI_VID_HSIZE1_HSA_LENGTH_MASK 0x000003FF
#define DSI_VID_HSIZE1_HSA_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_HSIZE1, HSA_LENGTH, __x)
#define DSI_VID_HSIZE1_HBP_LENGTH_SHIFT 10
#define DSI_VID_HSIZE1_HBP_LENGTH_MASK 0x000FFC00
#define DSI_VID_HSIZE1_HBP_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_HSIZE1, HBP_LENGTH, __x)
#define DSI_VID_HSIZE1_HFP_LENGTH_SHIFT 20
#define DSI_VID_HSIZE1_HFP_LENGTH_MASK 0x7FF00000
#define DSI_VID_HSIZE1_HFP_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_HSIZE1, HFP_LENGTH, __x)
#define DSI_VID_HSIZE2 0x0000009C
#define DSI_VID_HSIZE2_RGB_SIZE_SHIFT 0
#define DSI_VID_HSIZE2_RGB_SIZE_MASK 0x00001FFF
#define DSI_VID_HSIZE2_RGB_SIZE(__x) \
	DSI_VAL2REG(DSI_VID_HSIZE2, RGB_SIZE, __x)
#define DSI_VID_BLKSIZE1 0x000000A0
#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT 0
#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK 0x00001FFF
#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK(__x) \
	DSI_VAL2REG(DSI_VID_BLKSIZE1, BLKLINE_EVENT_PCK, __x)
#define DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT 13
#define DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK 0x03FFE000
#define DSI_VID_BLKSIZE1_BLKEOL_PCK(__x) \
	DSI_VAL2REG(DSI_VID_BLKSIZE1, BLKEOL_PCK, __x)
#define DSI_VID_BLKSIZE2 0x000000A4
#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT 0
#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_MASK 0x00001FFF
#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK(__x) \
	DSI_VAL2REG(DSI_VID_BLKSIZE2, BLKLINE_PULSE_PCK, __x)
#define DSI_VID_PCK_TIME 0x000000A8
#define DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT 0
#define DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK 0x00001FFF
#define DSI_VID_PCK_TIME_BLKEOL_DURATION(__x) \
	DSI_VAL2REG(DSI_VID_PCK_TIME, BLKEOL_DURATION, __x)
#define DSI_VID_DPHY_TIME 0x000000AC
#define DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT 0
#define DSI_VID_DPHY_TIME_REG_LINE_DURATION_MASK 0x00001FFF
#define DSI_VID_DPHY_TIME_REG_LINE_DURATION(__x) \
	DSI_VAL2REG(DSI_VID_DPHY_TIME, REG_LINE_DURATION, __x)
#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT 13
#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_MASK 0x00FFE000
#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME(__x) \
	DSI_VAL2REG(DSI_VID_DPHY_TIME, REG_WAKEUP_TIME, __x)
#define DSI_VID_ERR_COLOR 0x000000B0
#define DSI_VID_ERR_COLOR_COL_RED_SHIFT 0
#define DSI_VID_ERR_COLOR_COL_RED_MASK 0x000000FF
#define DSI_VID_ERR_COLOR_COL_RED(__x) \
	DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_RED, __x)
#define DSI_VID_ERR_COLOR_COL_GREEN_SHIFT 8
#define DSI_VID_ERR_COLOR_COL_GREEN_MASK 0x0000FF00
#define DSI_VID_ERR_COLOR_COL_GREEN(__x) \
	DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_GREEN, __x)
#define DSI_VID_ERR_COLOR_COL_BLUE_SHIFT 16
#define DSI_VID_ERR_COLOR_COL_BLUE_MASK 0x00FF0000
#define DSI_VID_ERR_COLOR_COL_BLUE(__x) \
	DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_BLUE, __x)
#define DSI_VID_ERR_COLOR_PAD_VAL_SHIFT 24
#define DSI_VID_ERR_COLOR_PAD_VAL_MASK 0xFF000000
#define DSI_VID_ERR_COLOR_PAD_VAL(__x) \
	DSI_VAL2REG(DSI_VID_ERR_COLOR, PAD_VAL, __x)
#define DSI_VID_VPOS 0x000000B4
#define DSI_VID_VPOS_LINE_POS_SHIFT 0
#define DSI_VID_VPOS_LINE_POS_MASK 0x00000003
#define DSI_VID_VPOS_LINE_POS(__x) \
	DSI_VAL2REG(DSI_VID_VPOS, LINE_POS, __x)
#define DSI_VID_VPOS_LINE_VAL_SHIFT 2
#define DSI_VID_VPOS_LINE_VAL_MASK 0x00001FFC
#define DSI_VID_VPOS_LINE_VAL(__x) \
	DSI_VAL2REG(DSI_VID_VPOS, LINE_VAL, __x)
#define DSI_VID_HPOS 0x000000B8
#define DSI_VID_HPOS_HORIZONTAL_POS_SHIFT 0
#define DSI_VID_HPOS_HORIZONTAL_POS_MASK 0x00000007
#define DSI_VID_HPOS_HORIZONTAL_POS(__x) \
	DSI_VAL2REG(DSI_VID_HPOS, HORIZONTAL_POS, __x)
#define DSI_VID_HPOS_HORIZONTAL_VAL_SHIFT 3
#define DSI_VID_HPOS_HORIZONTAL_VAL_MASK 0x0000FFF8
#define DSI_VID_HPOS_HORIZONTAL_VAL(__x) \
	DSI_VAL2REG(DSI_VID_HPOS, HORIZONTAL_VAL, __x)
#define DSI_VID_MODE_STS 0x000000BC
#define DSI_VID_MODE_STS_VSG_RUNNING_SHIFT 0
#define DSI_VID_MODE_STS_VSG_RUNNING_MASK 0x00000001
#define DSI_VID_MODE_STS_VSG_RUNNING(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, VSG_RUNNING, __x)
#define DSI_VID_MODE_STS_ERR_MISSING_DATA_SHIFT 1
#define DSI_VID_MODE_STS_ERR_MISSING_DATA_MASK 0x00000002
#define DSI_VID_MODE_STS_ERR_MISSING_DATA(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_DATA, __x)
#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC_SHIFT 2
#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC_MASK 0x00000004
#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_HSYNC, __x)
#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC_SHIFT 3
#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC_MASK 0x00000008
#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_VSYNC, __x)
#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH_SHIFT 4
#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH_MASK 0x00000010
#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, REG_ERR_SMALL_LENGTH, __x)
#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT_SHIFT 5
#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT_MASK 0x00000020
#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, REG_ERR_SMALL_HEIGHT, __x)
#define DSI_VID_MODE_STS_ERR_BURSTWRITE_SHIFT 6
#define DSI_VID_MODE_STS_ERR_BURSTWRITE_MASK 0x00000040
#define DSI_VID_MODE_STS_ERR_BURSTWRITE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, ERR_BURSTWRITE, __x)
#define DSI_VID_MODE_STS_ERR_LONGWRITE_SHIFT 7
#define DSI_VID_MODE_STS_ERR_LONGWRITE_MASK 0x00000080
#define DSI_VID_MODE_STS_ERR_LONGWRITE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, ERR_LONGWRITE, __x)
#define DSI_VID_MODE_STS_ERR_LONGREAD_SHIFT 8
#define DSI_VID_MODE_STS_ERR_LONGREAD_MASK 0x00000100
#define DSI_VID_MODE_STS_ERR_LONGREAD(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, ERR_LONGREAD, __x)
#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH_SHIFT 9
#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH_MASK 0x00000200
#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, ERR_VRS_WRONG_LENGTH, __x)
#define DSI_VID_MODE_STS_VSG_RECOVERY_SHIFT 10
#define DSI_VID_MODE_STS_VSG_RECOVERY_MASK 0x00000400
#define DSI_VID_MODE_STS_VSG_RECOVERY(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS, VSG_RECOVERY, __x)
#define DSI_VID_VCA_SETTING1 0x000000C0
#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT 0
#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK 0x0000FFFF
#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT(__x) \
	DSI_VAL2REG(DSI_VID_VCA_SETTING1, MAX_BURST_LIMIT, __x)
#define DSI_VID_VCA_SETTING1_BURST_LP_SHIFT 16
#define DSI_VID_VCA_SETTING1_BURST_LP_MASK 0x00010000
#define DSI_VID_VCA_SETTING1_BURST_LP(__x) \
	DSI_VAL2REG(DSI_VID_VCA_SETTING1, BURST_LP, __x)
#define DSI_VID_VCA_SETTING2 0x000000C4
#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT 0
#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK 0x0000FFFF
#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT(__x) \
	DSI_VAL2REG(DSI_VID_VCA_SETTING2, EXACT_BURST_LIMIT, __x)
#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT 16
#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK 0xFFFF0000
#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT(__x) \
	DSI_VAL2REG(DSI_VID_VCA_SETTING2, MAX_LINE_LIMIT, __x)
#define DSI_TVG_CTL 0x000000C8
#define DSI_TVG_CTL_TVG_RUN_SHIFT 0
#define DSI_TVG_CTL_TVG_RUN_MASK 0x00000001
#define DSI_TVG_CTL_TVG_RUN(__x) \
	DSI_VAL2REG(DSI_TVG_CTL, TVG_RUN, __x)
#define DSI_TVG_CTL_TVG_STOPMODE_SHIFT 1
#define DSI_TVG_CTL_TVG_STOPMODE_MASK 0x00000006
#define DSI_TVG_CTL_TVG_STOPMODE(__x) \
	DSI_VAL2REG(DSI_TVG_CTL, TVG_STOPMODE, __x)
#define DSI_TVG_CTL_TVG_MODE_SHIFT 3
#define DSI_TVG_CTL_TVG_MODE_MASK 0x00000018
#define DSI_TVG_CTL_TVG_MODE(__x) \
	DSI_VAL2REG(DSI_TVG_CTL, TVG_MODE, __x)
#define DSI_TVG_CTL_TVG_STRIPE_SIZE_SHIFT 5
#define DSI_TVG_CTL_TVG_STRIPE_SIZE_MASK 0x000000E0
#define DSI_TVG_CTL_TVG_STRIPE_SIZE(__x) \
	DSI_VAL2REG(DSI_TVG_CTL, TVG_STRIPE_SIZE, __x)
#define DSI_TVG_IMG_SIZE 0x000000CC
#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE_SHIFT 0
#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE_MASK 0x00001FFF
#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE(__x) \
	DSI_VAL2REG(DSI_TVG_IMG_SIZE, TVG_LINE_SIZE, __x)
#define DSI_TVG_IMG_SIZE_TVG_NBLINE_SHIFT 16
#define DSI_TVG_IMG_SIZE_TVG_NBLINE_MASK 0x07FF0000
#define DSI_TVG_IMG_SIZE_TVG_NBLINE(__x) \
	DSI_VAL2REG(DSI_TVG_IMG_SIZE, TVG_NBLINE, __x)
#define DSI_TVG_COLOR1 0x000000D0
#define DSI_TVG_COLOR1_COL1_RED_SHIFT 0
#define DSI_TVG_COLOR1_COL1_RED_MASK 0x000000FF
#define DSI_TVG_COLOR1_COL1_RED(__x) \
	DSI_VAL2REG(DSI_TVG_COLOR1, COL1_RED, __x)
#define DSI_TVG_COLOR1_COL1_GREEN_SHIFT 8
#define DSI_TVG_COLOR1_COL1_GREEN_MASK 0x0000FF00
#define DSI_TVG_COLOR1_COL1_GREEN(__x) \
	DSI_VAL2REG(DSI_TVG_COLOR1, COL1_GREEN, __x)
#define DSI_TVG_COLOR1_COL1_BLUE_SHIFT 16
#define DSI_TVG_COLOR1_COL1_BLUE_MASK 0x00FF0000
#define DSI_TVG_COLOR1_COL1_BLUE(__x) \
	DSI_VAL2REG(DSI_TVG_COLOR1, COL1_BLUE, __x)
#define DSI_TVG_COLOR2 0x000000D4
#define DSI_TVG_COLOR2_COL2_RED_SHIFT 0
#define DSI_TVG_COLOR2_COL2_RED_MASK 0x000000FF
#define DSI_TVG_COLOR2_COL2_RED(__x) \
	DSI_VAL2REG(DSI_TVG_COLOR2, COL2_RED, __x)
#define DSI_TVG_COLOR2_COL2_GREEN_SHIFT 8
#define DSI_TVG_COLOR2_COL2_GREEN_MASK 0x0000FF00
#define DSI_TVG_COLOR2_COL2_GREEN(__x) \
	DSI_VAL2REG(DSI_TVG_COLOR2, COL2_GREEN, __x)
#define DSI_TVG_COLOR2_COL2_BLUE_SHIFT 16
#define DSI_TVG_COLOR2_COL2_BLUE_MASK 0x00FF0000
#define DSI_TVG_COLOR2_COL2_BLUE(__x) \
	DSI_VAL2REG(DSI_TVG_COLOR2, COL2_BLUE, __x)
#define DSI_TVG_STS 0x000000D8
#define DSI_TVG_STS_TVG_RUNNING_SHIFT 0
#define DSI_TVG_STS_TVG_RUNNING_MASK 0x00000001
#define DSI_TVG_STS_TVG_RUNNING(__x) \
	DSI_VAL2REG(DSI_TVG_STS, TVG_RUNNING, __x)
#define DSI_TBG_CTL 0x000000E0
#define DSI_TBG_CTL_TBG_START_SHIFT 0
#define DSI_TBG_CTL_TBG_START_MASK 0x00000001
#define DSI_TBG_CTL_TBG_START(__x) \
	DSI_VAL2REG(DSI_TBG_CTL, TBG_START, __x)
#define DSI_TBG_CTL_TBG_HS_REQ_SHIFT 1
#define DSI_TBG_CTL_TBG_HS_REQ_MASK 0x00000002
#define DSI_TBG_CTL_TBG_HS_REQ(__x) \
	DSI_VAL2REG(DSI_TBG_CTL, TBG_HS_REQ, __x)
#define DSI_TBG_CTL_TBG_DATA_SEL_SHIFT 2
#define DSI_TBG_CTL_TBG_DATA_SEL_MASK 0x00000004
#define DSI_TBG_CTL_TBG_DATA_SEL(__x) \
	DSI_VAL2REG(DSI_TBG_CTL, TBG_DATA_SEL, __x)
#define DSI_TBG_CTL_TBG_MODE_SHIFT 3
#define DSI_TBG_CTL_TBG_MODE_MASK 0x00000018
#define DSI_TBG_CTL_TBG_MODE_1BYTE 0
#define DSI_TBG_CTL_TBG_MODE_2BYTE 1
#define DSI_TBG_CTL_TBG_MODE_BURST_COUNTER 2
#define DSI_TBG_CTL_TBG_MODE_BURST 3
#define DSI_TBG_CTL_TBG_MODE_ENUM(__x) \
	DSI_VAL2REG(DSI_TBG_CTL, TBG_MODE, DSI_TBG_CTL_TBG_MODE_##__x)
#define DSI_TBG_CTL_TBG_MODE(__x) \
	DSI_VAL2REG(DSI_TBG_CTL, TBG_MODE, __x)
#define DSI_TBG_SETTING 0x000000E4
#define DSI_TBG_SETTING_TBG_DATA_SHIFT 0
#define DSI_TBG_SETTING_TBG_DATA_MASK 0x0000FFFF
#define DSI_TBG_SETTING_TBG_DATA(__x) \
	DSI_VAL2REG(DSI_TBG_SETTING, TBG_DATA, __x)
#define DSI_TBG_SETTING_TBG_CPT_SHIFT 16
#define DSI_TBG_SETTING_TBG_CPT_MASK 0x0FFF0000
#define DSI_TBG_SETTING_TBG_CPT(__x) \
	DSI_VAL2REG(DSI_TBG_SETTING, TBG_CPT, __x)
#define DSI_TBG_STS 0x000000E8
#define DSI_TBG_STS_TBG_STATUS_SHIFT 0
#define DSI_TBG_STS_TBG_STATUS_MASK 0x00000001
#define DSI_TBG_STS_TBG_STATUS(__x) \
	DSI_VAL2REG(DSI_TBG_STS, TBG_STATUS, __x)
#define DSI_MCTL_MAIN_STS_CTL 0x000000F0
#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN_SHIFT 0
#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN_MASK 0x00000001
#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, PLL_LOCK_EN, __x)
#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN_SHIFT 1
#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN_MASK 0x00000002
#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CLKLANE_READY_EN, __x)
#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN_SHIFT 2
#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN_MASK 0x00000004
#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT1_READY_EN, __x)
#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN_SHIFT 3
#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN_MASK 0x00000008
#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT2_READY_EN, __x)
#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN_SHIFT 4
#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN_MASK 0x00000010
#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, HSTX_TO_ERR_EN, __x)
#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN_SHIFT 5
#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN_MASK 0x00000020
#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, LPRX_TO_ERR_EN, __x)
#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN_SHIFT 6
#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN_MASK 0x00000040
#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CRS_UNTERM_PCK_ERR_EN, __x)
#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN_SHIFT 7
#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN_MASK 0x00000080
#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, VRS_UNTERM_PCK_ERR_EN, __x)
#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE_SHIFT 16
#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE_MASK 0x00010000
#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, PLL_LOCK_EDGE, __x)
#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE_SHIFT 17
#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE_MASK 0x00020000
#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CLKLANE_READY_EDGE, __x)
#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE_SHIFT 18
#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE_MASK 0x00040000
#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT1_READY_EDGE, __x)
#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE_SHIFT 19
#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE_MASK 0x00080000
#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT2_READY_EDGE, __x)
#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE_SHIFT 20
#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE_MASK 0x00100000
#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, HSTX_TO_ERR_EDGE, __x)
#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE_SHIFT 21
#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE_MASK 0x00200000
#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, LPRX_TO_ERR_EDGE, __x)
#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE_SHIFT 22
#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE_MASK 0x00400000
#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CRS_UNTERM_PCK_ERR_EDGE, __x)
#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE_SHIFT 23
#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE_MASK 0x00800000
#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, VRS_UNTERM_PCK_ERR_EDGE, __x)
#define DSI_CMD_MODE_STS_CTL 0x000000F4
#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN_SHIFT 0
#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN_MASK 0x00000001
#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_NO_TE_EN, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN_SHIFT 1
#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN_MASK 0x00000002
#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_TE_MISS_EN, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN_SHIFT 2
#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN_MASK 0x00000004
#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI1_UNDERRUN_EN, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN_SHIFT 3
#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN_MASK 0x00000008
#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI2_UNDERRUN_EN, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN_SHIFT 4
#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN_MASK 0x00000010
#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_UNWANTED_RD_EN, __x)
#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN_SHIFT 5
#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN_MASK 0x00000020
#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, CSM_RUNNING_EN, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE_SHIFT 16
#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE_MASK 0x00010000
#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_NO_TE_EDGE, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE_SHIFT 17
#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE_MASK 0x00020000
#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_TE_MISS_EDGE, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE_SHIFT 18
#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE_MASK 0x00040000
#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI1_UNDERRUN_EDGE, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE_SHIFT 19
#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE_MASK 0x00080000
#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI2_UNDERRUN_EDGE, __x)
#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE_SHIFT 20
#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE_MASK 0x00100000
#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_UNWANTED_RD_EDGE, __x)
#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE_SHIFT 21
#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE_MASK 0x00200000
#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, CSM_RUNNING_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL 0x000000F8
#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN_SHIFT 0
#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN_MASK 0x00000001
#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, CMD_TRANSMISSION_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN_SHIFT 1
#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN_MASK 0x00000002
#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, WRITE_COMPLETED_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN_SHIFT 2
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN_MASK 0x00000004
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_COMPLETED_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN_SHIFT 3
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN_MASK 0x00000008
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN_SHIFT 4
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN_MASK 0x00000010
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_RECEIVED_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN_SHIFT 5
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN_MASK 0x00000020
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_WITH_ERR_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN_SHIFT 6
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN_MASK 0x00000040
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_RECEIVED_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN_SHIFT 7
#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN_MASK 0x00000080
#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TE_RECEIVED_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN_SHIFT 8
#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN_MASK 0x00000100
#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_COMPLETED_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN_SHIFT 9
#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN_MASK 0x00000200
#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_FINISHED_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN_SHIFT 10
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN_MASK 0x00000400
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_WITH_ERR_EN, __x)
#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE_SHIFT 16
#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE_MASK 0x00010000
#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, CMD_TRANSMISSION_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE_SHIFT 17
#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE_MASK 0x00020000
#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, WRITE_COMPLETED_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE_SHIFT 18
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE_MASK 0x00040000
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_COMPLETED_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE_SHIFT 19
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE_MASK 0x00080000
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE_SHIFT 20
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE_MASK 0x00100000
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_RECEIVED_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE_SHIFT 21
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE_MASK 0x00200000
#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_WITH_ERR_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE_SHIFT 22
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE_MASK 0x00400000
#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_RECEIVED_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE_SHIFT 23
#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE_MASK 0x00800000
#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TE_RECEIVED_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE_SHIFT 24
#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE_MASK 0x01000000
#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_COMPLETED_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE_SHIFT 25
#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE_MASK 0x02000000
#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_FINISHED_EDGE, __x)
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE_SHIFT 26
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE_MASK 0x04000000
#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_WITH_ERR_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL 0x000000FC
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN_SHIFT 0
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN_MASK 0x00000001
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_FIXED_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN_SHIFT 1
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN_MASK 0x00000002
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNCORRECTABLE_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN_SHIFT 2
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN_MASK 0x00000004
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_CHECKSUM_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN_SHIFT 3
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN_MASK 0x00000008
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNDECODABLE_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN_SHIFT 4
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN_MASK 0x00000010
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_RECEIVE_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN_SHIFT 5
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN_MASK 0x00000020
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_OVERSIZE_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN_SHIFT 6
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN_MASK 0x00000040
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_WRONG_LENGTH_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN_SHIFT 7
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN_MASK 0x00000080
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_MISSING_EOT_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN_SHIFT 8
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN_MASK 0x00000100
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_EOT_WITH_ERR_EN, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE_SHIFT 16
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE_MASK 0x00010000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_FIXED_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE_SHIFT 17
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE_MASK 0x00020000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNCORRECTABLE_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE_SHIFT 18
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE_MASK 0x00040000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_CHECKSUM_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE_SHIFT 19
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE_MASK 0x00080000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNDECODABLE_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE_SHIFT 20
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE_MASK 0x00100000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_RECEIVE_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE_SHIFT 21
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE_MASK 0x00200000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_OVERSIZE_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE_SHIFT 22
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE_MASK 0x00400000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_WRONG_LENGTH_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE_SHIFT 23
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE_MASK 0x00800000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_MISSING_EOT_EDGE, __x)
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE_SHIFT 24
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE_MASK 0x01000000
#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_EOT_WITH_ERR_EDGE, __x)
#define DSI_VID_MODE_STS_CTL 0x00000100
#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN_SHIFT 0
#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN_MASK 0x00000001
#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RUNNING_EN, __x)
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN_SHIFT 1
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN_MASK 0x00000002
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_DATA_EN, __x)
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN_SHIFT 2
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN_MASK 0x00000004
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_HSYNC_EN, __x)
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN_SHIFT 3
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN_MASK 0x00000008
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_VSYNC_EN, __x)
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN_SHIFT 4
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN_MASK 0x00000010
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_LENGTH_EN, __x)
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN_SHIFT 5
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN_MASK 0x00000020
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_HEIGHT_EN, __x)
#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN_SHIFT 6
#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN_MASK 0x00000040
#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_BURSTWRITE_EN, __x)
#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN_SHIFT 7
#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN_MASK 0x00000080
#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGWRITE_EN, __x)
#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN_SHIFT 8
#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN_MASK 0x00000100
#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGREAD_EN, __x)
#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN_SHIFT 9
#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN_MASK 0x00000200
#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_VRS_WRONG_LENGTH_EN, __x)
#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE_SHIFT 16
#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE_MASK 0x00010000
#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RUNNING_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE_SHIFT 17
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE_MASK 0x00020000
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_DATA_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE_SHIFT 18
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE_MASK 0x00040000
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_HSYNC_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE_SHIFT 19
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE_MASK 0x00080000
#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_VSYNC_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE_SHIFT 20
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE_MASK 0x00100000
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_LENGTH_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE_SHIFT 21
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE_MASK 0x00200000
#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_HEIGHT_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE_SHIFT 22
#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE_MASK 0x00400000
#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_BURSTWRITE_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE_SHIFT 23
#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE_MASK 0x00800000
#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGWRITE_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE_SHIFT 24
#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE_MASK 0x01000000
#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGREAD_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE_SHIFT 25
#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE_MASK 0x02000000
#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_VRS_WRONG_LENGTH_EDGE, __x)
#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE_SHIFT 26
#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE_MASK 0x04000000
#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RECOVERY_EDGE, __x)
#define DSI_TG_STS_CTL 0x00000104
#define DSI_TG_STS_CTL_TVG_STS_EN_SHIFT 0
#define DSI_TG_STS_CTL_TVG_STS_EN_MASK 0x00000001
#define DSI_TG_STS_CTL_TVG_STS_EN(__x) \
	DSI_VAL2REG(DSI_TG_STS_CTL, TVG_STS_EN, __x)
#define DSI_TG_STS_CTL_TBG_STS_EN_SHIFT 1
#define DSI_TG_STS_CTL_TBG_STS_EN_MASK 0x00000002
#define DSI_TG_STS_CTL_TBG_STS_EN(__x) \
	DSI_VAL2REG(DSI_TG_STS_CTL, TBG_STS_EN, __x)
#define DSI_TG_STS_CTL_TVG_STS_EDGE_SHIFT 16
#define DSI_TG_STS_CTL_TVG_STS_EDGE_MASK 0x00010000
#define DSI_TG_STS_CTL_TVG_STS_EDGE(__x) \
	DSI_VAL2REG(DSI_TG_STS_CTL, TVG_STS_EDGE, __x)
#define DSI_TG_STS_CTL_TBG_STS_EDGE_SHIFT 17
#define DSI_TG_STS_CTL_TBG_STS_EDGE_MASK 0x00020000
#define DSI_TG_STS_CTL_TBG_STS_EDGE(__x) \
	DSI_VAL2REG(DSI_TG_STS_CTL, TBG_STS_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL 0x00000108
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN_SHIFT 6
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN_MASK 0x00000040
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_1_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN_SHIFT 7
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN_MASK 0x00000080
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_2_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN_SHIFT 8
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN_MASK 0x00000100
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_1_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN_SHIFT 9
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN_MASK 0x00000200
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_2_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN_SHIFT 10
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN_MASK 0x00000400
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_1_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN_SHIFT 11
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN_MASK 0x00000800
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_2_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN_SHIFT 12
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN_MASK 0x00001000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_1_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN_SHIFT 13
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN_MASK 0x00002000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_2_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN_SHIFT 14
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN_MASK 0x00004000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_1_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN_SHIFT 15
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN_MASK 0x00008000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_2_EN, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE_SHIFT 22
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE_MASK 0x00400000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_1_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE_SHIFT 23
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE_MASK 0x00800000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_2_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE_SHIFT 24
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE_MASK 0x01000000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_1_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE_SHIFT 25
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE_MASK 0x02000000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_2_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE_SHIFT 26
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE_MASK 0x04000000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_1_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE_SHIFT 27
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE_MASK 0x08000000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_2_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE_SHIFT 28
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE_MASK 0x10000000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_1_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE_SHIFT 29
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE_MASK 0x20000000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_2_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE_SHIFT 30
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE_MASK 0x40000000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_1_EDGE, __x)
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE_SHIFT 31
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE_MASK 0x80000000
#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE(__x) \
	DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_2_EDGE, __x)
#define DSI_MCTL_MAIN_STS_CLR 0x00000110
#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR_SHIFT 0
#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR_MASK 0x00000001
#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, PLL_LOCK_CLR, __x)
#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR_SHIFT 1
#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR_MASK 0x00000002
#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, CLKLANE_READY_CLR, __x)
#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR_SHIFT 2
#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR_MASK 0x00000004
#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, DAT1_READY_CLR, __x)
#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR_SHIFT 3
#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR_MASK 0x00000008
#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, DAT2_READY_CLR, __x)
#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR_SHIFT 4
#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR_MASK 0x00000010
#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, HSTX_TO_ERR_CLR, __x)
#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR_SHIFT 5
#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR_MASK 0x00000020
#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, LPRX_TO_ERR_CLR, __x)
#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR_SHIFT 6
#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR_MASK 0x00000040
#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, CRS_UNTERM_PCK_CLR, __x)
#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR_SHIFT 7
#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR_MASK 0x00000080
#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, VRS_UNTERM_PCK_CLR, __x)
#define DSI_CMD_MODE_STS_CLR 0x00000114
#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR_SHIFT 0
#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR_MASK 0x00000001
#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_NO_TE_CLR, __x)
#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR_SHIFT 1
#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR_MASK 0x00000002
#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_TE_MISS_CLR, __x)
#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR_SHIFT 2
#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR_MASK 0x00000004
#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_SDI1_UNDERRUN_CLR, __x)
#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR_SHIFT 3
#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR_MASK 0x00000008
#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_SDI2_UNDERRUN_CLR, __x)
#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR_SHIFT 4
#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR_MASK 0x00000010
#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_UNWANTED_RD_CLR, __x)
#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR_SHIFT 5
#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR_MASK 0x00000020
#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, CSM_RUNNING_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR 0x00000118
#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR_SHIFT 0
#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR_MASK 0x00000001
#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, CMD_TRANSMISSION_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR_SHIFT 1
#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR_MASK 0x00000002
#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, WRITE_COMPLETED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR_SHIFT 2
#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR_MASK 0x00000004
#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TRIGGER_COMPLETED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR_SHIFT 3
#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR_MASK 0x00000008
#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, READ_COMPLETED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR_SHIFT 4
#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR_MASK 0x00000010
#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, ACKNOWLEDGE_RECEIVED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR_SHIFT 5
#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR_MASK 0x00000020
#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR_SHIFT 6
#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR_MASK 0x00000040
#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TRIGGER_RECEIVED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR_SHIFT 7
#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR_MASK 0x00000080
#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TE_RECEIVED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR_SHIFT 8
#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR_MASK 0x00000100
#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, BTA_COMPLETED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR_SHIFT 9
#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR_MASK 0x00000200
#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, BTA_FINISHED_CLR, __x)
#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR_SHIFT 10
#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR_MASK 0x00000400
#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, READ_COMPLETED_WITH_ERR_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR 0x0000011C
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR_SHIFT 0
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR_MASK 0x00000001
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_FIXED_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR_SHIFT 1
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR_MASK 0x00000002
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_UNCORRECTABLE_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR_SHIFT 2
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR_MASK 0x00000004
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_CHECKSUM_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR_SHIFT 3
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR_MASK 0x00000008
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_UNDECODABLE_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR_SHIFT 4
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR_MASK 0x00000010
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_RECEIVE_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR_SHIFT 5
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR_MASK 0x00000020
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_OVERSIZE_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR_SHIFT 6
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR_MASK 0x00000040
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_WRONG_LENGTH_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR_SHIFT 7
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR_MASK 0x00000080
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_MISSING_EOT_CLR, __x)
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR_SHIFT 8
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR_MASK 0x00000100
#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_EOT_WITH_ERR_CLR, __x)
#define DSI_VID_MODE_STS_CLR 0x00000120
#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR_SHIFT 0
#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR_MASK 0x00000001
#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, VSG_STS_CLR, __x)
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR_SHIFT 1
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR_MASK 0x00000002
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_DATA_CLR, __x)
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR_SHIFT 2
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR_MASK 0x00000004
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_HSYNC_CLR, __x)
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR_SHIFT 3
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR_MASK 0x00000008
#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_VSYNC_CLR, __x)
#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR_SHIFT 4
#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR_MASK 0x00000010
#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, REG_ERR_SMALL_LENGTH_CLR, __x)
#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR_SHIFT 5
#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR_MASK 0x00000020
#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, REG_ERR_SMALL_HEIGHT_CLR, __x)
#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR_SHIFT 6
#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR_MASK 0x00000040
#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_BURSTWRITE_CLR, __x)
#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR_SHIFT 7
#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR_MASK 0x00000080
#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_LONGWRITE_CLR, __x)
#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR_SHIFT 8
#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR_MASK 0x00000100
#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_LONGREAD_CLR, __x)
#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR_SHIFT 9
#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR_MASK 0x00000200
#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_VRS_WRONG_LENGTH_CLR, __x)
#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR_SHIFT 10
#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR_MASK 0x00000400
#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_CLR, VSG_RECOVERY_CLR, __x)
#define DSI_TG_STS_CLR 0x00000124
#define DSI_TG_STS_CLR_TVG_STS_CLR_SHIFT 0
#define DSI_TG_STS_CLR_TVG_STS_CLR_MASK 0x00000001
#define DSI_TG_STS_CLR_TVG_STS_CLR(__x) \
	DSI_VAL2REG(DSI_TG_STS_CLR, TVG_STS_CLR, __x)
#define DSI_TG_STS_CLR_TBG_STS_CLR_SHIFT 1
#define DSI_TG_STS_CLR_TBG_STS_CLR_MASK 0x00000002
#define DSI_TG_STS_CLR_TBG_STS_CLR(__x) \
	DSI_VAL2REG(DSI_TG_STS_CLR, TBG_STS_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR 0x00000128
#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR_SHIFT 6
#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR_MASK 0x00000040
#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_ESC_1_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR_SHIFT 7
#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR_MASK 0x00000080
#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_ESC_2_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR_SHIFT 8
#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR_MASK 0x00000100
#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_SYNCESC_1_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR_SHIFT 9
#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR_MASK 0x00000200
#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_SYNCESC_2_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR_SHIFT 10
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR_MASK 0x00000400
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONTROL_1_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR_SHIFT 11
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR_MASK 0x00000800
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONTROL_2_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR_SHIFT 12
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR_MASK 0x00001000
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP0_1_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR_SHIFT 13
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR_MASK 0x00002000
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP0_2_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR_SHIFT 14
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR_MASK 0x00004000
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP1_1_CLR, __x)
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR_SHIFT 15
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR_MASK 0x00008000
#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP1_2_CLR, __x)
#define DSI_MCTL_MAIN_STS_FLAG 0x00000130
#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG_SHIFT 0
#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG_MASK 0x00000001
#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, PLL_LOCK_FLAG, __x)
#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG_SHIFT 1
#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG_MASK 0x00000002
#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, CLKLANE_READY_FLAG, __x)
#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG_SHIFT 2
#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG_MASK 0x00000004
#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, DAT1_READY_FLAG, __x)
#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG_SHIFT 3
#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG_MASK 0x00000008
#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, DAT2_READY_FLAG, __x)
#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG_SHIFT 4
#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG_MASK 0x00000010
#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, HSTX_TO_ERR_FLAG, __x)
#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG_SHIFT 5
#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG_MASK 0x00000020
#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, LPRX_TO_ERR_FLAG, __x)
#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG_SHIFT 6
#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG_MASK 0x00000040
#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, CRS_UNTERM_PCK_FLAG, __x)
#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG_SHIFT 7
#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG_MASK 0x00000080
#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, VRS_UNTERM_PCK_FLAG, __x)
#define DSI_CMD_MODE_STS_FLAG 0x00000134
#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG_SHIFT 0
#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG_MASK 0x00000001
#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_NO_TE_FLAG, __x)
#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG_SHIFT 1
#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG_MASK 0x00000002
#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_TE_MISS_FLAG, __x)
#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG_SHIFT 2
#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG_MASK 0x00000004
#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_SDI1_UNDERRUN_FLAG, __x)
#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG_SHIFT 3
#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG_MASK 0x00000008
#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_SDI2_UNDERRUN_FLAG, __x)
#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG_SHIFT 4
#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG_MASK 0x00000010
#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_UNWANTED_RD_FLAG, __x)
#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG_SHIFT 5
#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG_MASK 0x00000020
#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG(__x) \
	DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, CSM_RUNNING_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG 0x00000138
#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG_SHIFT 0
#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG_MASK 0x00000001
#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, CMD_TRANSMISSION_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG_SHIFT 1
#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG_MASK 0x00000002
#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, WRITE_COMPLETED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG_SHIFT 2
#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG_MASK 0x00000004
#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TRIGGER_COMPLETED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG_SHIFT 3
#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG_MASK 0x00000008
#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, READ_COMPLETED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG_SHIFT 4
#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG_MASK 0x00000010
#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, ACKNOWLEDGE_RECEIVED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG_SHIFT 5
#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG_MASK 0x00000020
#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG_SHIFT 6
#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG_MASK 0x00000040
#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TRIGGER_RECEIVED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG_SHIFT 7
#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG_MASK 0x00000080
#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TE_RECEIVED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG_SHIFT 8
#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG_MASK 0x00000100
#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, BTA_COMPLETED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG_SHIFT 9
#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG_MASK 0x00000200
#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, BTA_FINISHED_FLAG, __x)
#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG_SHIFT 10
#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG_MASK 0x00000400
#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, READ_COMPLETED_WITH_ERR_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG 0x0000013C
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG_SHIFT 0
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG_MASK 0x00000001
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_FIXED_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG_SHIFT 1
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG_MASK 0x00000002
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_UNCORRECTABLE_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG_SHIFT 2
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG_MASK 0x00000004
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_CHECKSUM_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG_SHIFT 3
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG_MASK 0x00000008
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_UNDECODABLE_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG_SHIFT 4
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG_MASK 0x00000010
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_RECEIVE_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG_SHIFT 5
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG_MASK 0x00000020
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_OVERSIZE_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG_SHIFT 6
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG_MASK 0x00000040
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_WRONG_LENGTH_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG_SHIFT 7
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG_MASK 0x00000080
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_MISSING_EOT_FLAG, __x)
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG_SHIFT 8
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG_MASK 0x00000100
#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG(__x) \
	DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_EOT_WITH_ERR_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG 0x00000140
#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG_SHIFT 0
#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG_MASK 0x00000001
#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, VSG_STS_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG_SHIFT 1
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG_MASK 0x00000002
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_DATA_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG_SHIFT 2
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG_MASK 0x00000004
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_HSYNC_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG_SHIFT 3
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG_MASK 0x00000008
#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_VSYNC_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG_SHIFT 4
#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG_MASK 0x00000010
#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, REG_ERR_SMALL_LENGTH_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG_SHIFT 5
#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG_MASK 0x00000020
#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, REG_ERR_SMALL_HEIGHT_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG_SHIFT 6
#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG_MASK 0x00000040
#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_BURSTWRITE_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG_SHIFT 7
#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG_MASK 0x00000080
#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_LONGWRITE_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG_SHIFT 8
#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG_MASK 0x00000100
#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_LONGREAD_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG_SHIFT 9
#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG_MASK 0x00000200
#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_VRS_WRONG_LENGTH_FLAG, __x)
#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG_SHIFT 10
#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG_MASK 0x00000400
#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG(__x) \
	DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, VSG_RECOVERY_FLAG, __x)
#define DSI_TG_STS_FLAG 0x00000144
#define DSI_TG_STS_FLAG_TVG_STS_FLAG_SHIFT 0
#define DSI_TG_STS_FLAG_TVG_STS_FLAG_MASK 0x00000001
#define DSI_TG_STS_FLAG_TVG_STS_FLAG(__x) \
	DSI_VAL2REG(DSI_TG_STS_FLAG, TVG_STS_FLAG, __x)
#define DSI_TG_STS_FLAG_TBG_STS_FLAG_SHIFT 1
#define DSI_TG_STS_FLAG_TBG_STS_FLAG_MASK 0x00000002
#define DSI_TG_STS_FLAG_TBG_STS_FLAG(__x) \
	DSI_VAL2REG(DSI_TG_STS_FLAG, TBG_STS_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG 0x00000148
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG_SHIFT 6
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG_MASK 0x00000040
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_ESC_1_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG_SHIFT 7
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG_MASK 0x00000080
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_ESC_2_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG_SHIFT 8
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG_MASK 0x00000100
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_SYNCESC_1_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG_SHIFT 9
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG_MASK 0x00000200
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_SYNCESC_2_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG_SHIFT 10
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG_MASK 0x00000400
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONTROL_1_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG_SHIFT 11
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG_MASK 0x00000800
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONTROL_2_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG_SHIFT 12
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG_MASK 0x00001000
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP0_1_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG_SHIFT 13
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG_MASK 0x00002000
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP0_2_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG_SHIFT 14
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG_MASK 0x00004000
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP1_1_FLAG, __x)
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG_SHIFT 15
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG_MASK 0x00008000
#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG(__x) \
	DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP1_2_FLAG, __x)
#define DSI_DPHY_LANES_TRIM 0x00000150
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_SHIFT 0
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_MASK 0x00000003
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_DAT1, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1_SHIFT 2
#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1_MASK 0x00000004
#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_CD_OFF_DAT1, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1_SHIFT 3
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1_MASK 0x00000008
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_DAT1, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1_SHIFT 4
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1_MASK 0x00000010
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_DAT1, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1_SHIFT 5
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1_MASK 0x00000020
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_DAT1, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_SHIFT 6
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_MASK 0x000000C0
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_CLK, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_SHIFT 8
#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_MASK 0x00000300
#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_LP_RX_VIL_CLK, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_SHIFT 10
#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_MASK 0x00000C00
#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_LP_TX_SLEWRATE_CLK, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_SHIFT 12
#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_MASK 0x00001000
#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_81 0
#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90 1
#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_ENUM(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SPECS_90_81B, \
	DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_##__x)
#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SPECS_90_81B, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK_SHIFT 13
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK_MASK 0x00002000
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_CLK, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK_SHIFT 14
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK_MASK 0x00004000
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_CLK, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK_SHIFT 15
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK_MASK 0x00008000
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_CLK, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2_SHIFT 16
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2_MASK 0x00030000
#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_DAT2, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2_SHIFT 18
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2_MASK 0x00040000
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_DAT2, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2_SHIFT 19
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2_MASK 0x00080000
#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_DAT2, __x)
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2_SHIFT 20
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2_MASK 0x00100000
#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2(__x) \
	DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_DAT2, __x)
#define DSI_ID_REG 0x00000FF0
#define DSI_ID_REG_Y_SHIFT 0
#define DSI_ID_REG_Y_MASK 0x0000000F
#define DSI_ID_REG_Y(__x) \
	DSI_VAL2REG(DSI_ID_REG, Y, __x)
#define DSI_ID_REG_X_SHIFT 4
#define DSI_ID_REG_X_MASK 0x000000F0
#define DSI_ID_REG_X(__x) \
	DSI_VAL2REG(DSI_ID_REG, X, __x)
#define DSI_ID_REG_H_SHIFT 8
#define DSI_ID_REG_H_MASK 0x00000300
#define DSI_ID_REG_H(__x) \
	DSI_VAL2REG(DSI_ID_REG, H, __x)
#define DSI_ID_REG_PRODUCT_ID_SHIFT 10
#define DSI_ID_REG_PRODUCT_ID_MASK 0x0003FC00
#define DSI_ID_REG_PRODUCT_ID(__x) \
	DSI_VAL2REG(DSI_ID_REG, PRODUCT_ID, __x)
#define DSI_ID_REG_VENDOR_ID_SHIFT 18
#define DSI_ID_REG_VENDOR_ID_MASK 0xFFFC0000
#define DSI_ID_REG_VENDOR_ID(__x) \
	DSI_VAL2REG(DSI_ID_REG, VENDOR_ID, __x)
#define DSI_IP_CONF 0x00000FF4
#define DSI_IP_CONF_FIFO_SIZE_SHIFT 0
#define DSI_IP_CONF_FIFO_SIZE_MASK 0x0000003F
#define DSI_IP_CONF_FIFO_SIZE(__x) \
	DSI_VAL2REG(DSI_IP_CONF, FIFO_SIZE, __x)

#endif /* __DSILINK_REGS_H */