1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
|
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Joakim Axelsson <joakim.axelsson at stericsson.com>
* for ST-Ericsson.
*
* Origin: Most part are moved here from old board code for u8500.
*
* License terms: GNU General Public License (GPL), version 2.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/prcmu.h>
#ifdef CONFIG_ARCH_CPU_INIT
/* Old table to init ED version of db8500. Should be removed */
unsigned int addr_vall_arr[] = {
0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO Enable reqd only */
0x8011F008, 0x00001CFF, /* Clocks for HSI TODO Enable reqd only */
0x8000F000, 0x00007FFF, /* Clocks for I2C TODO Enable reqd only */
0x8000F008, 0x00007FFF, /* Clocks for I2C TODO Enable reqd only */
0x80157020, 0x00000150, /* I2C 48MHz clock */
0x8012F000, 0x00007FFF, /* Clocks for SD TODO Enable reqd only */
0x8012F008, 0x00007FFF, /* Clocks for SD TODO Enable reqd only */
0xA03DF000, 0x0000000D, /* Clock for MTU Timers */
0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */
0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */
0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */
0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */
0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */
0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */
0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */
0x801571E4, 0x0000000C, /* PRCMU settings for B2R2, PRCM_APE_RESETN_SET_REG */
0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */
0xA03FF000, 0x00000003, /* USB */
0xA03FF008, 0x00000001, /* USB */
0xA03FE00C, 0x00000000, /* USB */
0xA03FE020, 0x00000FFF, /* USB */
0xA03FE024, 0x00000000 /* USB */
};
static void init_regs(void)
{
/* FIXME Remove magic register array settings for ED also */
if (u8500_is_earlydrop()) {
unsigned i;
for (i = 0; i < ARRAY_SIZE(addr_vall_arr)/2; i++)
*((volatile unsigned int *)(addr_vall_arr[2 * i]))
= addr_vall_arr[(2 * i) + 1];
} else {
struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
/* Enable timers */
writel(1 << 17, &prcmu->tcr);
u8500_prcmu_enable(&prcmu->per1clk_mgt);
u8500_prcmu_enable(&prcmu->per2clk_mgt);
u8500_prcmu_enable(&prcmu->per3clk_mgt);
u8500_prcmu_enable(&prcmu->per5clk_mgt);
u8500_prcmu_enable(&prcmu->per6clk_mgt);
u8500_prcmu_enable(&prcmu->per7clk_mgt);
u8500_prcmu_enable(&prcmu->uartclk_mgt);
u8500_prcmu_enable(&prcmu->i2cclk_mgt);
u8500_prcmu_enable(&prcmu->sdmmcclk_mgt);
u8500_clock_enable(1, 9, -1); /* GPIO0 */
if (u8500_is_earlydrop())
u8500_clock_enable(2, 12, -1); /* GPIO1 */
else
u8500_clock_enable(2, 11, -1); /* GPIO1 */
u8500_clock_enable(3, 8, -1); /* GPIO2 */
u8500_clock_enable(5, 1, -1); /* GPIO3 */
u8500_clock_enable(3, 6, 6); /* UART2 */
u8500_clock_enable(3, 3, 3); /* I2C0 */
u8500_clock_enable(1, 5, 5); /* SDI0 */
u8500_clock_enable(2, 4, 2); /* SDI4 */
if (u8500_is_earlydrop())
u8500_clock_enable(7, 2, -1); /* MTU0 */
else if (cpu_is_u8500v1())
u8500_clock_enable(6, 7, -1); /* MTU0 */
else if (cpu_is_u8500v2())
u8500_clock_enable(6, 6, -1); /* MTU0 */
if (!u8500_is_earlydrop())
u8500_clock_enable(3, 4, 4); /* SDI2 */
/*
* Enabling clocks for all devices which are AMBA devices in the
* kernel. Otherwise they will not get probe()'d because the
* peripheral ID register will not be powered.
*/
/* XXX: some of these differ between ED/V1 */
u8500_clock_enable(1, 1, 1); /* UART1 */
u8500_clock_enable(1, 0, 0); /* UART0 */
u8500_clock_enable(3, 2, 2); /* SSP1 */
u8500_clock_enable(3, 1, 1); /* SSP0 */
u8500_clock_enable(2, 8, -1); /* SPI0 */
u8500_clock_enable(2, 5, 3); /* MSP2 */
}
}
/*
* SOC specific cpu init
*/
int arch_cpu_init(void)
{
if (u8500_is_earlydrop())
/* MTU timer clock always enabled (not clocked) */
writel(0x20000, PRCM_TCR);
icache_enable();
init_regs();
return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */
|
