summaryrefslogtreecommitdiff
path: root/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h
blob: a92479bc67a87a67662f5fb721a4790b175b80a7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
/* DO NOT EDIT THIS FILE
 * Automatically generated by generate-def-headers.xsl
 * DO NOT EDIT THIS FILE
 */

#ifndef __BFIN_DEF_ADSP_EDN_BF548_extended__
#define __BFIN_DEF_ADSP_EDN_BF548_extended__

#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
#define PORTA                          0xFFC014C4 /* GPIO Data Register */
#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
#define PORTB                          0xFFC014E4 /* GPIO Data Register */
#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
#define PORTC                          0xFFC01504 /* GPIO Data Register */
#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
#define PORTD                          0xFFC01524 /* GPIO Data Register */
#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
#define PORTE                          0xFFC01544 /* GPIO Data Register */
#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
#define PORTF                          0xFFC01564 /* GPIO Data Register */
#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
#define PORTG                          0xFFC01584 /* GPIO Data Register */
#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
#define PORTH                          0xFFC015A4 /* GPIO Data Register */
#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
#define PORTI                          0xFFC015C4 /* GPIO Data Register */
#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
#define CNT_STATUS                     0xFFC04208 /* Status Register  */
#define CNT_COMMAND                    0xFFC0420C /* Command Register */
#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
#define SDH_STATUS                     0xFFC03934 /* SDH Status */
#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
#define UART0_LCR                      0xFFC0040C /* Line Control Register */
#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
#define UART0_LSR                      0xFFC00414 /* Line Status Register */
#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
#define UART0_SCR                      0xFFC0041C /* Scratch Register */
#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
#define UART1_LCR                      0xFFC0200C /* Line Control Register */
#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
#define UART1_LSR                      0xFFC02014 /* Line Status Register */
#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
#define UART1_SCR                      0xFFC0201C /* Scratch Register */
#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
#define UART2_LCR                      0xFFC0210C /* Line Control Register */
#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
#define UART2_LSR                      0xFFC02114 /* Line Status Register */
#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
#define UART2_SCR                      0xFFC0211C /* Scratch Register */
#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
#define UART3_LCR                      0xFFC0310C /* Line Control Register */
#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
#define UART3_LSR                      0xFFC03114 /* Line Status Register */
#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
#define UART3_SCR                      0xFFC0311C /* Scratch Register */
#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
#define USB_FADDR                      0xFFC03C00 /* Function address register */
#define USB_POWER                      0xFFC03C04 /* Power management register */
#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
#define USB_FRAME                      0xFFC03C20 /* USB frame number */
#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */

#endif /* __BFIN_DEF_ADSP_EDN_BF548_extended__ */