diff options
| author | Swati Sharma <swati2.sharma@intel.com> | 2021-07-07 02:40:25 +0530 |
|---|---|---|
| committer | Swati Sharma <swati2.sharma@intel.com> | 2021-07-07 14:52:26 +0530 |
| commit | 390edfb703c346f06b0850db71bd3cc1342a3c02 (patch) | |
| tree | fea40219c5eb6157893fcb452c22570b03c57204 | |
| parent | 687589e76f787d26ee2b539e551a9be06bd41ce3 (diff) | |
tests/kms_cdclk: Fix CDCLK failure condition
Driver still works in a such way that we never reduce CDCLK, but always
only increase it. That was done in order to avoid continuous CDCLK switching,
So, in case if new CDCLK is 307200 and there is no change in CDCLK beacuse
of above stated driver optimization; pass the test else check lt condition.
TODO: Enhance this test to lower modes for all connectors in order to lower
CDCLK and get a proper DVFS behavior, along with the above mentioned
kernel change.
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
| -rw-r--r-- | tests/kms_cdclk.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/kms_cdclk.c b/tests/kms_cdclk.c index d2a9fa5f..818cbfd5 100644 --- a/tests/kms_cdclk.c +++ b/tests/kms_cdclk.c @@ -31,6 +31,7 @@ IGT_TEST_DESCRIPTION("Test cdclk features : crawling"); #define HDISPLAY_4K 3840 #define VDISPLAY_4K 2160 #define VREFRESH 60 +#define MAX_CDCLK_4K 307200 /* Test flags */ enum { @@ -228,7 +229,8 @@ static void test_mode_transition(data_t *data, enum pipe pipe, igt_output_t *out igt_info("CD clock frequency %d -> %d\n", cdclk_ref, cdclk_new); /* cdclk should bump */ - igt_assert_lt(cdclk_ref, cdclk_new); + if (cdclk_new != MAX_CDCLK_4K) + igt_assert_lt(cdclk_ref, cdclk_new); /* cleanup */ do_cleanup_display(display); |