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| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2017-05-08 16:14:01 +0100 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2017-05-08 16:14:01 +0100 |
| commit | 6e37f5b5c2a021249475476b7cbd8ad8a346a81c (patch) | |
| tree | d638259d5dce588e8d29fd25f9457b15dfc9458c | |
| parent | b56e1714137a48f5a3aab1e3e30f9f86169ac2f2 (diff) | |
gem_wsim: Fix implicit sync on last workload step
Last step has to be a batch for the implicit sync to make sense.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
| -rw-r--r-- | benchmarks/gem_wsim.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 15c4cedd..2da96040 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -1007,7 +1007,7 @@ run_workload(unsigned int id, struct workload *wrk, } } - if (run) + if (run && wrk->steps[wrk->nr_steps - 1].type == BATCH) gem_sync(fd, wrk->steps[wrk->nr_steps - 1].obj[0].handle); clock_gettime(CLOCK_MONOTONIC, &t_end); |