tests: add gem_tiled_pread_pwrite

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

3 files changed, 234 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
index 7e2dab0b..e055540f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,6 +5,8 @@ Makefile.in
 *.la
 *.lo
 *.o
+*.swo
+*.swp
 *~
 aclocal.m4
 autom4te.cache
@@ -60,6 +62,7 @@ tests/gem_vmap_blits
 tests/gem_tiled_blits
 tests/gem_tiled_fence_blits
 tests/gem_tiled_pread
+tests/gem_tiled_pread_pwrite
 tests/gem_unref_active_buffers
 tests/gem_bad_address
 tests/gem_bad_batch
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 7173afb9..750e3a46 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -28,6 +28,7 @@ TESTS_progs = \
 	gem_pwrite \
 	gem_pread_after_blit \
 	gem_tiled_pread \
+	gem_tiled_pread_pwrite \
 	gem_linear_blits \
 	gem_vmap_blits \
 	gem_tiled_blits \
diff --git a/tests/gem_tiled_pread_pwrite.c b/tests/gem_tiled_pread_pwrite.c
new file mode 100644
index 00000000..52b33579
--- /dev/null
+++ b/tests/gem_tiled_pread_pwrite.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+/** @file gem_tiled_pread_pwrite.c
+ *
+ * This is a test of pread's behavior on tiled objects with respect to the
+ * reported swizzling value.
+ *
+ * The goal is to exercise the slow_bit17_copy path for reading on bit17
+ * machines, but will also be useful for catching swizzling value bugs on
+ * other systems.
+ */
+
+/*
+ * Testcase: Test swizzling by testing pwrite does the invers of pread
+ *
+ * Together with the explicit pread testcase, this should cover our swizzle
+ * handling.
+ *
+ * Note that this test will use swap in an effort to test all of ram.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include "drm.h"
+#include "i915_drm.h"
+#include "drmtest.h"
+#include "intel_gpu_tools.h"
+
+#define WIDTH 512
+#define HEIGHT 512
+static uint32_t linear[WIDTH * HEIGHT];
+static uint32_t current_tiling_mode;
+
+#define PAGE_SIZE 4096
+
+static uint32_t
+gem_create(int fd, int size)
+{
+	struct drm_i915_gem_create create;
+
+	create.handle = 0;
+	create.size = size;
+	(void)drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
+
+	return create.handle;
+}
+
+static void *gem_mmap(int fd, uint32_t handle, int size, int prot)
+{
+	struct drm_i915_gem_mmap_gtt mmap_arg;
+	void *ptr;
+
+	mmap_arg.handle = handle;
+	if (drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg))
+		return NULL;
+
+	ptr = mmap(0, size, prot, MAP_SHARED, fd, mmap_arg.offset);
+	if (ptr == MAP_FAILED)
+		ptr = NULL;
+
+	return ptr;
+}
+
+static int gem_write(int fd,
+		     uint32_t handle, uint32_t offset,
+		     const void *src, int length)
+{
+	struct drm_i915_gem_pwrite pwrite;
+
+	pwrite.handle = handle;
+	pwrite.offset = offset;
+	pwrite.size = length;
+	pwrite.data_ptr = (uintptr_t)src;
+	return drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
+}
+
+static void
+gem_read(int fd, uint32_t handle, int offset, int length, void *buf)
+{
+	struct drm_i915_gem_pread pread;
+	int ret;
+
+	pread.handle = handle;
+	pread.offset = offset;
+	pread.size = length;
+	pread.data_ptr = (uintptr_t)buf;
+	ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_PREAD, &pread);
+	assert(ret == 0);
+}
+
+static void
+gem_set_tiling(int fd, uint32_t handle, int tiling)
+{
+	struct drm_i915_gem_set_tiling set_tiling;
+	int ret;
+
+	do {
+		set_tiling.handle = handle;
+		set_tiling.tiling_mode = tiling;
+		set_tiling.stride = WIDTH * sizeof(uint32_t);
+
+		ret = ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
+	} while (ret == -1 && (errno == EINTR || errno == EAGAIN));
+}
+
+static void
+gem_get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzle)
+{
+	struct drm_i915_gem_get_tiling get_tiling;
+	int ret;
+
+	memset(&get_tiling, 0, sizeof(get_tiling));
+	get_tiling.handle = handle;
+
+	ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
+	assert(ret == 0);
+
+	*tiling = get_tiling.tiling_mode;
+	*swizzle = get_tiling.swizzle_mode;
+}
+
+static uint32_t
+create_bo_and_fill(int fd)
+{
+	uint32_t handle;
+	uint32_t *data;
+	int i;
+
+	handle = gem_create(fd, sizeof(linear));
+	gem_set_tiling(fd, handle, current_tiling_mode);
+
+	/* Fill the BO with dwords starting at start_val */
+	data = gem_mmap(fd, handle, sizeof(linear), PROT_READ | PROT_WRITE);
+	for (i = 0; i < WIDTH*HEIGHT; i++)
+		data[i] = i;
+	munmap(data, sizeof(linear));
+
+	return handle;
+}
+
+static uint32_t
+create_bo(int fd)
+{
+	uint32_t handle;
+
+	handle = gem_create(fd, sizeof(linear));
+	gem_set_tiling(fd, handle, current_tiling_mode);
+
+	return handle;
+}
+
+int
+main(int argc, char **argv)
+{
+	int fd;
+	uint32_t *data;
+	int i, j;
+	uint32_t tiling, swizzle;
+	uint32_t handle, handle_target;
+	uint32_t devid;
+	int count;
+	
+
+	fd = drm_open_any();
+	count = intel_get_total_ram_mb() * 9 / 10;
+
+	devid = intel_get_drm_devid(fd);
+
+	for (i = 0; i < count/2; i++) {
+		current_tiling_mode = I915_TILING_X;
+
+		handle = create_bo_and_fill(fd);
+		gem_get_tiling(fd, handle, &tiling, &swizzle);
+
+		gem_read(fd, handle, 0, sizeof(linear), linear);
+
+		handle_target = create_bo(fd);
+		gem_write(fd, handle_target, 0, linear, sizeof(linear));
+
+		/* Check the target bo's contents. */
+		data = gem_mmap(fd, handle_target, sizeof(linear), PROT_READ | PROT_WRITE);
+		for (j = 0; j < WIDTH*HEIGHT; j++)
+			if (data[j] != j) {
+				fprintf(stderr, "mismatch at %i: %i\n",
+						j, data[j]);
+				exit(1);
+			}
+		munmap(data, sizeof(linear));
+
+		/* Leak both bos so that we use all of system mem! */
+	}
+
+	close(fd);
+
+	return 0;
+}