diff options
author | Damien Lespiau <damien.lespiau@intel.com> | 2013-01-26 23:55:01 +0000 |
---|---|---|
committer | Damien Lespiau <damien.lespiau@intel.com> | 2013-03-04 15:54:40 +0000 |
commit | 95b12082d272699ade246f625d4fa231c3ae5204 (patch) | |
tree | cd52fb538a5b79c2353272eea0ecc731029388b5 /assembler | |
parent | d70e9f824f6f837614bbc2714c5ccc5f77d2c539 (diff) |
assembler: Add a check for when ExecSize and width are 1
Another check (that we hit if we try to use brw_set_src0()). Again,
protect it with the -W option.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Diffstat (limited to 'assembler')
-rw-r--r-- | assembler/gram.y | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/assembler/gram.y b/assembler/gram.y index 96bc7974..b3578e82 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -261,8 +261,10 @@ static bool validate_src_reg(struct brw_instruction *insn, YYLTYPE *location) { int hstride_for_reg[] = {0, 1, 2, 4}; + int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256}; int width_for_reg[] = {1, 2, 4, 8, 16}; - int width, hstride; + int execsize_for_reg[] = {1, 2, 4, 8, 16, 32}; + int width, hstride, vstride, execsize; if (reg.file == BRW_IMMEDIATE_VALUE) return true; @@ -277,9 +279,20 @@ static bool validate_src_reg(struct brw_instruction *insn, assert(reg.hstride >= 0 && reg.hstride < ARRAY_SIZE(hstride_for_reg)); hstride = hstride_for_reg[reg.hstride]; + if (reg.vstride == 0xf) { + vstride = -1; + } else { + assert(reg.vstride >= 0 && reg.vstride < ARRAY_SIZE(vstride_for_reg)); + vstride = vstride_for_reg[reg.vstride]; + } + assert(reg.width >= 0 && reg.width < ARRAY_SIZE(width_for_reg)); width = width_for_reg[reg.width]; + assert(insn->header.execution_size >= 0 && + insn->header.execution_size < ARRAY_SIZE(execsize_for_reg)); + execsize = execsize_for_reg[insn->header.execution_size]; + /* Register Region Restrictions */ /* D. If Width = 1, HorzStride must be 0 regardless of the values of @@ -292,6 +305,17 @@ static bool validate_src_reg(struct brw_instruction *insn, warn(ALL, location, "region width is 1 but horizontal stride is %d " " (should be 0)\n", hstride); + /* E. If ExecSize = Width = 1, both VertStride and HorzStride must be 0. + * This defines a scalar. */ + if (execsize == 1 && width == 1) { + if (hstride != 0) + warn(ALL, location, "execution size and region width are 1 but " + "horizontal stride is %d (should be 0)\n", hstride); + if (vstride != 0) + warn(ALL, location, "execution size and region width are 1 but " + "vertical stride is %d (should be 0)\n", vstride); + } + return true; } |