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authorDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>2018-07-12 01:09:40 -0700
committerRodrigo Vivi <rodrigo.vivi@intel.com>2018-07-13 15:29:56 -0700
commit86b1db1eb0041411f1c13da6cbe135f3b4ad5bbe (patch)
treede15899cac92a0770d452f5f9b70eab14a95c0c0 /benchmarks/gem_blt.c
parent140a67c13aad2595ee6c72e41d14d35a793158b5 (diff)
tests/frontbuffer_tracking: Do not test sink crc
eDP sink crc reads use vblank interrupts that cause PSR exit and therefore makes them unsuitable for PSR testing. Besides that, reading sink CRC via the AUX channel for testing when the HW also is most likely is going to be using AUX channel is a recipe for inconsistent test results. Thirdly, CRC's have been seen to be noisy or vary across sinks for the same driver and test code. We tradeoff the ability to validate what the sink is displaying for correctness. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'benchmarks/gem_blt.c')
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