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authorTvrtko Ursulin <tvrtko.ursulin@intel.com>2018-07-19 10:28:23 +0100
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>2018-09-14 12:48:32 +0100
commit218fa79fdcf0d47dfd34eccbaf827d4224ed28d8 (patch)
treeb1b29a55e89d485d73df7972a3172da97d52115e /benchmarks/gem_wsim.c
parent468febc4c746f168e885e0d662ec3adb0cca60f6 (diff)
trace.pl: Fix frequency timeline
Frequency timeline needs to be finished with an entry spanning to the end of known time so that the last known frequency is displayed. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'benchmarks/gem_wsim.c')
0 files changed, 0 insertions, 0 deletions