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authorChris Wilson <chris@chris-wilson.co.uk>2019-01-22 23:17:51 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2019-03-26 10:37:58 +0000
commit601b3ed82b80b45f7b60a620e6609eb0a4b721df (patch)
treeeb6815821915c1c75ce21064313615f15c3a8e1b /include/drm-uapi/exynos_drm.h
parent2551ed1864985d2fe1c250337f86c7b2bc670c67 (diff)
i915/gem_sync: Make switch-default asymmetric
To make the demonstration of the cheeky preemption more impactful, make the second context a nop to contrast the first being 1024 MI_STORE_DWORD_IMM. Then if we execute and wait on the second context before executing the first, the client latency is even more drastically reduced. To more clearly show any effect on wait reordering, measure the alternative path and present both. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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