lib: Apply magic clflush serialisation

On Baytrail, Braswell and Atoms beyond we see an issue where the mfence
is insufficient to force the cacheline to be coherent (i.e. such that
writes from the GPU are visible by the CPU after the call to clflush). A
second clflush is ordered with an earlier clflush to the same address
and this appears sufficient to give the coherency required for GPU/CPU
interop.

Testcase: igt/gem_exec_flush
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Akash Goel <akash.goel@intel.com>

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