diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2014-12-03 19:05:09 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2014-12-04 10:17:16 +0800 |
| commit | 10c6ad3805489819047ee24379bb1e7ab08ead1d (patch) | |
| tree | 8d2249f68e6749b46dd104ad9fc8217edb1dd490 /shaders | |
| parent | 106f0bf965ac5ba8e5553e3e1b39396750bedc74 (diff) | |
lib: Add GPGPU fill
This is to add fill operation using GPGPU pipeline which is similar to
current media fill. This can be used to simply verify GPGPU pipeline
and help to enable it on newer HW, currently it works on Gen7 only and
will add support on later platform.
Now this sets very simply thread group dispatch for one thread per
thread group on SIMD16 dispatch. So the fill shader just uses thread
group ID for buffer offset.
v2: No new fill func typedef but adapt to igt_fillfunc_t.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'shaders')
| -rw-r--r-- | shaders/gpgpu/README | 4 | ||||
| -rw-r--r-- | shaders/gpgpu/gpgpu_fill.gxa | 51 |
2 files changed, 55 insertions, 0 deletions
diff --git a/shaders/gpgpu/README b/shaders/gpgpu/README new file mode 100644 index 00000000..3bf328ad --- /dev/null +++ b/shaders/gpgpu/README @@ -0,0 +1,4 @@ + +Commands used to generate the shader on gen7 +$> m4 gpgpu_fill.gxa > gpgpu_fill.gxm +$> intel-gen4asm -g 7 -o <output> gpgpu_fill.gxm diff --git a/shaders/gpgpu/gpgpu_fill.gxa b/shaders/gpgpu/gpgpu_fill.gxa new file mode 100644 index 00000000..fc309f36 --- /dev/null +++ b/shaders/gpgpu/gpgpu_fill.gxa @@ -0,0 +1,51 @@ +/* + * Registers + * g0 -- header + * g1 -- constant + * g2 -- calculate X/Y offset + * g4-g12 payload for write message + */ +define(`ORIG', `g2.0<2,2,1>UD') +define(`ORIG_X', `g2.0<1>UD') +define(`ORIG_Y', `g2.4<1>UD') +define(`COLOR', `g1.0') +define(`COLORUB', `COLOR<0,1,0>UB') +define(`COLORUD', `COLOR<0,1,0>UD') +define(`X', `g0.4<0,1,0>UD') +define(`Y', `g0.24<0,1,0>UD') + +mov(4) COLOR<1>UB COLORUB {align1}; + +/* WRITE */ +/* count thread group ID for X/Y offset */ +mul(1) ORIG_X X 0x10UD {align1}; +mov(1) ORIG_Y Y {align1}; +mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1}; +mov(2) g4.0<1>UD ORIG {align1}; +/* Normal mode: for block height 1 row and block width 16 bytes */ +mov(1) g4.8<1>UD 0x0000000fUD {align1}; + +mov(16) g5.0<1>UD COLORUD {align1 compr}; +mov(16) g7.0<1>UD COLORUD {align1 compr}; +mov(16) g9.0<1>UD COLORUD {align1 compr}; +mov(16) g11.0<1>UD COLORUD {align1 compr}; + +/* + * comment out the following instruction on Gen7 + * write(0, 0, 10, 12) + * 10: media_block_write + * 12: data cache data port 1 + */ +send(16) 4 acc0<1>UW null write(0, 0, 10, 12) mlen 9 rlen 0 {align1}; + +/* + * uncomment the following instruction on Gen7 + * write(0, 0, 10, 0) + * 10: media_block_write + * 0: reander cache data port + */ +/* send(16) 4 acc0<1>UW null write(0, 0, 10, 0) mlen 9 rlen 0 {align1}; */ + +/* EOT */ +mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; +send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |