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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-03 18:57:40 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-03 19:01:30 +0200
commit630dd4087d50f6db3b9d4e9fc42ca159b6d39446 (patch)
tree95a6a5a1fceffc26995af21d48622f928e4d1ed7 /tests/gem_cacheing.c
parent2d431fd6b6430261334f50a9dbba5bd473ded449 (diff)
tests/gem_caching: only disable on vintage i965g/gm
Hooray for confusing macros! Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tests/gem_cacheing.c')
-rw-r--r--tests/gem_cacheing.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/tests/gem_cacheing.c b/tests/gem_cacheing.c
index c49932f2..ccc8ef14 100644
--- a/tests/gem_cacheing.c
+++ b/tests/gem_cacheing.c
@@ -115,14 +115,20 @@ int main(int argc, char **argv)
fd = drm_open_any();
- if (!gem_has_cacheing(fd))
+ if (!gem_has_cacheing(fd)) {
+ printf("no set_caching support detected\n");
return 77;
+ }
devid = intel_get_drm_devid(fd);
if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
flags &= ~TEST_READ;
- if (IS_965(devid)) /* chipset is completely fubar */
+ if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
+ /* chipset is completely fubar */
+ printf("coherency broken on i965g/gm\n");
flags = 0;
+ }
+
if (flags == 0)
return 77;