diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2016-10-21 10:52:47 +0100 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2016-10-21 10:53:55 +0100 |
commit | 6939e0cbff3cfed4c2afd9ac6936cabeeb022e1a (patch) | |
tree | 2ce73f5a0b5565fe50aa326e018eb15c276171eb /tests/gem_exec_parse.c | |
parent | 800aedb69b3aefbbd0576834917c06e1addfe769 (diff) |
igt/gem_exec_parse: Double check hw validation
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tests/gem_exec_parse.c')
-rw-r--r-- | tests/gem_exec_parse.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c index 8a3af775..a39db3e0 100644 --- a/tests/gem_exec_parse.c +++ b/tests/gem_exec_parse.c @@ -385,6 +385,29 @@ static void exec_batch_chained(int fd, uint32_t cmd_bo, uint32_t *cmds, gem_close(fd, target_bo); } +static void stray_lri(int fd, uint32_t handle) +{ + /* Ideally this would test all once whitelisted registers */ + uint32_t lri[] = { + MI_LOAD_REGISTER_IMM, + OACONTROL, + 0x31337000, + MI_BATCH_BUFFER_END, + }; + int err; + + igt_assert_eq_u32(intel_register_read(OACONTROL), 0xdeadbeef); + + err = __exec_batch(fd, handle, lri, sizeof(lri), I915_EXEC_RENDER); + if (err == -EINVAL) + return; + + igt_assert_eq(err, 0); + gem_sync(fd, handle); + + igt_assert_eq_u32(intel_register_read(OACONTROL), 0xdeadbeef); +} + uint32_t handle; int fd; @@ -463,6 +486,23 @@ igt_main -EINVAL); } + igt_subtest_group { + igt_fixture { + intel_register_access_init(intel_get_pci_device(), 0); + + intel_register_write(OACONTROL, 0xdeadbeef); + igt_assert_eq_u32(intel_register_read(OACONTROL), 0xdeadbeef); + } + + igt_subtest("basic-stray-lri") + stray_lri(fd, handle); + + igt_fixture { + intel_register_write(OACONTROL, 0); + intel_register_access_fini(); + } + } + igt_subtest("registers") { uint32_t lri_bad[] = { MI_LOAD_REGISTER_IMM, |