diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2019-01-07 12:35:27 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-01-10 23:29:40 +0000 |
| commit | 478452fece3997dfacaa4d6babe6b8bf6fef784f (patch) | |
| tree | 11dcbd5cb252225f2af522ff55d44110c580c293 /tests/i915/gem_ctx_isolation.c | |
| parent | 93f0ad4b835e56dd02f2b7520433e015f28bb571 (diff) | |
i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET
On Skylake, BB_OFFSET seems to be unstable. Since this is an
offset into the batch at the time of CS execution, it should be actively
written to as we read from the register so allow it a qword of
discrepancy (since the CS should be reading in qwords). This still
allows us to detect dirt across the rest of the register field, should
that be required.
v2: restrict ignore_bits to only BIT(2) that we see fluctuate in testing
(Antonio)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
Diffstat (limited to 'tests/i915/gem_ctx_isolation.c')
| -rw-r--r-- | tests/i915/gem_ctx_isolation.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index 058cf3ec..839d49ad 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -96,7 +96,7 @@ static const struct named_register { { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 }, { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 }, { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 }, - { "BB_OFFSET", GEN8, RCS0, 0x2158 }, + { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 }, { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c }, { "CS_GPR", GEN8, RCS0, 0x2600, 32 }, { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 }, |