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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2017-12-08 15:14:15 +0000 |
|---|---|---|
| committer | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2017-12-08 17:22:38 +0000 |
| commit | 4dce16890fd3c9894f8b855a85fd169bf7faead2 (patch) | |
| tree | f9746d3178042f61d958ccd549737e0d9df52db6 /tests/kms_rotation_crc.c | |
| parent | d56a18576ee471a0e7bb065b3c109556f80d8d3e (diff) | |
igt/perf: Read RCS0 timestamp directly
On Haswell, at least, MI_REPORT_PERF_COUNT is not flushed by the
PIPECONTROL surrounding the batch. (In theory, before the breadcrumb is
updated the CPU's view of memory is coherent with the GPU, i.e. all
writes have landed and are visible to userspace. This does not appear to
be the case for MI_REPORT_PERF_COUNT.) This makes it an unreliable
method for querying the timestamp, so use MI_STORE_REGISTER_MEM instead.
Testcase: igt/perf/oa-exponents
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Diffstat (limited to 'tests/kms_rotation_crc.c')
0 files changed, 0 insertions, 0 deletions