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| author | Brad Volkin <bradley.d.volkin@intel.com> | 2014-01-29 13:58:27 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-25 14:17:03 +0100 |
| commit | 1b1321cde7b60d413b425f358e6ecd2bd47b90fb (patch) | |
| tree | 4f7ad720251c8285b8b09b0466134fc100d2e1ca /tests | |
| parent | 59cb7e105e0ba3d4b1c3a378d962ec270eaa3700 (diff) | |
tests/gem_exec_parse: Add tests for register whitelist
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/gem_exec_parse.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c index ebf71161..48fde25e 100644 --- a/tests/gem_exec_parse.c +++ b/tests/gem_exec_parse.c @@ -141,6 +141,7 @@ int fd; #define MI_ARB_ON_OFF (0x8 << 23) #define MI_DISPLAY_FLIP ((0x14 << 23) | 1) +#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1) #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) #define PIPE_CONTROL_QW_WRITE (1<<14) @@ -213,6 +214,31 @@ igt_main -EINVAL)); } + igt_subtest("registers") { + uint32_t lri_bad[] = { + MI_LOAD_REGISTER_IMM, + 0, // disallowed register address + 0x12000000, + MI_BATCH_BUFFER_END, + }; + uint32_t lri_ok[] = { + MI_LOAD_REGISTER_IMM, + 0x5280, // allowed register address (SO_WRITE_OFFSET[0]) + 0x1, + MI_BATCH_BUFFER_END, + }; + igt_assert( + exec_batch(fd, handle, + lri_bad, sizeof(lri_bad), + I915_EXEC_RENDER, + -EINVAL)); + igt_assert( + exec_batch(fd, handle, + lri_ok, sizeof(lri_ok), + I915_EXEC_RENDER, + 0)); + } + igt_fixture { gem_close(fd, handle); |